ETISS 0.8.0
ExtendableTranslatingInstructionSetSimulator(version0.8.0)
RISCV64Arch.cpp
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1 // This file was generated on Mon Aug 03 15:02:40 CEST 2020
2 // If necessary please modify this file according to the instructions
3 // Contact: eda@tum
4 
5 /*********************************************************************************************************************************
6 
7 * Modification guidelines:
8 
9  1. The initial value of SP register should be initialized by ctr0.S/board.S. If not, it could be initialized
10  through utility class etiss::VirtualStruct::Field.
11 
12  2. Debug mode print out all assignment results. GDB in 8 is prefered.
13 
14  3. Manually copy the content in bracket ["return ETISS_RETURNCODE_CPUFINISHED; \n"] to terminating instruction,
15  otherwise the emulation can not be ended.
16 
17  4. If subset of encoding error occurs, it means the format of the encoding in the input model was not appropriate
18 
19  5. If the PC register points to wrong address, please notice that some assembly may cause branch operation
20  implicitly such as "MOV Rd Rn" in ARMv6-M
21 
22  6. If a variable is the result of dynamic slicing such as, var_1 = var_2<Hshift-1..Lshift-2>, the size would be
23  calculated during process (if possible), otherwise it is assumed to be the register size. Problems may occur when
24  var_1 encounters bit manipulation such as "~" due to bit expansion. To change the nml model with explicit slicing
25  e.g var_1 = val_2<3..0> or avoid bit manipulation for dynamic sliced variable. Otherwise, you have to manually
26  correct it.
27 
28  7. Implementation dependent functionalities such as exception handling should be manully added. Corresponding interfaces
29  are provided in RISCV64ArchSpecificImp.h
30 
31  8. RISCV64GDBCore.h provides the GDBCore class to support gdb flavor debugging feature, modify iy if in need.
32 
33  *********************************************************************************************************************************/
34 
35 #include "RISCV64Arch.h"
36 #include "RISCV64ArchSpecificImp.h"
37 
38 #define RISCV64_DEBUG_CALL 0
39 #define RISCV64_Pipeline1 0
40 #define RISCV64_Pipeline2 0
41 using namespace etiss ;
42 using namespace etiss::instr ;
43 
44 // Debug
45 int32_t tlb_overlap_handler(int32_t fault, MMU *mmu, uint64_t vma, MM_ACCESS access)
46 {
47  return etiss::RETURNCODE::NOERROR;
48 }
49 
50 RISCV64Arch::RISCV64Arch():CPUArch("RISCV64")
51 {
52  headers_.insert("Arch/RISCV64/RISCV64.h");
53 }
54 
55 const std::set<std::string> & RISCV64Arch::getListenerSupportedRegisters()
56 {
57  return listenerSupportedRegisters_;
58 }
59 
60 ETISS_CPU * RISCV64Arch::newCPU()
61 {
62  ETISS_CPU * ret = (ETISS_CPU *) new RISCV64() ;
63  resetCPU (ret, 0);
64  return ret;
65 }
66 
67 void RISCV64Arch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
68 {
69  memset (cpu, 0, sizeof(RISCV64));
70  RISCV64 * riscv64cpu = (RISCV64 *) cpu;
71 
72  if (startpointer) cpu->instructionPointer = *startpointer;
73  else cpu->instructionPointer = 0x0; // reference to manual
74  cpu->mode = 1;
75  cpu->cpuTime_ps = 0;
76  cpu->cpuCycleTime_ps = etiss::cfg(getLastAssignedCoreName())
77  .get<uint32_t>("arch.cpu_cycle_time_ps", 31250); // original: 31250; // 32MHz
78  #if RISCV64_Pipeline1 || RISCV64_Pipeline2
79  //Initialize resources measurements
80  cpu->resources[0] = "I_RAM";
81  cpu->resources[1] = "IF";
82  cpu->resources[2] = "ID";
83  cpu->resources[3] = "Multiplier1";
84  cpu->resources[4] = "ReadPorts";
85  cpu->resources[5] = "ALU";
86  cpu->resources[6] = "D_RAM";
87  cpu->resources[7] = "WB";
88  cpu->resources[8] = "Multiplier2";
89  for(int i = 0; i < 9; i = i + 1){
90  cpu->resourceUsages[i] = 0;
91  cpu->cycles[i] = 0;
92  }
93  #endif
94 
95  // Instantiate the pointers in order to avoid segmentation fault
96  for(int i = 0; i < 32; i ++)
97  {
98  riscv64cpu->ins_X[i] = 0;
99  riscv64cpu->X[i] = & riscv64cpu->ins_X[i];
100  }
101 
102  // Initialize the registers and state flags;
103  riscv64cpu->ZERO = 0;
104  riscv64cpu->X[0] = & (riscv64cpu->ZERO);
105  riscv64cpu->RA = 0;
106  riscv64cpu->X[1] = & (riscv64cpu->RA);
107  riscv64cpu->SP = 0;
108  riscv64cpu->X[2] = & (riscv64cpu->SP);
109  riscv64cpu->GP = 0;
110  riscv64cpu->X[3] = & (riscv64cpu->GP);
111  riscv64cpu->TP = 0;
112  riscv64cpu->X[4] = & (riscv64cpu->TP);
113  riscv64cpu->T0 = 0;
114  riscv64cpu->X[5] = & (riscv64cpu->T0);
115  riscv64cpu->T1 = 0;
116  riscv64cpu->X[6] = & (riscv64cpu->T1);
117  riscv64cpu->T2 = 0;
118  riscv64cpu->X[7] = & (riscv64cpu->T2);
119  riscv64cpu->S0 = 0;
120  riscv64cpu->X[8] = & (riscv64cpu->S0);
121  riscv64cpu->S1 = 0;
122  riscv64cpu->X[9] = & (riscv64cpu->S1);
123  riscv64cpu->A0 = 0;
124  riscv64cpu->X[10] = & (riscv64cpu->A0);
125  riscv64cpu->A1 = 0;
126  riscv64cpu->X[11] = & (riscv64cpu->A1);
127  riscv64cpu->A2 = 0;
128  riscv64cpu->X[12] = & (riscv64cpu->A2);
129  riscv64cpu->A3 = 0;
130  riscv64cpu->X[13] = & (riscv64cpu->A3);
131  riscv64cpu->A4 = 0;
132  riscv64cpu->X[14] = & (riscv64cpu->A4);
133  riscv64cpu->A5 = 0;
134  riscv64cpu->X[15] = & (riscv64cpu->A5);
135  riscv64cpu->A6 = 0;
136  riscv64cpu->X[16] = & (riscv64cpu->A6);
137  riscv64cpu->A7 = 0;
138  riscv64cpu->X[17] = & (riscv64cpu->A7);
139  riscv64cpu->S2 = 0;
140  riscv64cpu->X[18] = & (riscv64cpu->S2);
141  riscv64cpu->S3 = 0;
142  riscv64cpu->X[19] = & (riscv64cpu->S3);
143  riscv64cpu->S4 = 0;
144  riscv64cpu->X[20] = & (riscv64cpu->S4);
145  riscv64cpu->S5 = 0;
146  riscv64cpu->X[21] = & (riscv64cpu->S5);
147  riscv64cpu->S6 = 0;
148  riscv64cpu->X[22] = & (riscv64cpu->S6);
149  riscv64cpu->S7 = 0;
150  riscv64cpu->X[23] = & (riscv64cpu->S7);
151  riscv64cpu->S8 = 0;
152  riscv64cpu->X[24] = & (riscv64cpu->S8);
153  riscv64cpu->S9 = 0;
154  riscv64cpu->X[25] = & (riscv64cpu->S9);
155  riscv64cpu->S10 = 0;
156  riscv64cpu->X[26] = & (riscv64cpu->S10);
157  riscv64cpu->S11 = 0;
158  riscv64cpu->X[27] = & (riscv64cpu->S11);
159  riscv64cpu->T3 = 0;
160  riscv64cpu->X[28] = & (riscv64cpu->T3);
161  riscv64cpu->T4 = 0;
162  riscv64cpu->X[29] = & (riscv64cpu->T4);
163  riscv64cpu->T5 = 0;
164  riscv64cpu->X[30] = & (riscv64cpu->T5);
165  riscv64cpu->T6 = 0;
166  riscv64cpu->X[31] = & (riscv64cpu->T6);
167  for (int i = 0; i<32 ;i++){
168  riscv64cpu->F[i] = 0;
169  }
170  riscv64cpu->FCSR = 0;
171  for (int i = 0; i<4096 ;i++){
172  riscv64cpu->CSR[i] = 0;
173  }
174  riscv64cpu->CSR[0] = 15;
175  riscv64cpu->CSR[256] = 15;
176  riscv64cpu->CSR[768] = 15;
177  riscv64cpu->CSR[260] = 4294967295;
178  riscv64cpu->CSR[769] = 0x800000000014112D;
179  riscv64cpu->CSR[3088] = 3;
180  for (int i = 0; i<4 ;i++){
181  riscv64cpu->FENCE[i] = 0;
182  }
183  riscv64cpu->RES = 0;
184 
185  /* >>> manually added code section */
186  riscv64cpu->CSR[0x304] = (0xFFFFFFFFFFFFFBBB);
187  // MIE: enable all core-local and add. platform-specific interrupts
188  riscv64cpu->CSR[0x104] = riscv64cpu->CSR[0x304] & (~(0x888));
189  // SIE: enable all core-local and add. platform-specific interrupts (supervised)
190  riscv64cpu->CSR[0x004] = riscv64cpu->CSR[0x304] & (~(0xAAA));
191  // UIE: enable all core-local and add. platform-specific interrupts (user)
192  /* <<< manually added code section */
193 }
194 
195 void RISCV64Arch::deleteCPU(ETISS_CPU *cpu)
196 {
197  delete (RISCV64 *) cpu ;
198 }
199 
200 
204 unsigned RISCV64Arch::getMaximumInstructionSizeInBytes()
205 {
206  return 8;
207 }
211 unsigned RISCV64Arch::getInstructionSizeInBytes()
212 {
213  return 2;
214 }
218 const std::set<std::string> & RISCV64Arch::getHeaders() const
219 {
220  return headers_ ;
221 }
222 
223 void RISCV64Arch::initCodeBlock(etiss::CodeBlock & cb) const
224 {
225  cb.fileglobalCode().insert("#include \"Arch/RISCV64/RISCV64.h\"\n");
226 }
227 
228 etiss::plugin::gdb::GDBCore & RISCV64Arch::getGDBCore()
229 {
230 
231  return gdbcore_;
232 }
233 
234 // Manually added
235 etiss::Plugin *RISCV64Arch::newTimer(ETISS_CPU *cpu)
236 {
237  return (etiss::Plugin *)new RISCV64Timer();
238 }
239 
240 // Manually added
241 void RISCV64Arch::deleteTimer(etiss::Plugin *timer)
242 {
243  delete timer;
244 }
245 
246 // Manually added
247 etiss::mm::MMU *RISCV64Arch::newMMU(ETISS_CPU *cpu)
248 {
249  return (etiss::mm::MMU *)new RISCV64MMU(false);
250 }
251 
252 static const char * const reg_name[] =
253 {
254  "X0",
255  "X1",
256  "X2",
257  "X3",
258  "X4",
259  "X5",
260  "X6",
261  "X7",
262  "X8",
263  "X9",
264  "X10",
265  "X11",
266  "X12",
267  "X13",
268  "X14",
269  "X15",
270  "X16",
271  "X17",
272  "X18",
273  "X19",
274  "X20",
275  "X21",
276  "X22",
277  "X23",
278  "X24",
279  "X25",
280  "X26",
281  "X27",
282  "X28",
283  "X29",
284  "X30",
285  "X31",
286 };
287 
289 static InstructionDefinition lui_rd_imm(
290  ISA32_RISCV64,
291  "lui",
292  (uint32_t)0x37,
293  (uint32_t) 0x7f,
294  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
295  {
296  etiss_uint64 rd = 0;
297  static BitArrayRange R_rd_0 (11,7);
298  etiss_uint64 rd_0 = R_rd_0.read(ba);
299  rd += rd_0;
300  etiss_int64 imm = 0;
301  static BitArrayRange R_imm_12 (31,12);
302  etiss_int64 imm_12 = R_imm_12.read(ba);
303  imm += imm_12<<12;
304  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
305  partInit.getAffectedRegisters().add(reg_name[rd],64);
306  partInit.getAffectedRegisters().add("instructionPointer",64);
307  partInit.code() = std::string("//lui\n")+
308  "etiss_uint32 temp = 0;\n"
309  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
310  #if RISCV64_Pipeline1
311  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
312  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
313  "etiss_uint32 num_stages = 4;\n"
314  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
315  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
316  #endif
317  #if RISCV64_Pipeline2
318  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
319  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
320  "etiss_uint32 num_stages = 4;\n"
321  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
322  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
323  #endif
324 
325  "etiss_int64 imm_extended = 0;\n"
326 
327 "if((" + toString(imm) + " & 0x80000000)>>31 == 0)\n"
328 "{\n"
329  "imm_extended = 0;\n"
330  #if RISCV64_DEBUG_CALL
331  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
332  #endif
333 "}\n"
334 
335 "else\n"
336 "{\n"
337  "imm_extended = 4294967295;\n"
338  #if RISCV64_DEBUG_CALL
339  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
340  #endif
341  "imm_extended = (imm_extended << 32);\n"
342  #if RISCV64_DEBUG_CALL
343  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
344  #endif
345 "}\n"
346 "imm_extended = imm_extended + " + toString(imm) + ";\n"
347 #if RISCV64_DEBUG_CALL
348 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
349 #endif
350 "if(" + toString(rd) + " != 0)\n"
351 "{\n"
352  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = imm_extended;\n"
353  #if RISCV64_DEBUG_CALL
354  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
355  #endif
356 "}\n"
357 
358 
359  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
360 
361 ;
362 return true;
363 },
364 0,
365 nullptr
366 );
367 //-------------------------------------------------------------------------------------------------------------------
368 static InstructionDefinition auipc_rd_imm(
369  ISA32_RISCV64,
370  "auipc",
371  (uint32_t)0x17,
372  (uint32_t) 0x7f,
373  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
374  {
375  etiss_uint64 rd = 0;
376  static BitArrayRange R_rd_0 (11,7);
377  etiss_uint64 rd_0 = R_rd_0.read(ba);
378  rd += rd_0;
379  etiss_int64 imm = 0;
380  static BitArrayRange R_imm_12 (31,12);
381  etiss_int64 imm_12 = R_imm_12.read(ba);
382  imm += imm_12<<12;
383  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
384  partInit.getAffectedRegisters().add(reg_name[rd],64);
385  partInit.getAffectedRegisters().add("instructionPointer",64);
386  partInit.code() = std::string("//auipc\n")+
387  "etiss_uint32 temp = 0;\n"
388  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
389  #if RISCV64_Pipeline1
390  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
391  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
392  "etiss_uint32 num_stages = 4;\n"
393  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
394  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
395  #endif
396  #if RISCV64_Pipeline2
397  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
398  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
399  "etiss_uint32 num_stages = 4;\n"
400  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
401  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
402  #endif
403 
404  "etiss_int64 imm_extended = 0;\n"
405 
406 "if((" + toString(imm) + " & 0x80000000)>>31 == 0)\n"
407 "{\n"
408  "imm_extended = 0;\n"
409  #if RISCV64_DEBUG_CALL
410  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
411  #endif
412 "}\n"
413 
414 "else\n"
415 "{\n"
416  "imm_extended = 4294967295;\n"
417  #if RISCV64_DEBUG_CALL
418  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
419  #endif
420  "imm_extended = (imm_extended << 32);\n"
421  #if RISCV64_DEBUG_CALL
422  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
423  #endif
424 "}\n"
425 "imm_extended = imm_extended + " + toString(imm) + ";\n"
426 #if RISCV64_DEBUG_CALL
427 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
428 #endif
429 "if(" + toString(rd) + " != 0)\n"
430 "{\n"
431  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
432  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
433  "{\n"
434  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
435  "}\n"
436  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0 + imm_extended;\n"
437  #if RISCV64_DEBUG_CALL
438  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
439  #endif
440 "}\n"
441 
442 
443  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
444 
445 ;
446 return true;
447 },
448 0,
449 nullptr
450 );
451 //-------------------------------------------------------------------------------------------------------------------
452 static InstructionDefinition jal_rd_imm(
453  ISA32_RISCV64,
454  "jal",
455  (uint32_t)0x6f,
456  (uint32_t) 0x7f,
457  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
458  {
459  etiss_uint64 rd = 0;
460  static BitArrayRange R_rd_0 (11,7);
461  etiss_uint64 rd_0 = R_rd_0.read(ba);
462  rd += rd_0;
463  etiss_int64 imm = 0;
464  static BitArrayRange R_imm_20 (31,31);
465  etiss_int64 imm_20 = R_imm_20.read(ba);
466  imm += imm_20<<20;
467  static BitArrayRange R_imm_1 (30,21);
468  etiss_int64 imm_1 = R_imm_1.read(ba);
469  imm += imm_1<<1;
470  static BitArrayRange R_imm_11 (20,20);
471  etiss_int64 imm_11 = R_imm_11.read(ba);
472  imm += imm_11<<11;
473  static BitArrayRange R_imm_12 (19,12);
474  etiss_int64 imm_12 = R_imm_12.read(ba);
475  imm += imm_12<<12;
476  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
477  partInit.getAffectedRegisters().add(reg_name[rd],64);
478  partInit.getAffectedRegisters().add("instructionPointer",64);
479  partInit.code() = std::string("//jal\n")+
480  "etiss_uint32 temp = 0;\n"
481  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
482  #if RISCV64_Pipeline1
483  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
484  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
485  "etiss_uint32 num_stages = 4;\n"
486  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
487  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
488  #endif
489  #if RISCV64_Pipeline2
490  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
491  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
492  "etiss_uint32 num_stages = 4;\n"
493  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
494  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
495  #endif
496 
497  "etiss_int64 imm_extended = 0;\n"
498 
499 "if((" + toString(imm) + " & 0x100000)>>20 == 0)\n"
500 "{\n"
501  "imm_extended = 0;\n"
502  #if RISCV64_DEBUG_CALL
503  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
504  #endif
505 "}\n"
506 
507 "else\n"
508 "{\n"
509  "imm_extended = 4294967295;\n"
510  #if RISCV64_DEBUG_CALL
511  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
512  #endif
513  "imm_extended = (imm_extended << 32);\n"
514  #if RISCV64_DEBUG_CALL
515  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
516  #endif
517  "imm_extended = imm_extended + 4292870144;\n"
518  #if RISCV64_DEBUG_CALL
519  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
520  #endif
521 "}\n"
522 "imm_extended = imm_extended + " + toString(imm) + ";\n"
523 #if RISCV64_DEBUG_CALL
524 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
525 #endif
526 "if(" + toString(rd) + " != 0)\n"
527 "{\n"
528  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
529  #if RISCV64_DEBUG_CALL
530  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
531  #endif
532 "}\n"
533 
534 "else\n"
535 "{\n"
536 // Explicit assignment to PC
537 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
538 "}\n"
539 "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
540 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
541 "{\n"
542  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
543 "}\n"
544 "cpu->instructionPointer = (etiss_int64)cast_0 + imm_extended;\n"
545 #if RISCV64_DEBUG_CALL
546 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
547 #endif
548 
549  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
550 
551  "return 0;\n"
552 ;
553 return true;
554 },
555 0,
556 nullptr
557 );
558 //-------------------------------------------------------------------------------------------------------------------
559 static InstructionDefinition jalr_rd_rs1_imm(
560  ISA32_RISCV64,
561  "jalr",
562  (uint32_t)0x67,
563  (uint32_t) 0x707f,
564  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
565  {
566  etiss_uint64 rs1 = 0;
567  static BitArrayRange R_rs1_0 (19,15);
568  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
569  rs1 += rs1_0;
570  etiss_uint64 rd = 0;
571  static BitArrayRange R_rd_0 (11,7);
572  etiss_uint64 rd_0 = R_rd_0.read(ba);
573  rd += rd_0;
574  etiss_int64 imm = 0;
575  static BitArrayRange R_imm_0 (31,20);
576  etiss_int64 imm_0 = R_imm_0.read(ba);
577  imm += imm_0;
578  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
579  partInit.getRegisterDependencies().add(reg_name[rs1],64);
580  partInit.getAffectedRegisters().add(reg_name[rd],64);
581  partInit.getAffectedRegisters().add("instructionPointer",64);
582  partInit.code() = std::string("//jalr\n")+
583  "etiss_uint32 temp = 0;\n"
584  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
585  #if RISCV64_Pipeline1
586  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
587  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
588  "etiss_uint32 num_stages = 4;\n"
589  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
590  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
591  #endif
592  #if RISCV64_Pipeline2
593  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
594  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
595  "etiss_uint32 num_stages = 4;\n"
596  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
597  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
598  #endif
599 
600  "etiss_int64 imm_extended = 0;\n"
601  "etiss_int64 new_pc = 0;\n"
602 
603 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
604 "{\n"
605  "imm_extended = 0;\n"
606  #if RISCV64_DEBUG_CALL
607  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
608  #endif
609 "}\n"
610 
611 "else\n"
612 "{\n"
613  "imm_extended = 4294967295;\n"
614  #if RISCV64_DEBUG_CALL
615  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
616  #endif
617  "imm_extended = (imm_extended << 32);\n"
618  #if RISCV64_DEBUG_CALL
619  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
620  #endif
621  "imm_extended = imm_extended + 4294963200;\n"
622  #if RISCV64_DEBUG_CALL
623  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
624  #endif
625 "}\n"
626 "imm_extended = imm_extended + " + toString(imm) + ";\n"
627 #if RISCV64_DEBUG_CALL
628 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
629 #endif
630 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
631 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
632 "{\n"
633  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
634 "}\n"
635 "new_pc = (etiss_int64)cast_0 + imm_extended;\n"
636 #if RISCV64_DEBUG_CALL
637 "printf(\"new_pc = %#lx\\n\",new_pc); \n"
638 #endif
639 "if(" + toString(rd) + " != 0)\n"
640 "{\n"
641  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
642  #if RISCV64_DEBUG_CALL
643  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
644  #endif
645 "}\n"
646 
647 "else\n"
648 "{\n"
649 // Explicit assignment to PC
650 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
651 "}\n"
652 "cpu->instructionPointer = (new_pc & ~1)&0xffffffffffffffff;\n"
653 #if RISCV64_DEBUG_CALL
654 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
655 #endif
656 
657  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
658 
659  "return 0;\n"
660 ;
661 return true;
662 },
663 0,
664 nullptr
665 );
666 //-------------------------------------------------------------------------------------------------------------------
667 static InstructionDefinition beq_rs1_rs2_imm(
668  ISA32_RISCV64,
669  "beq",
670  (uint32_t)0x63,
671  (uint32_t) 0x707f,
672  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
673  {
674  etiss_uint64 rs2 = 0;
675  static BitArrayRange R_rs2_0 (24,20);
676  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
677  rs2 += rs2_0;
678  etiss_uint64 rs1 = 0;
679  static BitArrayRange R_rs1_0 (19,15);
680  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
681  rs1 += rs1_0;
682  etiss_int64 imm = 0;
683  static BitArrayRange R_imm_12 (31,31);
684  etiss_int64 imm_12 = R_imm_12.read(ba);
685  imm += imm_12<<12;
686  static BitArrayRange R_imm_5 (30,25);
687  etiss_int64 imm_5 = R_imm_5.read(ba);
688  imm += imm_5<<5;
689  static BitArrayRange R_imm_1 (11,8);
690  etiss_int64 imm_1 = R_imm_1.read(ba);
691  imm += imm_1<<1;
692  static BitArrayRange R_imm_11 (7,7);
693  etiss_int64 imm_11 = R_imm_11.read(ba);
694  imm += imm_11<<11;
695  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
696  partInit.getRegisterDependencies().add(reg_name[rs2],64);
697  partInit.getRegisterDependencies().add(reg_name[rs1],64);
698  partInit.getAffectedRegisters().add("instructionPointer",64);
699  partInit.code() = std::string("//beq\n")+
700  "etiss_uint32 temp = 0;\n"
701  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
702  #if RISCV64_Pipeline1
703  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
704  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
705  "etiss_uint32 num_stages = 4;\n"
706  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
707  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
708  #endif
709  #if RISCV64_Pipeline2
710  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
711  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
712  "etiss_uint32 num_stages = 4;\n"
713  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
714  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
715  #endif
716 
717  "etiss_int64 imm_extended = 0;\n"
718  "etiss_int64 choose1 = 0;\n"
719 
720 "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n"
721 "{\n"
722  "imm_extended = 0;\n"
723  #if RISCV64_DEBUG_CALL
724  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
725  #endif
726 "}\n"
727 
728 "else\n"
729 "{\n"
730  "imm_extended = 4294967295;\n"
731  #if RISCV64_DEBUG_CALL
732  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
733  #endif
734  "imm_extended = (imm_extended << 32);\n"
735  #if RISCV64_DEBUG_CALL
736  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
737  #endif
738  "imm_extended = imm_extended + 4294959104;\n"
739  #if RISCV64_DEBUG_CALL
740  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
741  #endif
742 "}\n"
743 "imm_extended = imm_extended + " + toString(imm) + ";\n"
744 #if RISCV64_DEBUG_CALL
745 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
746 #endif
747 "if(*((RISCV64*)cpu)->X[" + toString(rs1) + "] == *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
748 "{\n"
749  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
750  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
751  "{\n"
752  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
753  "}\n"
754  "choose1 = (etiss_int64)cast_0 + imm_extended;\n"
755  #if RISCV64_DEBUG_CALL
756  "printf(\"choose1 = %#lx\\n\",choose1); \n"
757  #endif
758 // Explicit assignment to PC
759 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
760 "}\n"
761 
762 "else\n"
763 "{\n"
764  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
765  #if RISCV64_DEBUG_CALL
766  "printf(\"choose1 = %#lx\\n\",choose1); \n"
767  #endif
768 "}\n"
769 "cpu->instructionPointer = choose1;\n"
770 #if RISCV64_DEBUG_CALL
771 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
772 #endif
773 
774  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
775 
776  "return 0;\n"
777 ;
778 return true;
779 },
780 0,
781 nullptr
782 );
783 //-------------------------------------------------------------------------------------------------------------------
784 static InstructionDefinition lb_rd_imm_rs1_(
785  ISA32_RISCV64,
786  "lb",
787  (uint32_t)0x3,
788  (uint32_t) 0x707f,
789  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
790  {
791  etiss_uint64 rs1 = 0;
792  static BitArrayRange R_rs1_0 (19,15);
793  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
794  rs1 += rs1_0;
795  etiss_uint64 rd = 0;
796  static BitArrayRange R_rd_0 (11,7);
797  etiss_uint64 rd_0 = R_rd_0.read(ba);
798  rd += rd_0;
799  etiss_int64 imm = 0;
800  static BitArrayRange R_imm_0 (31,20);
801  etiss_int64 imm_0 = R_imm_0.read(ba);
802  imm += imm_0;
803  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
804  partInit.getRegisterDependencies().add(reg_name[rs1],64);
805  partInit.getAffectedRegisters().add(reg_name[rd],64);
806  partInit.getAffectedRegisters().add("instructionPointer",64);
807  partInit.code() = std::string("//lb\n")+
808  "etiss_uint32 exception = 0;\n"
809  "etiss_uint32 temp = 0;\n"
810  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
811  #if RISCV64_Pipeline1
812  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
813  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
814  "etiss_uint32 num_stages = 4;\n"
815  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
816  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
817  #endif
818  #if RISCV64_Pipeline2
819  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
820  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
821  "etiss_uint32 num_stages = 4;\n"
822  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
823  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
824  #endif
825 
826  "etiss_int64 offs = 0;\n"
827  "etiss_int64 imm_extended = 0;\n"
828 
829 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
830 "{\n"
831  "imm_extended = 0;\n"
832  #if RISCV64_DEBUG_CALL
833  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
834  #endif
835 "}\n"
836 
837 "else\n"
838 "{\n"
839  "imm_extended = 4294967295;\n"
840  #if RISCV64_DEBUG_CALL
841  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
842  #endif
843  "imm_extended = (imm_extended << 32);\n"
844  #if RISCV64_DEBUG_CALL
845  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
846  #endif
847  "imm_extended = imm_extended + 4294963200;\n"
848  #if RISCV64_DEBUG_CALL
849  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
850  #endif
851 "}\n"
852 "imm_extended = imm_extended + " + toString(imm) + ";\n"
853 #if RISCV64_DEBUG_CALL
854 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
855 #endif
856 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
857 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
858 "{\n"
859  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
860 "}\n"
861 "offs = (etiss_int64)cast_0 + imm_extended;\n"
862 #if RISCV64_DEBUG_CALL
863 "printf(\"offs = %#lx\\n\",offs); \n"
864 #endif
865 "if(" + toString(rd) + " != 0)\n"
866 "{\n"
867  "etiss_uint8 MEM_offs;\n"
868  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
869  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,1);\n"
870  "etiss_int8 cast_1 = MEM_offs; \n"
871  "if((etiss_int8)((etiss_uint8)cast_1 - 0x80) > 0x0)\n"
872  "{\n"
873  "cast_1 =0x0 + (etiss_uint8)cast_1 ;\n"
874  "}\n"
875  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
876  #if RISCV64_DEBUG_CALL
877  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
878  #endif
879 "}\n"
880 
881 
882  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
883 
884  "return exception;\n"
885 ;
886 return true;
887 },
888 0,
889 nullptr
890 );
891 //-------------------------------------------------------------------------------------------------------------------
892 static InstructionDefinition sb_rs2_imm_rs1_(
893  ISA32_RISCV64,
894  "sb",
895  (uint32_t)0x23,
896  (uint32_t) 0x707f,
897  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
898  {
899  etiss_uint64 rs2 = 0;
900  static BitArrayRange R_rs2_0 (24,20);
901  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
902  rs2 += rs2_0;
903  etiss_uint64 rs1 = 0;
904  static BitArrayRange R_rs1_0 (19,15);
905  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
906  rs1 += rs1_0;
907  etiss_int64 imm = 0;
908  static BitArrayRange R_imm_5 (31,25);
909  etiss_int64 imm_5 = R_imm_5.read(ba);
910  imm += imm_5<<5;
911  static BitArrayRange R_imm_0 (11,7);
912  etiss_int64 imm_0 = R_imm_0.read(ba);
913  imm += imm_0;
914  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
915  partInit.getRegisterDependencies().add(reg_name[rs2],64);
916  partInit.getRegisterDependencies().add(reg_name[rs1],64);
917  partInit.getAffectedRegisters().add("instructionPointer",64);
918  partInit.code() = std::string("//sb\n")+
919  "etiss_uint32 exception = 0;\n"
920  "etiss_uint32 temp = 0;\n"
921  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
922  #if RISCV64_Pipeline1
923  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
924  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
925  "etiss_uint32 num_stages = 4;\n"
926  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
927  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
928  #endif
929  #if RISCV64_Pipeline2
930  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
931  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
932  "etiss_uint32 num_stages = 4;\n"
933  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
934  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
935  #endif
936 
937  "etiss_int64 offs = 0;\n"
938  "etiss_int64 imm_extended = 0;\n"
939 
940 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
941 "{\n"
942  "imm_extended = 0;\n"
943  #if RISCV64_DEBUG_CALL
944  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
945  #endif
946 "}\n"
947 
948 "else\n"
949 "{\n"
950  "imm_extended = 4294967295;\n"
951  #if RISCV64_DEBUG_CALL
952  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
953  #endif
954  "imm_extended = (imm_extended << 32);\n"
955  #if RISCV64_DEBUG_CALL
956  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
957  #endif
958  "imm_extended = imm_extended + 4294963200;\n"
959  #if RISCV64_DEBUG_CALL
960  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
961  #endif
962 "}\n"
963 "imm_extended = imm_extended + " + toString(imm) + ";\n"
964 #if RISCV64_DEBUG_CALL
965 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
966 #endif
967 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
968 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
969 "{\n"
970  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
971 "}\n"
972 "offs = (etiss_int64)cast_0 + imm_extended;\n"
973 #if RISCV64_DEBUG_CALL
974 "printf(\"offs = %#lx\\n\",offs); \n"
975 #endif
976  "etiss_uint8 MEM_offs;\n"
977 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
978 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
979 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,1);\n"
980 #if RISCV64_DEBUG_CALL
981 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
982 #endif
983 "if((offs + 1 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
984 "{\n"
985  "((RISCV64*)cpu)->RES = 0;\n"
986  #if RISCV64_DEBUG_CALL
987  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
988  #endif
989 "}\n"
990 
991 
992  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
993 
994  "return exception;\n"
995 ;
996 return true;
997 },
998 0,
999 nullptr
1000 );
1001 //-------------------------------------------------------------------------------------------------------------------
1002 static InstructionDefinition addi_rd_rs1_imm(
1003  ISA32_RISCV64,
1004  "addi",
1005  (uint32_t)0x13,
1006  (uint32_t) 0x707f,
1007  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1008  {
1009  etiss_uint64 rs1 = 0;
1010  static BitArrayRange R_rs1_0 (19,15);
1011  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1012  rs1 += rs1_0;
1013  etiss_uint64 rd = 0;
1014  static BitArrayRange R_rd_0 (11,7);
1015  etiss_uint64 rd_0 = R_rd_0.read(ba);
1016  rd += rd_0;
1017  etiss_int64 imm = 0;
1018  static BitArrayRange R_imm_0 (31,20);
1019  etiss_int64 imm_0 = R_imm_0.read(ba);
1020  imm += imm_0;
1021  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1022  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1023  partInit.getAffectedRegisters().add(reg_name[rd],64);
1024  partInit.getAffectedRegisters().add("instructionPointer",64);
1025  partInit.code() = std::string("//addi\n")+
1026  "etiss_uint32 temp = 0;\n"
1027  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1028  #if RISCV64_Pipeline1
1029  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1030  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1031  "etiss_uint32 num_stages = 4;\n"
1032  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1033  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1034  #endif
1035  #if RISCV64_Pipeline2
1036  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1037  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1038  "etiss_uint32 num_stages = 4;\n"
1039  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1040  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1041  #endif
1042 
1043  "etiss_int64 imm_extended = 0;\n"
1044 
1045 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
1046 "{\n"
1047  "imm_extended = 0;\n"
1048  #if RISCV64_DEBUG_CALL
1049  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1050  #endif
1051 "}\n"
1052 
1053 "else\n"
1054 "{\n"
1055  "imm_extended = 4294967295;\n"
1056  #if RISCV64_DEBUG_CALL
1057  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1058  #endif
1059  "imm_extended = (imm_extended << 32);\n"
1060  #if RISCV64_DEBUG_CALL
1061  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1062  #endif
1063  "imm_extended = imm_extended + 4294963200;\n"
1064  #if RISCV64_DEBUG_CALL
1065  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1066  #endif
1067 "}\n"
1068 "imm_extended = imm_extended + " + toString(imm) + ";\n"
1069 #if RISCV64_DEBUG_CALL
1070 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1071 #endif
1072 "if(" + toString(rd) + " != 0)\n"
1073 "{\n"
1074  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
1075  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
1076  "{\n"
1077  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
1078  "}\n"
1079  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0 + imm_extended;\n"
1080  #if RISCV64_DEBUG_CALL
1081  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
1082  #endif
1083 "}\n"
1084 
1085 
1086  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1087 
1088 ;
1089 return true;
1090 },
1091 0,
1092 nullptr
1093 );
1094 //-------------------------------------------------------------------------------------------------------------------
1095 static InstructionDefinition addiw_rd_rs1_imm(
1096  ISA32_RISCV64,
1097  "addiw",
1098  (uint32_t)0x1b,
1099  (uint32_t) 0x707f,
1100  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1101  {
1102  etiss_uint64 rs1 = 0;
1103  static BitArrayRange R_rs1_0 (19,15);
1104  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1105  rs1 += rs1_0;
1106  etiss_uint64 rd = 0;
1107  static BitArrayRange R_rd_0 (11,7);
1108  etiss_uint64 rd_0 = R_rd_0.read(ba);
1109  rd += rd_0;
1110  etiss_int64 imm = 0;
1111  static BitArrayRange R_imm_0 (31,20);
1112  etiss_int64 imm_0 = R_imm_0.read(ba);
1113  imm += imm_0;
1114  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1115  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1116  partInit.getAffectedRegisters().add(reg_name[rd],64);
1117  partInit.getAffectedRegisters().add("instructionPointer",64);
1118  partInit.code() = std::string("//addiw\n")+
1119  "etiss_uint32 temp = 0;\n"
1120  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1121  #if RISCV64_Pipeline1
1122  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1123  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1124  "etiss_uint32 num_stages = 4;\n"
1125  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1126  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1127  #endif
1128  #if RISCV64_Pipeline2
1129  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1130  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1131  "etiss_uint32 num_stages = 4;\n"
1132  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1133  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1134  #endif
1135 
1136  "etiss_int64 imm_extended = 0;\n"
1137  "etiss_int32 res = 0;\n"
1138 
1139 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
1140 "{\n"
1141  "imm_extended = 0;\n"
1142  #if RISCV64_DEBUG_CALL
1143  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1144  #endif
1145 "}\n"
1146 
1147 "else\n"
1148 "{\n"
1149  "imm_extended = 4294967295;\n"
1150  #if RISCV64_DEBUG_CALL
1151  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1152  #endif
1153  "imm_extended = (imm_extended << 32);\n"
1154  #if RISCV64_DEBUG_CALL
1155  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1156  #endif
1157  "imm_extended = imm_extended + 4294963200;\n"
1158  #if RISCV64_DEBUG_CALL
1159  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1160  #endif
1161 "}\n"
1162 "imm_extended = imm_extended + " + toString(imm) + ";\n"
1163 #if RISCV64_DEBUG_CALL
1164 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1165 #endif
1166 "if(" + toString(rd) + " != 0)\n"
1167 "{\n"
1168  "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
1169  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
1170  "{\n"
1171  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
1172  "}\n"
1173  "res = (etiss_int32)cast_0 + imm_extended;\n"
1174  #if RISCV64_DEBUG_CALL
1175  "printf(\"res = %#x\\n\",res); \n"
1176  #endif
1177  "etiss_int32 cast_1 = res; \n"
1178  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
1179  "{\n"
1180  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
1181  "}\n"
1182  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
1183  #if RISCV64_DEBUG_CALL
1184  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
1185  #endif
1186 "}\n"
1187 
1188 
1189  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1190 
1191 ;
1192 return true;
1193 },
1194 0,
1195 nullptr
1196 );
1197 //-------------------------------------------------------------------------------------------------------------------
1198 static InstructionDefinition bne_rs1_rs2_imm(
1199  ISA32_RISCV64,
1200  "bne",
1201  (uint32_t)0x1063,
1202  (uint32_t) 0x707f,
1203  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1204  {
1205  etiss_uint64 rs2 = 0;
1206  static BitArrayRange R_rs2_0 (24,20);
1207  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
1208  rs2 += rs2_0;
1209  etiss_uint64 rs1 = 0;
1210  static BitArrayRange R_rs1_0 (19,15);
1211  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1212  rs1 += rs1_0;
1213  etiss_int64 imm = 0;
1214  static BitArrayRange R_imm_12 (31,31);
1215  etiss_int64 imm_12 = R_imm_12.read(ba);
1216  imm += imm_12<<12;
1217  static BitArrayRange R_imm_5 (30,25);
1218  etiss_int64 imm_5 = R_imm_5.read(ba);
1219  imm += imm_5<<5;
1220  static BitArrayRange R_imm_1 (11,8);
1221  etiss_int64 imm_1 = R_imm_1.read(ba);
1222  imm += imm_1<<1;
1223  static BitArrayRange R_imm_11 (7,7);
1224  etiss_int64 imm_11 = R_imm_11.read(ba);
1225  imm += imm_11<<11;
1226  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1227  partInit.getRegisterDependencies().add(reg_name[rs2],64);
1228  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1229  partInit.getAffectedRegisters().add("instructionPointer",64);
1230  partInit.code() = std::string("//bne\n")+
1231  "etiss_uint32 temp = 0;\n"
1232  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1233  #if RISCV64_Pipeline1
1234  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1235  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1236  "etiss_uint32 num_stages = 4;\n"
1237  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1238  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1239  #endif
1240  #if RISCV64_Pipeline2
1241  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1242  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1243  "etiss_uint32 num_stages = 4;\n"
1244  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1245  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1246  #endif
1247 
1248  "etiss_int64 imm_extended = 0;\n"
1249  "etiss_int64 choose1 = 0;\n"
1250 
1251 "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n"
1252 "{\n"
1253  "imm_extended = 0;\n"
1254  #if RISCV64_DEBUG_CALL
1255  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1256  #endif
1257 "}\n"
1258 
1259 "else\n"
1260 "{\n"
1261  "imm_extended = 4294967295;\n"
1262  #if RISCV64_DEBUG_CALL
1263  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1264  #endif
1265  "imm_extended = (imm_extended << 32);\n"
1266  #if RISCV64_DEBUG_CALL
1267  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1268  #endif
1269  "imm_extended = imm_extended + 4294959104;\n"
1270  #if RISCV64_DEBUG_CALL
1271  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1272  #endif
1273 "}\n"
1274 "imm_extended = imm_extended + " + toString(imm) + ";\n"
1275 #if RISCV64_DEBUG_CALL
1276 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1277 #endif
1278 "if(*((RISCV64*)cpu)->X[" + toString(rs1) + "] != *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
1279 "{\n"
1280  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
1281  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
1282  "{\n"
1283  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
1284  "}\n"
1285  "choose1 = (etiss_int64)cast_0 + imm_extended;\n"
1286  #if RISCV64_DEBUG_CALL
1287  "printf(\"choose1 = %#lx\\n\",choose1); \n"
1288  #endif
1289 // Explicit assignment to PC
1290 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1291 "}\n"
1292 
1293 "else\n"
1294 "{\n"
1295  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
1296  #if RISCV64_DEBUG_CALL
1297  "printf(\"choose1 = %#lx\\n\",choose1); \n"
1298  #endif
1299 "}\n"
1300 "cpu->instructionPointer = choose1;\n"
1301 #if RISCV64_DEBUG_CALL
1302 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
1303 #endif
1304 
1305  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
1306 
1307  "return 0;\n"
1308 ;
1309 return true;
1310 },
1311 0,
1312 nullptr
1313 );
1314 //-------------------------------------------------------------------------------------------------------------------
1315 static InstructionDefinition lh_rd_imm_rs1_(
1316  ISA32_RISCV64,
1317  "lh",
1318  (uint32_t)0x1003,
1319  (uint32_t) 0x707f,
1320  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1321  {
1322  etiss_uint64 rs1 = 0;
1323  static BitArrayRange R_rs1_0 (19,15);
1324  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1325  rs1 += rs1_0;
1326  etiss_uint64 rd = 0;
1327  static BitArrayRange R_rd_0 (11,7);
1328  etiss_uint64 rd_0 = R_rd_0.read(ba);
1329  rd += rd_0;
1330  etiss_int64 imm = 0;
1331  static BitArrayRange R_imm_0 (31,20);
1332  etiss_int64 imm_0 = R_imm_0.read(ba);
1333  imm += imm_0;
1334  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1335  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1336  partInit.getAffectedRegisters().add(reg_name[rd],64);
1337  partInit.getAffectedRegisters().add("instructionPointer",64);
1338  partInit.code() = std::string("//lh\n")+
1339  "etiss_uint32 exception = 0;\n"
1340  "etiss_uint32 temp = 0;\n"
1341  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1342  #if RISCV64_Pipeline1
1343  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1344  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1345  "etiss_uint32 num_stages = 4;\n"
1346  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1347  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1348  #endif
1349  #if RISCV64_Pipeline2
1350  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1351  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1352  "etiss_uint32 num_stages = 4;\n"
1353  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1354  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1355  #endif
1356 
1357  "etiss_int64 offs = 0;\n"
1358  "etiss_int64 imm_extended = 0;\n"
1359 
1360 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
1361 "{\n"
1362  "imm_extended = 0;\n"
1363  #if RISCV64_DEBUG_CALL
1364  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1365  #endif
1366 "}\n"
1367 
1368 "else\n"
1369 "{\n"
1370  "imm_extended = 4294967295;\n"
1371  #if RISCV64_DEBUG_CALL
1372  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1373  #endif
1374  "imm_extended = (imm_extended << 32);\n"
1375  #if RISCV64_DEBUG_CALL
1376  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1377  #endif
1378  "imm_extended = imm_extended + 4294963200;\n"
1379  #if RISCV64_DEBUG_CALL
1380  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1381  #endif
1382 "}\n"
1383 "imm_extended = imm_extended + " + toString(imm) + ";\n"
1384 #if RISCV64_DEBUG_CALL
1385 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1386 #endif
1387 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
1388 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
1389 "{\n"
1390  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
1391 "}\n"
1392 "offs = (etiss_int64)cast_0 + imm_extended;\n"
1393 #if RISCV64_DEBUG_CALL
1394 "printf(\"offs = %#lx\\n\",offs); \n"
1395 #endif
1396 "if(" + toString(rd) + " != 0)\n"
1397 "{\n"
1398  "etiss_uint16 MEM_offs;\n"
1399  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
1400  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,2);\n"
1401  "etiss_int16 cast_1 = MEM_offs; \n"
1402  "if((etiss_int16)((etiss_uint16)cast_1 - 0x8000) > 0x0)\n"
1403  "{\n"
1404  "cast_1 =0x0 + (etiss_uint16)cast_1 ;\n"
1405  "}\n"
1406  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
1407  #if RISCV64_DEBUG_CALL
1408  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
1409  #endif
1410 "}\n"
1411 
1412 
1413  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1414 
1415  "return exception;\n"
1416 ;
1417 return true;
1418 },
1419 0,
1420 nullptr
1421 );
1422 //-------------------------------------------------------------------------------------------------------------------
1423 static InstructionDefinition sh_rs2_imm_rs1_(
1424  ISA32_RISCV64,
1425  "sh",
1426  (uint32_t)0x1023,
1427  (uint32_t) 0x707f,
1428  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1429  {
1430  etiss_uint64 rs2 = 0;
1431  static BitArrayRange R_rs2_0 (24,20);
1432  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
1433  rs2 += rs2_0;
1434  etiss_uint64 rs1 = 0;
1435  static BitArrayRange R_rs1_0 (19,15);
1436  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1437  rs1 += rs1_0;
1438  etiss_int64 imm = 0;
1439  static BitArrayRange R_imm_5 (31,25);
1440  etiss_int64 imm_5 = R_imm_5.read(ba);
1441  imm += imm_5<<5;
1442  static BitArrayRange R_imm_0 (11,7);
1443  etiss_int64 imm_0 = R_imm_0.read(ba);
1444  imm += imm_0;
1445  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1446  partInit.getRegisterDependencies().add(reg_name[rs2],64);
1447  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1448  partInit.getAffectedRegisters().add("instructionPointer",64);
1449  partInit.code() = std::string("//sh\n")+
1450  "etiss_uint32 exception = 0;\n"
1451  "etiss_uint32 temp = 0;\n"
1452  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1453  #if RISCV64_Pipeline1
1454  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1455  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1456  "etiss_uint32 num_stages = 4;\n"
1457  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1458  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1459  #endif
1460  #if RISCV64_Pipeline2
1461  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1462  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1463  "etiss_uint32 num_stages = 4;\n"
1464  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1465  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1466  #endif
1467 
1468  "etiss_int64 offs = 0;\n"
1469  "etiss_int64 imm_extended = 0;\n"
1470 
1471 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
1472 "{\n"
1473  "imm_extended = 0;\n"
1474  #if RISCV64_DEBUG_CALL
1475  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1476  #endif
1477 "}\n"
1478 
1479 "else\n"
1480 "{\n"
1481  "imm_extended = 4294967295;\n"
1482  #if RISCV64_DEBUG_CALL
1483  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1484  #endif
1485  "imm_extended = (imm_extended << 32);\n"
1486  #if RISCV64_DEBUG_CALL
1487  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1488  #endif
1489  "imm_extended = imm_extended + 4294963200;\n"
1490  #if RISCV64_DEBUG_CALL
1491  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1492  #endif
1493 "}\n"
1494 "imm_extended = imm_extended + " + toString(imm) + ";\n"
1495 #if RISCV64_DEBUG_CALL
1496 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
1497 #endif
1498 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
1499 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
1500 "{\n"
1501  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
1502 "}\n"
1503 "offs = (etiss_int64)cast_0 + imm_extended;\n"
1504 #if RISCV64_DEBUG_CALL
1505 "printf(\"offs = %#lx\\n\",offs); \n"
1506 #endif
1507  "etiss_uint16 MEM_offs;\n"
1508 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
1509 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
1510 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,2);\n"
1511 #if RISCV64_DEBUG_CALL
1512 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
1513 #endif
1514 "if((offs + 2 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
1515 "{\n"
1516  "((RISCV64*)cpu)->RES = 0;\n"
1517  #if RISCV64_DEBUG_CALL
1518  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
1519  #endif
1520 "}\n"
1521 
1522 
1523  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1524 
1525  "return exception;\n"
1526 ;
1527 return true;
1528 },
1529 0,
1530 nullptr
1531 );
1532 //-------------------------------------------------------------------------------------------------------------------
1533 static InstructionDefinition fence_i_(
1534  ISA32_RISCV64,
1535  "fence_i",
1536  (uint32_t)0x100f,
1537  (uint32_t) 0x707f,
1538  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1539  {
1540  etiss_uint64 rs1 = 0;
1541  static BitArrayRange R_rs1_0 (19,15);
1542  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1543  rs1 += rs1_0;
1544  etiss_uint64 rd = 0;
1545  static BitArrayRange R_rd_0 (11,7);
1546  etiss_uint64 rd_0 = R_rd_0.read(ba);
1547  rd += rd_0;
1548  etiss_uint64 imm = 0;
1549  static BitArrayRange R_imm_0 (31,20);
1550  etiss_uint64 imm_0 = R_imm_0.read(ba);
1551  imm += imm_0;
1552  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1553  partInit.getAffectedRegisters().add(reg_name[1],64);
1554  partInit.getAffectedRegisters().add("instructionPointer",64);
1555  partInit.code() = std::string("//fence_i\n")+
1556  "etiss_uint32 temp = 0;\n"
1557  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1558  #if RISCV64_Pipeline1
1559  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1560  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1561  "etiss_uint32 num_stages = 4;\n"
1562  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1563  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1564  #endif
1565  #if RISCV64_Pipeline2
1566  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1567  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1568  "etiss_uint32 num_stages = 4;\n"
1569  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1570  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1571  #endif
1572 
1573 
1574 "((RISCV64*)cpu)->FENCE[1] = " + toString(imm) + ";\n"
1575 #if RISCV64_DEBUG_CALL
1576 "printf(\"((RISCV64*)cpu)->FENCE[1] = %#lx\\n\",((RISCV64*)cpu)->FENCE[1]); \n"
1577 #endif
1578 
1579  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1580 
1581 ;
1582 return true;
1583 },
1584 0,
1585 nullptr
1586 );
1587 //-------------------------------------------------------------------------------------------------------------------
1588 static InstructionDefinition csrrw_rd_csr_rs1(
1589  ISA32_RISCV64,
1590  "csrrw",
1591  (uint32_t)0x1073,
1592  (uint32_t) 0x707f,
1593  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1594  {
1595  etiss_uint64 rs1 = 0;
1596  static BitArrayRange R_rs1_0 (19,15);
1597  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1598  rs1 += rs1_0;
1599  etiss_uint64 rd = 0;
1600  static BitArrayRange R_rd_0 (11,7);
1601  etiss_uint64 rd_0 = R_rd_0.read(ba);
1602  rd += rd_0;
1603  etiss_uint64 csr = 0;
1604  static BitArrayRange R_csr_0 (31,20);
1605  etiss_uint64 csr_0 = R_csr_0.read(ba);
1606  csr += csr_0;
1607  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1608  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1609  partInit.getAffectedRegisters().add(reg_name[rd],64);
1610  partInit.getAffectedRegisters().add("instructionPointer",64);
1611  partInit.code() = std::string("//csrrw\n")+
1612  "etiss_uint32 temp = 0;\n"
1613  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1614  #if RISCV64_Pipeline1
1615  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1616  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1617  "etiss_uint32 num_stages = 4;\n"
1618  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1619  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1620  #endif
1621  #if RISCV64_Pipeline2
1622  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1623  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1624  "etiss_uint32 num_stages = 4;\n"
1625  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1626  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1627  #endif
1628 
1629  "etiss_int64 mAddr = 0;\n"
1630  "etiss_int64 writeMask = 0;\n"
1631  "etiss_int64 writeMaskU = 0;\n"
1632  "etiss_int64 sAddr = 0;\n"
1633  "etiss_int64 writeMaskS = 0;\n"
1634  "etiss_int64 uAddr = 0;\n"
1635  "etiss_uint64 rs_val = 0;\n"
1636  "etiss_uint64 csr_val = 0;\n"
1637  "etiss_int64 writeMaskM = 0;\n"
1638 
1639 "rs_val = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
1640 #if RISCV64_DEBUG_CALL
1641 "printf(\"rs_val = %#lx\\n\",rs_val); \n"
1642 #endif
1643 "if(" + toString(rd) + " != 0)\n"
1644 "{\n"
1645  "csr_val = ((RISCV64*)cpu)->CSR[" + toString(csr) + "];\n"
1646  #if RISCV64_DEBUG_CALL
1647  "printf(\"csr_val = %#lx\\n\",csr_val); \n"
1648  #endif
1649  "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
1650  "{\n"
1651  "uAddr = 0;\n"
1652  #if RISCV64_DEBUG_CALL
1653  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
1654  #endif
1655  "sAddr = 256;\n"
1656  #if RISCV64_DEBUG_CALL
1657  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
1658  #endif
1659  "mAddr = 768;\n"
1660  #if RISCV64_DEBUG_CALL
1661  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
1662  #endif
1663  "writeMaskM = -9223372036846388805;\n"
1664  #if RISCV64_DEBUG_CALL
1665  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
1666  #endif
1667  "writeMaskS = -9223372036853866189;\n"
1668  #if RISCV64_DEBUG_CALL
1669  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
1670  #endif
1671  "writeMaskU = -9223372036853866479;\n"
1672  #if RISCV64_DEBUG_CALL
1673  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
1674  #endif
1675  "}\n"
1676 
1677  "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
1678  "{\n"
1679  "uAddr = 68;\n"
1680  #if RISCV64_DEBUG_CALL
1681  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
1682  #endif
1683  "sAddr = 324;\n"
1684  #if RISCV64_DEBUG_CALL
1685  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
1686  #endif
1687  "mAddr = 836;\n"
1688  #if RISCV64_DEBUG_CALL
1689  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
1690  #endif
1691  "writeMaskM = 3003;\n"
1692  #if RISCV64_DEBUG_CALL
1693  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
1694  #endif
1695  "writeMaskS = 819;\n"
1696  #if RISCV64_DEBUG_CALL
1697  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
1698  #endif
1699  "writeMaskU = 273;\n"
1700  #if RISCV64_DEBUG_CALL
1701  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
1702  #endif
1703  "}\n"
1704 
1705  "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
1706  "{\n"
1707  "uAddr = 4;\n"
1708  #if RISCV64_DEBUG_CALL
1709  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
1710  #endif
1711  "sAddr = 260;\n"
1712  #if RISCV64_DEBUG_CALL
1713  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
1714  #endif
1715  "mAddr = 772;\n"
1716  #if RISCV64_DEBUG_CALL
1717  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
1718  #endif
1719  "writeMaskM = 3003;\n"
1720  #if RISCV64_DEBUG_CALL
1721  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
1722  #endif
1723  "writeMaskS = 819;\n"
1724  #if RISCV64_DEBUG_CALL
1725  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
1726  #endif
1727  "writeMaskU = 273;\n"
1728  #if RISCV64_DEBUG_CALL
1729  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
1730  #endif
1731  "}\n"
1732 
1733  "if(uAddr != sAddr)\n"
1734  "{\n"
1735  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
1736  "{\n"
1737  "writeMask = writeMaskM;\n"
1738  #if RISCV64_DEBUG_CALL
1739  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
1740  #endif
1741  "}\n"
1742 
1743  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
1744  "{\n"
1745  "writeMask = writeMaskS;\n"
1746  #if RISCV64_DEBUG_CALL
1747  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
1748  #endif
1749  "}\n"
1750 
1751  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
1752  "{\n"
1753  "writeMask = writeMaskU;\n"
1754  #if RISCV64_DEBUG_CALL
1755  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
1756  #endif
1757  "}\n"
1758 
1759  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | (rs_val & writeMask))&0xffffffffffffffff;\n"
1760  #if RISCV64_DEBUG_CALL
1761  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
1762  #endif
1763  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
1764  #if RISCV64_DEBUG_CALL
1765  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
1766  #endif
1767  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
1768  #if RISCV64_DEBUG_CALL
1769  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
1770  #endif
1771  "}\n"
1772 
1773  "else\n"
1774  "{\n"
1775  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = rs_val;\n"
1776  #if RISCV64_DEBUG_CALL
1777  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
1778  #endif
1779  "}\n"
1780  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = csr_val;\n"
1781  #if RISCV64_DEBUG_CALL
1782  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
1783  #endif
1784 "}\n"
1785 
1786 "else\n"
1787 "{\n"
1788  "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
1789  "{\n"
1790  "uAddr = 0;\n"
1791  #if RISCV64_DEBUG_CALL
1792  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
1793  #endif
1794  "sAddr = 256;\n"
1795  #if RISCV64_DEBUG_CALL
1796  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
1797  #endif
1798  "mAddr = 768;\n"
1799  #if RISCV64_DEBUG_CALL
1800  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
1801  #endif
1802  "writeMaskM = -9223372036846388805;\n"
1803  #if RISCV64_DEBUG_CALL
1804  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
1805  #endif
1806  "writeMaskS = -9223372036853866189;\n"
1807  #if RISCV64_DEBUG_CALL
1808  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
1809  #endif
1810  "writeMaskU = -9223372036853866479;\n"
1811  #if RISCV64_DEBUG_CALL
1812  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
1813  #endif
1814  "}\n"
1815 
1816  "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
1817  "{\n"
1818  "uAddr = 68;\n"
1819  #if RISCV64_DEBUG_CALL
1820  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
1821  #endif
1822  "sAddr = 324;\n"
1823  #if RISCV64_DEBUG_CALL
1824  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
1825  #endif
1826  "mAddr = 836;\n"
1827  #if RISCV64_DEBUG_CALL
1828  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
1829  #endif
1830  "writeMaskM = 3003;\n"
1831  #if RISCV64_DEBUG_CALL
1832  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
1833  #endif
1834  "writeMaskS = 819;\n"
1835  #if RISCV64_DEBUG_CALL
1836  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
1837  #endif
1838  "writeMaskU = 273;\n"
1839  #if RISCV64_DEBUG_CALL
1840  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
1841  #endif
1842  "}\n"
1843 
1844  "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
1845  "{\n"
1846  "uAddr = 4;\n"
1847  #if RISCV64_DEBUG_CALL
1848  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
1849  #endif
1850  "sAddr = 260;\n"
1851  #if RISCV64_DEBUG_CALL
1852  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
1853  #endif
1854  "mAddr = 772;\n"
1855  #if RISCV64_DEBUG_CALL
1856  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
1857  #endif
1858  "writeMaskM = 3003;\n"
1859  #if RISCV64_DEBUG_CALL
1860  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
1861  #endif
1862  "writeMaskS = 819;\n"
1863  #if RISCV64_DEBUG_CALL
1864  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
1865  #endif
1866  "writeMaskU = 273;\n"
1867  #if RISCV64_DEBUG_CALL
1868  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
1869  #endif
1870  "}\n"
1871 
1872  "if(uAddr != sAddr)\n"
1873  "{\n"
1874  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
1875  "{\n"
1876  "writeMask = writeMaskM;\n"
1877  #if RISCV64_DEBUG_CALL
1878  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
1879  #endif
1880  "}\n"
1881 
1882  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
1883  "{\n"
1884  "writeMask = writeMaskS;\n"
1885  #if RISCV64_DEBUG_CALL
1886  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
1887  #endif
1888  "}\n"
1889 
1890  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
1891  "{\n"
1892  "writeMask = writeMaskU;\n"
1893  #if RISCV64_DEBUG_CALL
1894  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
1895  #endif
1896  "}\n"
1897 
1898  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | (rs_val & writeMask))&0xffffffffffffffff;\n"
1899  #if RISCV64_DEBUG_CALL
1900  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
1901  #endif
1902  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
1903  #if RISCV64_DEBUG_CALL
1904  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
1905  #endif
1906  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
1907  #if RISCV64_DEBUG_CALL
1908  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
1909  #endif
1910  "}\n"
1911 
1912  "else\n"
1913  "{\n"
1914  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = rs_val;\n"
1915  #if RISCV64_DEBUG_CALL
1916  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
1917  #endif
1918  "}\n"
1919 "}\n"
1920 
1921  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
1922 
1923 ;
1924 return true;
1925 },
1926 0,
1927 nullptr
1928 );
1929 //-------------------------------------------------------------------------------------------------------------------
1930 static InstructionDefinition blt_rs1_rs2_imm(
1931  ISA32_RISCV64,
1932  "blt",
1933  (uint32_t)0x4063,
1934  (uint32_t) 0x707f,
1935  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1936  {
1937  etiss_uint64 rs2 = 0;
1938  static BitArrayRange R_rs2_0 (24,20);
1939  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
1940  rs2 += rs2_0;
1941  etiss_uint64 rs1 = 0;
1942  static BitArrayRange R_rs1_0 (19,15);
1943  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
1944  rs1 += rs1_0;
1945  etiss_int64 imm = 0;
1946  static BitArrayRange R_imm_12 (31,31);
1947  etiss_int64 imm_12 = R_imm_12.read(ba);
1948  imm += imm_12<<12;
1949  static BitArrayRange R_imm_5 (30,25);
1950  etiss_int64 imm_5 = R_imm_5.read(ba);
1951  imm += imm_5<<5;
1952  static BitArrayRange R_imm_1 (11,8);
1953  etiss_int64 imm_1 = R_imm_1.read(ba);
1954  imm += imm_1<<1;
1955  static BitArrayRange R_imm_11 (7,7);
1956  etiss_int64 imm_11 = R_imm_11.read(ba);
1957  imm += imm_11<<11;
1958  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
1959  partInit.getRegisterDependencies().add(reg_name[rs2],64);
1960  partInit.getRegisterDependencies().add(reg_name[rs1],64);
1961  partInit.getAffectedRegisters().add("instructionPointer",64);
1962  partInit.code() = std::string("//blt\n")+
1963  "etiss_uint32 temp = 0;\n"
1964  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
1965  #if RISCV64_Pipeline1
1966  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1967  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1968  "etiss_uint32 num_stages = 4;\n"
1969  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1970  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1971  #endif
1972  #if RISCV64_Pipeline2
1973  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
1974  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
1975  "etiss_uint32 num_stages = 4;\n"
1976  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
1977  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
1978  #endif
1979 
1980  "etiss_int64 imm_extended = 0;\n"
1981  "etiss_int64 choose1 = 0;\n"
1982 
1983 "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n"
1984 "{\n"
1985  "imm_extended = 0;\n"
1986  #if RISCV64_DEBUG_CALL
1987  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1988  #endif
1989 "}\n"
1990 
1991 "else\n"
1992 "{\n"
1993  "imm_extended = 4294967295;\n"
1994  #if RISCV64_DEBUG_CALL
1995  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
1996  #endif
1997  "imm_extended = (imm_extended << 32);\n"
1998  #if RISCV64_DEBUG_CALL
1999  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2000  #endif
2001  "imm_extended = imm_extended + 4294959104;\n"
2002  #if RISCV64_DEBUG_CALL
2003  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2004  #endif
2005 "}\n"
2006 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2007 #if RISCV64_DEBUG_CALL
2008 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2009 #endif
2010 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
2011 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2012 "{\n"
2013  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2014 "}\n"
2015 "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
2016 "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
2017 "{\n"
2018  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
2019 "}\n"
2020 "if((etiss_int64)cast_1 < (etiss_int64)cast_0)\n"
2021 "{\n"
2022  "etiss_int64 cast_2 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
2023  "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
2024  "{\n"
2025  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
2026  "}\n"
2027  "choose1 = (etiss_int64)cast_2 + imm_extended;\n"
2028  #if RISCV64_DEBUG_CALL
2029  "printf(\"choose1 = %#lx\\n\",choose1); \n"
2030  #endif
2031 // Explicit assignment to PC
2032 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2033 "}\n"
2034 
2035 "else\n"
2036 "{\n"
2037  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
2038  #if RISCV64_DEBUG_CALL
2039  "printf(\"choose1 = %#lx\\n\",choose1); \n"
2040  #endif
2041 "}\n"
2042 "cpu->instructionPointer = choose1;\n"
2043 #if RISCV64_DEBUG_CALL
2044 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
2045 #endif
2046 
2047  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
2048 
2049  "return 0;\n"
2050 ;
2051 return true;
2052 },
2053 0,
2054 nullptr
2055 );
2056 //-------------------------------------------------------------------------------------------------------------------
2057 static InstructionDefinition lbu_rd_imm_rs1_(
2058  ISA32_RISCV64,
2059  "lbu",
2060  (uint32_t)0x4003,
2061  (uint32_t) 0x707f,
2062  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2063  {
2064  etiss_uint64 rs1 = 0;
2065  static BitArrayRange R_rs1_0 (19,15);
2066  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
2067  rs1 += rs1_0;
2068  etiss_uint64 rd = 0;
2069  static BitArrayRange R_rd_0 (11,7);
2070  etiss_uint64 rd_0 = R_rd_0.read(ba);
2071  rd += rd_0;
2072  etiss_int64 imm = 0;
2073  static BitArrayRange R_imm_0 (31,20);
2074  etiss_int64 imm_0 = R_imm_0.read(ba);
2075  imm += imm_0;
2076  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2077  partInit.getRegisterDependencies().add(reg_name[rs1],64);
2078  partInit.getAffectedRegisters().add(reg_name[rd],64);
2079  partInit.getAffectedRegisters().add("instructionPointer",64);
2080  partInit.code() = std::string("//lbu\n")+
2081  "etiss_uint32 exception = 0;\n"
2082  "etiss_uint32 temp = 0;\n"
2083  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2084  #if RISCV64_Pipeline1
2085  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2086  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2087  "etiss_uint32 num_stages = 4;\n"
2088  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2089  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2090  #endif
2091  #if RISCV64_Pipeline2
2092  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2093  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2094  "etiss_uint32 num_stages = 4;\n"
2095  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2096  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2097  #endif
2098 
2099  "etiss_int64 offs = 0;\n"
2100  "etiss_int64 imm_extended = 0;\n"
2101 
2102 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
2103 "{\n"
2104  "imm_extended = 0;\n"
2105  #if RISCV64_DEBUG_CALL
2106  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2107  #endif
2108 "}\n"
2109 
2110 "else\n"
2111 "{\n"
2112  "imm_extended = 4294967295;\n"
2113  #if RISCV64_DEBUG_CALL
2114  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2115  #endif
2116  "imm_extended = (imm_extended << 32);\n"
2117  #if RISCV64_DEBUG_CALL
2118  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2119  #endif
2120  "imm_extended = imm_extended + 4294963200;\n"
2121  #if RISCV64_DEBUG_CALL
2122  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2123  #endif
2124 "}\n"
2125 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2126 #if RISCV64_DEBUG_CALL
2127 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2128 #endif
2129 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
2130 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2131 "{\n"
2132  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2133 "}\n"
2134 "offs = (etiss_int64)cast_0 + imm_extended;\n"
2135 #if RISCV64_DEBUG_CALL
2136 "printf(\"offs = %#lx\\n\",offs); \n"
2137 #endif
2138 "if(" + toString(rd) + " != 0)\n"
2139 "{\n"
2140  "etiss_uint8 MEM_offs;\n"
2141  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
2142  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,1);\n"
2143  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)MEM_offs;\n"
2144  #if RISCV64_DEBUG_CALL
2145  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
2146  #endif
2147 "}\n"
2148 
2149 
2150  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2151 
2152  "return exception;\n"
2153 ;
2154 return true;
2155 },
2156 0,
2157 nullptr
2158 );
2159 //-------------------------------------------------------------------------------------------------------------------
2160 static InstructionDefinition xori_rd_rs1_imm(
2161  ISA32_RISCV64,
2162  "xori",
2163  (uint32_t)0x4013,
2164  (uint32_t) 0x707f,
2165  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2166  {
2167  etiss_uint64 rs1 = 0;
2168  static BitArrayRange R_rs1_0 (19,15);
2169  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
2170  rs1 += rs1_0;
2171  etiss_uint64 rd = 0;
2172  static BitArrayRange R_rd_0 (11,7);
2173  etiss_uint64 rd_0 = R_rd_0.read(ba);
2174  rd += rd_0;
2175  etiss_int64 imm = 0;
2176  static BitArrayRange R_imm_0 (31,20);
2177  etiss_int64 imm_0 = R_imm_0.read(ba);
2178  imm += imm_0;
2179  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2180  partInit.getRegisterDependencies().add(reg_name[rs1],64);
2181  partInit.getAffectedRegisters().add(reg_name[rd],64);
2182  partInit.getAffectedRegisters().add("instructionPointer",64);
2183  partInit.code() = std::string("//xori\n")+
2184  "etiss_uint32 temp = 0;\n"
2185  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2186  #if RISCV64_Pipeline1
2187  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2188  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2189  "etiss_uint32 num_stages = 4;\n"
2190  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2191  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2192  #endif
2193  #if RISCV64_Pipeline2
2194  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2195  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2196  "etiss_uint32 num_stages = 4;\n"
2197  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2198  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2199  #endif
2200 
2201  "etiss_int64 imm_extended = 0;\n"
2202 
2203 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
2204 "{\n"
2205  "imm_extended = 0;\n"
2206  #if RISCV64_DEBUG_CALL
2207  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2208  #endif
2209 "}\n"
2210 
2211 "else\n"
2212 "{\n"
2213  "imm_extended = 4294967295;\n"
2214  #if RISCV64_DEBUG_CALL
2215  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2216  #endif
2217  "imm_extended = (imm_extended << 32);\n"
2218  #if RISCV64_DEBUG_CALL
2219  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2220  #endif
2221  "imm_extended = imm_extended + 4294963200;\n"
2222  #if RISCV64_DEBUG_CALL
2223  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2224  #endif
2225 "}\n"
2226 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2227 #if RISCV64_DEBUG_CALL
2228 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2229 #endif
2230 "if(" + toString(rd) + " != 0)\n"
2231 "{\n"
2232  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
2233  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2234  "{\n"
2235  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2236  "}\n"
2237  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_0 ^ imm_extended);\n"
2238  #if RISCV64_DEBUG_CALL
2239  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
2240  #endif
2241 "}\n"
2242 
2243 
2244  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2245 
2246 ;
2247 return true;
2248 },
2249 0,
2250 nullptr
2251 );
2252 //-------------------------------------------------------------------------------------------------------------------
2253 static InstructionDefinition bge_rs1_rs2_imm(
2254  ISA32_RISCV64,
2255  "bge",
2256  (uint32_t)0x5063,
2257  (uint32_t) 0x707f,
2258  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2259  {
2260  etiss_uint64 rs2 = 0;
2261  static BitArrayRange R_rs2_0 (24,20);
2262  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
2263  rs2 += rs2_0;
2264  etiss_uint64 rs1 = 0;
2265  static BitArrayRange R_rs1_0 (19,15);
2266  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
2267  rs1 += rs1_0;
2268  etiss_int64 imm = 0;
2269  static BitArrayRange R_imm_12 (31,31);
2270  etiss_int64 imm_12 = R_imm_12.read(ba);
2271  imm += imm_12<<12;
2272  static BitArrayRange R_imm_5 (30,25);
2273  etiss_int64 imm_5 = R_imm_5.read(ba);
2274  imm += imm_5<<5;
2275  static BitArrayRange R_imm_1 (11,8);
2276  etiss_int64 imm_1 = R_imm_1.read(ba);
2277  imm += imm_1<<1;
2278  static BitArrayRange R_imm_11 (7,7);
2279  etiss_int64 imm_11 = R_imm_11.read(ba);
2280  imm += imm_11<<11;
2281  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2282  partInit.getRegisterDependencies().add(reg_name[rs2],64);
2283  partInit.getRegisterDependencies().add(reg_name[rs1],64);
2284  partInit.getAffectedRegisters().add("instructionPointer",64);
2285  partInit.code() = std::string("//bge\n")+
2286  "etiss_uint32 temp = 0;\n"
2287  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2288  #if RISCV64_Pipeline1
2289  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2290  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2291  "etiss_uint32 num_stages = 4;\n"
2292  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2293  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2294  #endif
2295  #if RISCV64_Pipeline2
2296  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2297  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2298  "etiss_uint32 num_stages = 4;\n"
2299  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2300  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2301  #endif
2302 
2303  "etiss_int64 imm_extended = 0;\n"
2304  "etiss_int64 choose1 = 0;\n"
2305 
2306 "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n"
2307 "{\n"
2308  "imm_extended = 0;\n"
2309  #if RISCV64_DEBUG_CALL
2310  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2311  #endif
2312 "}\n"
2313 
2314 "else\n"
2315 "{\n"
2316  "imm_extended = 4294967295;\n"
2317  #if RISCV64_DEBUG_CALL
2318  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2319  #endif
2320  "imm_extended = (imm_extended << 32);\n"
2321  #if RISCV64_DEBUG_CALL
2322  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2323  #endif
2324  "imm_extended = imm_extended + 4294959104;\n"
2325  #if RISCV64_DEBUG_CALL
2326  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2327  #endif
2328 "}\n"
2329 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2330 #if RISCV64_DEBUG_CALL
2331 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2332 #endif
2333 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
2334 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2335 "{\n"
2336  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2337 "}\n"
2338 "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
2339 "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
2340 "{\n"
2341  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
2342 "}\n"
2343 "if((etiss_int64)cast_1 >= (etiss_int64)cast_0)\n"
2344 "{\n"
2345  "etiss_int64 cast_2 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
2346  "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
2347  "{\n"
2348  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
2349  "}\n"
2350  "choose1 = (etiss_int64)cast_2 + imm_extended;\n"
2351  #if RISCV64_DEBUG_CALL
2352  "printf(\"choose1 = %#lx\\n\",choose1); \n"
2353  #endif
2354 // Explicit assignment to PC
2355 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2356 "}\n"
2357 
2358 "else\n"
2359 "{\n"
2360  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
2361  #if RISCV64_DEBUG_CALL
2362  "printf(\"choose1 = %#lx\\n\",choose1); \n"
2363  #endif
2364 "}\n"
2365 "cpu->instructionPointer = choose1;\n"
2366 #if RISCV64_DEBUG_CALL
2367 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
2368 #endif
2369 
2370  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
2371 
2372  "return 0;\n"
2373 ;
2374 return true;
2375 },
2376 0,
2377 nullptr
2378 );
2379 //-------------------------------------------------------------------------------------------------------------------
2380 static InstructionDefinition lhu_rd_imm_rs1_(
2381  ISA32_RISCV64,
2382  "lhu",
2383  (uint32_t)0x5003,
2384  (uint32_t) 0x707f,
2385  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2386  {
2387  etiss_uint64 rs1 = 0;
2388  static BitArrayRange R_rs1_0 (19,15);
2389  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
2390  rs1 += rs1_0;
2391  etiss_uint64 rd = 0;
2392  static BitArrayRange R_rd_0 (11,7);
2393  etiss_uint64 rd_0 = R_rd_0.read(ba);
2394  rd += rd_0;
2395  etiss_int64 imm = 0;
2396  static BitArrayRange R_imm_0 (31,20);
2397  etiss_int64 imm_0 = R_imm_0.read(ba);
2398  imm += imm_0;
2399  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2400  partInit.getRegisterDependencies().add(reg_name[rs1],64);
2401  partInit.getAffectedRegisters().add(reg_name[rd],64);
2402  partInit.getAffectedRegisters().add("instructionPointer",64);
2403  partInit.code() = std::string("//lhu\n")+
2404  "etiss_uint32 exception = 0;\n"
2405  "etiss_uint32 temp = 0;\n"
2406  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2407  #if RISCV64_Pipeline1
2408  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2409  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2410  "etiss_uint32 num_stages = 4;\n"
2411  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2412  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2413  #endif
2414  #if RISCV64_Pipeline2
2415  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2416  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2417  "etiss_uint32 num_stages = 4;\n"
2418  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2419  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2420  #endif
2421 
2422  "etiss_int64 offs = 0;\n"
2423  "etiss_int64 imm_extended = 0;\n"
2424 
2425 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
2426 "{\n"
2427  "imm_extended = 0;\n"
2428  #if RISCV64_DEBUG_CALL
2429  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2430  #endif
2431 "}\n"
2432 
2433 "else\n"
2434 "{\n"
2435  "imm_extended = 4294967295;\n"
2436  #if RISCV64_DEBUG_CALL
2437  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2438  #endif
2439  "imm_extended = (imm_extended << 32);\n"
2440  #if RISCV64_DEBUG_CALL
2441  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2442  #endif
2443  "imm_extended = imm_extended + 4294963200;\n"
2444  #if RISCV64_DEBUG_CALL
2445  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2446  #endif
2447 "}\n"
2448 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2449 #if RISCV64_DEBUG_CALL
2450 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2451 #endif
2452 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
2453 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2454 "{\n"
2455  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2456 "}\n"
2457 "offs = (etiss_int64)cast_0 + imm_extended;\n"
2458 #if RISCV64_DEBUG_CALL
2459 "printf(\"offs = %#lx\\n\",offs); \n"
2460 #endif
2461 "if(" + toString(rd) + " != 0)\n"
2462 "{\n"
2463  "etiss_uint16 MEM_offs;\n"
2464  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
2465  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,2);\n"
2466  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)MEM_offs;\n"
2467  #if RISCV64_DEBUG_CALL
2468  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
2469  #endif
2470 "}\n"
2471 
2472 
2473  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2474 
2475  "return exception;\n"
2476 ;
2477 return true;
2478 },
2479 0,
2480 nullptr
2481 );
2482 //-------------------------------------------------------------------------------------------------------------------
2483 static InstructionDefinition csrrwi_rd_csr_zimm(
2484  ISA32_RISCV64,
2485  "csrrwi",
2486  (uint32_t)0x5073,
2487  (uint32_t) 0x707f,
2488  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2489  {
2490  etiss_uint64 rd = 0;
2491  static BitArrayRange R_rd_0 (11,7);
2492  etiss_uint64 rd_0 = R_rd_0.read(ba);
2493  rd += rd_0;
2494  etiss_uint64 csr = 0;
2495  static BitArrayRange R_csr_0 (31,20);
2496  etiss_uint64 csr_0 = R_csr_0.read(ba);
2497  csr += csr_0;
2498  etiss_uint64 zimm = 0;
2499  static BitArrayRange R_zimm_0 (19,15);
2500  etiss_uint64 zimm_0 = R_zimm_0.read(ba);
2501  zimm += zimm_0;
2502  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2503  partInit.getAffectedRegisters().add(reg_name[rd],64);
2504  partInit.getAffectedRegisters().add("instructionPointer",64);
2505  partInit.code() = std::string("//csrrwi\n")+
2506  "etiss_uint32 temp = 0;\n"
2507  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2508  #if RISCV64_Pipeline1
2509  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2510  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2511  "etiss_uint32 num_stages = 4;\n"
2512  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2513  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2514  #endif
2515  #if RISCV64_Pipeline2
2516  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2517  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2518  "etiss_uint32 num_stages = 4;\n"
2519  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2520  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2521  #endif
2522 
2523  "etiss_int64 mAddr = 0;\n"
2524  "etiss_int64 writeMask = 0;\n"
2525  "etiss_int64 writeMaskU = 0;\n"
2526  "etiss_int64 sAddr = 0;\n"
2527  "etiss_int64 writeMaskS = 0;\n"
2528  "etiss_int64 uAddr = 0;\n"
2529  "etiss_int64 writeMaskM = 0;\n"
2530 
2531 "if(" + toString(rd) + " != 0)\n"
2532 "{\n"
2533  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((RISCV64*)cpu)->CSR[" + toString(csr) + "];\n"
2534  #if RISCV64_DEBUG_CALL
2535  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
2536  #endif
2537 "}\n"
2538 
2539 "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
2540 "{\n"
2541  "uAddr = 0;\n"
2542  #if RISCV64_DEBUG_CALL
2543  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
2544  #endif
2545  "sAddr = 256;\n"
2546  #if RISCV64_DEBUG_CALL
2547  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
2548  #endif
2549  "mAddr = 768;\n"
2550  #if RISCV64_DEBUG_CALL
2551  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
2552  #endif
2553  "writeMaskM = -9223372036846388805;\n"
2554  #if RISCV64_DEBUG_CALL
2555  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
2556  #endif
2557  "writeMaskS = -9223372036853866189;\n"
2558  #if RISCV64_DEBUG_CALL
2559  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
2560  #endif
2561  "writeMaskU = -9223372036853866479;\n"
2562  #if RISCV64_DEBUG_CALL
2563  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
2564  #endif
2565 "}\n"
2566 
2567 "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
2568 "{\n"
2569  "uAddr = 68;\n"
2570  #if RISCV64_DEBUG_CALL
2571  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
2572  #endif
2573  "sAddr = 324;\n"
2574  #if RISCV64_DEBUG_CALL
2575  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
2576  #endif
2577  "mAddr = 836;\n"
2578  #if RISCV64_DEBUG_CALL
2579  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
2580  #endif
2581  "writeMaskM = 3003;\n"
2582  #if RISCV64_DEBUG_CALL
2583  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
2584  #endif
2585  "writeMaskS = 819;\n"
2586  #if RISCV64_DEBUG_CALL
2587  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
2588  #endif
2589  "writeMaskU = 273;\n"
2590  #if RISCV64_DEBUG_CALL
2591  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
2592  #endif
2593 "}\n"
2594 
2595 "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
2596 "{\n"
2597  "uAddr = 4;\n"
2598  #if RISCV64_DEBUG_CALL
2599  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
2600  #endif
2601  "sAddr = 260;\n"
2602  #if RISCV64_DEBUG_CALL
2603  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
2604  #endif
2605  "mAddr = 772;\n"
2606  #if RISCV64_DEBUG_CALL
2607  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
2608  #endif
2609  "writeMaskM = 3003;\n"
2610  #if RISCV64_DEBUG_CALL
2611  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
2612  #endif
2613  "writeMaskS = 819;\n"
2614  #if RISCV64_DEBUG_CALL
2615  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
2616  #endif
2617  "writeMaskU = 273;\n"
2618  #if RISCV64_DEBUG_CALL
2619  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
2620  #endif
2621 "}\n"
2622 
2623 "if(uAddr != sAddr)\n"
2624 "{\n"
2625  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
2626  "{\n"
2627  "writeMask = writeMaskM;\n"
2628  #if RISCV64_DEBUG_CALL
2629  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
2630  #endif
2631  "}\n"
2632 
2633  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
2634  "{\n"
2635  "writeMask = writeMaskS;\n"
2636  #if RISCV64_DEBUG_CALL
2637  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
2638  #endif
2639  "}\n"
2640 
2641  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
2642  "{\n"
2643  "writeMask = writeMaskU;\n"
2644  #if RISCV64_DEBUG_CALL
2645  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
2646  #endif
2647  "}\n"
2648 
2649  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((etiss_uint64)" + toString(zimm) + " & writeMask))&0xffffffffffffffff;\n"
2650  #if RISCV64_DEBUG_CALL
2651  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
2652  #endif
2653  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
2654  #if RISCV64_DEBUG_CALL
2655  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
2656  #endif
2657  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
2658  #if RISCV64_DEBUG_CALL
2659  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
2660  #endif
2661 "}\n"
2662 
2663 "else\n"
2664 "{\n"
2665  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = (etiss_uint64)" + toString(zimm) + ";\n"
2666  #if RISCV64_DEBUG_CALL
2667  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
2668  #endif
2669 "}\n"
2670 
2671  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2672 
2673 ;
2674 return true;
2675 },
2676 0,
2677 nullptr
2678 );
2679 //-------------------------------------------------------------------------------------------------------------------
2680 static InstructionDefinition bltu_rs1_rs2_imm(
2681  ISA32_RISCV64,
2682  "bltu",
2683  (uint32_t)0x6063,
2684  (uint32_t) 0x707f,
2685  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2686  {
2687  etiss_uint64 rs2 = 0;
2688  static BitArrayRange R_rs2_0 (24,20);
2689  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
2690  rs2 += rs2_0;
2691  etiss_uint64 rs1 = 0;
2692  static BitArrayRange R_rs1_0 (19,15);
2693  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
2694  rs1 += rs1_0;
2695  etiss_int64 imm = 0;
2696  static BitArrayRange R_imm_12 (31,31);
2697  etiss_int64 imm_12 = R_imm_12.read(ba);
2698  imm += imm_12<<12;
2699  static BitArrayRange R_imm_5 (30,25);
2700  etiss_int64 imm_5 = R_imm_5.read(ba);
2701  imm += imm_5<<5;
2702  static BitArrayRange R_imm_1 (11,8);
2703  etiss_int64 imm_1 = R_imm_1.read(ba);
2704  imm += imm_1<<1;
2705  static BitArrayRange R_imm_11 (7,7);
2706  etiss_int64 imm_11 = R_imm_11.read(ba);
2707  imm += imm_11<<11;
2708  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2709  partInit.getRegisterDependencies().add(reg_name[rs2],64);
2710  partInit.getRegisterDependencies().add(reg_name[rs1],64);
2711  partInit.getAffectedRegisters().add("instructionPointer",64);
2712  partInit.code() = std::string("//bltu\n")+
2713  "etiss_uint32 temp = 0;\n"
2714  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2715  #if RISCV64_Pipeline1
2716  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2717  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2718  "etiss_uint32 num_stages = 4;\n"
2719  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2720  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2721  #endif
2722  #if RISCV64_Pipeline2
2723  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2724  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2725  "etiss_uint32 num_stages = 4;\n"
2726  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2727  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2728  #endif
2729 
2730  "etiss_int64 imm_extended = 0;\n"
2731  "etiss_int64 choose1 = 0;\n"
2732 
2733 "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n"
2734 "{\n"
2735  "imm_extended = 0;\n"
2736  #if RISCV64_DEBUG_CALL
2737  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2738  #endif
2739 "}\n"
2740 
2741 "else\n"
2742 "{\n"
2743  "imm_extended = 4294967295;\n"
2744  #if RISCV64_DEBUG_CALL
2745  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2746  #endif
2747  "imm_extended = (imm_extended << 32);\n"
2748  #if RISCV64_DEBUG_CALL
2749  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2750  #endif
2751  "imm_extended = imm_extended + 4294959104;\n"
2752  #if RISCV64_DEBUG_CALL
2753  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2754  #endif
2755 "}\n"
2756 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2757 #if RISCV64_DEBUG_CALL
2758 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2759 #endif
2760 "if(*((RISCV64*)cpu)->X[" + toString(rs1) + "] < *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
2761 "{\n"
2762  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
2763  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2764  "{\n"
2765  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2766  "}\n"
2767  "choose1 = (etiss_int64)cast_0 + imm_extended;\n"
2768  #if RISCV64_DEBUG_CALL
2769  "printf(\"choose1 = %#lx\\n\",choose1); \n"
2770  #endif
2771 // Explicit assignment to PC
2772 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2773 "}\n"
2774 
2775 "else\n"
2776 "{\n"
2777  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
2778  #if RISCV64_DEBUG_CALL
2779  "printf(\"choose1 = %#lx\\n\",choose1); \n"
2780  #endif
2781 "}\n"
2782 "cpu->instructionPointer = choose1;\n"
2783 #if RISCV64_DEBUG_CALL
2784 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
2785 #endif
2786 
2787  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
2788 
2789  "return 0;\n"
2790 ;
2791 return true;
2792 },
2793 0,
2794 nullptr
2795 );
2796 //-------------------------------------------------------------------------------------------------------------------
2797 static InstructionDefinition ori_rd_rs1_imm(
2798  ISA32_RISCV64,
2799  "ori",
2800  (uint32_t)0x6013,
2801  (uint32_t) 0x707f,
2802  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2803  {
2804  etiss_uint64 rs1 = 0;
2805  static BitArrayRange R_rs1_0 (19,15);
2806  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
2807  rs1 += rs1_0;
2808  etiss_uint64 rd = 0;
2809  static BitArrayRange R_rd_0 (11,7);
2810  etiss_uint64 rd_0 = R_rd_0.read(ba);
2811  rd += rd_0;
2812  etiss_int64 imm = 0;
2813  static BitArrayRange R_imm_0 (31,20);
2814  etiss_int64 imm_0 = R_imm_0.read(ba);
2815  imm += imm_0;
2816  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2817  partInit.getRegisterDependencies().add(reg_name[rs1],64);
2818  partInit.getAffectedRegisters().add(reg_name[rd],64);
2819  partInit.getAffectedRegisters().add("instructionPointer",64);
2820  partInit.code() = std::string("//ori\n")+
2821  "etiss_uint32 temp = 0;\n"
2822  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2823  #if RISCV64_Pipeline1
2824  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2825  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2826  "etiss_uint32 num_stages = 4;\n"
2827  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2828  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2829  #endif
2830  #if RISCV64_Pipeline2
2831  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2832  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2833  "etiss_uint32 num_stages = 4;\n"
2834  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2835  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2836  #endif
2837 
2838  "etiss_int64 imm_extended = 0;\n"
2839 
2840 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
2841 "{\n"
2842  "imm_extended = 0;\n"
2843  #if RISCV64_DEBUG_CALL
2844  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2845  #endif
2846 "}\n"
2847 
2848 "else\n"
2849 "{\n"
2850  "imm_extended = 4294967295;\n"
2851  #if RISCV64_DEBUG_CALL
2852  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
2853  #endif
2854  "imm_extended = (imm_extended << 32);\n"
2855  #if RISCV64_DEBUG_CALL
2856  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2857  #endif
2858  "imm_extended = imm_extended + 4294963200;\n"
2859  #if RISCV64_DEBUG_CALL
2860  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2861  #endif
2862 "}\n"
2863 "imm_extended = imm_extended + " + toString(imm) + ";\n"
2864 #if RISCV64_DEBUG_CALL
2865 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
2866 #endif
2867 "if(" + toString(rd) + " != 0)\n"
2868 "{\n"
2869  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
2870  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
2871  "{\n"
2872  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
2873  "}\n"
2874  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_0 | imm_extended);\n"
2875  #if RISCV64_DEBUG_CALL
2876  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
2877  #endif
2878 "}\n"
2879 
2880 
2881  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
2882 
2883 ;
2884 return true;
2885 },
2886 0,
2887 nullptr
2888 );
2889 //-------------------------------------------------------------------------------------------------------------------
2890 static InstructionDefinition csrrsi_rd_csr_zimm(
2891  ISA32_RISCV64,
2892  "csrrsi",
2893  (uint32_t)0x6073,
2894  (uint32_t) 0x707f,
2895  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2896  {
2897  etiss_uint64 rd = 0;
2898  static BitArrayRange R_rd_0 (11,7);
2899  etiss_uint64 rd_0 = R_rd_0.read(ba);
2900  rd += rd_0;
2901  etiss_uint64 csr = 0;
2902  static BitArrayRange R_csr_0 (31,20);
2903  etiss_uint64 csr_0 = R_csr_0.read(ba);
2904  csr += csr_0;
2905  etiss_uint64 zimm = 0;
2906  static BitArrayRange R_zimm_0 (19,15);
2907  etiss_uint64 zimm_0 = R_zimm_0.read(ba);
2908  zimm += zimm_0;
2909  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
2910  partInit.getAffectedRegisters().add(reg_name[rd],64);
2911  partInit.getAffectedRegisters().add("instructionPointer",64);
2912  partInit.code() = std::string("//csrrsi\n")+
2913  "etiss_uint32 temp = 0;\n"
2914  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
2915  #if RISCV64_Pipeline1
2916  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2917  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2918  "etiss_uint32 num_stages = 4;\n"
2919  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2920  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2921  #endif
2922  #if RISCV64_Pipeline2
2923  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
2924  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
2925  "etiss_uint32 num_stages = 4;\n"
2926  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
2927  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
2928  #endif
2929 
2930  "etiss_uint64 res = 0;\n"
2931  "etiss_int64 mAddr = 0;\n"
2932  "etiss_int64 writeMask = 0;\n"
2933  "etiss_int64 writeMaskU = 0;\n"
2934  "etiss_int64 sAddr = 0;\n"
2935  "etiss_int64 writeMaskS = 0;\n"
2936  "etiss_int64 uAddr = 0;\n"
2937  "etiss_int64 writeMaskM = 0;\n"
2938 
2939 "res = ((RISCV64*)cpu)->CSR[" + toString(csr) + "];\n"
2940 #if RISCV64_DEBUG_CALL
2941 "printf(\"res = %#lx\\n\",res); \n"
2942 #endif
2943 "if(" + toString(zimm) + " != 0)\n"
2944 "{\n"
2945  "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
2946  "{\n"
2947  "uAddr = 0;\n"
2948  #if RISCV64_DEBUG_CALL
2949  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
2950  #endif
2951  "sAddr = 256;\n"
2952  #if RISCV64_DEBUG_CALL
2953  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
2954  #endif
2955  "mAddr = 768;\n"
2956  #if RISCV64_DEBUG_CALL
2957  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
2958  #endif
2959  "writeMaskM = -9223372036846388805;\n"
2960  #if RISCV64_DEBUG_CALL
2961  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
2962  #endif
2963  "writeMaskS = -9223372036853866189;\n"
2964  #if RISCV64_DEBUG_CALL
2965  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
2966  #endif
2967  "writeMaskU = -9223372036853866479;\n"
2968  #if RISCV64_DEBUG_CALL
2969  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
2970  #endif
2971  "}\n"
2972 
2973  "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
2974  "{\n"
2975  "uAddr = 68;\n"
2976  #if RISCV64_DEBUG_CALL
2977  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
2978  #endif
2979  "sAddr = 324;\n"
2980  #if RISCV64_DEBUG_CALL
2981  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
2982  #endif
2983  "mAddr = 836;\n"
2984  #if RISCV64_DEBUG_CALL
2985  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
2986  #endif
2987  "writeMaskM = 3003;\n"
2988  #if RISCV64_DEBUG_CALL
2989  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
2990  #endif
2991  "writeMaskS = 819;\n"
2992  #if RISCV64_DEBUG_CALL
2993  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
2994  #endif
2995  "writeMaskU = 273;\n"
2996  #if RISCV64_DEBUG_CALL
2997  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
2998  #endif
2999  "}\n"
3000 
3001  "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
3002  "{\n"
3003  "uAddr = 4;\n"
3004  #if RISCV64_DEBUG_CALL
3005  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
3006  #endif
3007  "sAddr = 260;\n"
3008  #if RISCV64_DEBUG_CALL
3009  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
3010  #endif
3011  "mAddr = 772;\n"
3012  #if RISCV64_DEBUG_CALL
3013  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
3014  #endif
3015  "writeMaskM = 3003;\n"
3016  #if RISCV64_DEBUG_CALL
3017  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
3018  #endif
3019  "writeMaskS = 819;\n"
3020  #if RISCV64_DEBUG_CALL
3021  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
3022  #endif
3023  "writeMaskU = 273;\n"
3024  #if RISCV64_DEBUG_CALL
3025  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
3026  #endif
3027  "}\n"
3028 
3029  "if(uAddr != sAddr)\n"
3030  "{\n"
3031  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
3032  "{\n"
3033  "writeMask = writeMaskM;\n"
3034  #if RISCV64_DEBUG_CALL
3035  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
3036  #endif
3037  "}\n"
3038 
3039  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
3040  "{\n"
3041  "writeMask = writeMaskS;\n"
3042  #if RISCV64_DEBUG_CALL
3043  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
3044  #endif
3045  "}\n"
3046 
3047  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
3048  "{\n"
3049  "writeMask = writeMaskU;\n"
3050  #if RISCV64_DEBUG_CALL
3051  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
3052  #endif
3053  "}\n"
3054 
3055  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((res | (etiss_uint64)" + toString(zimm) + ") & writeMask))&0xffffffffffffffff;\n"
3056  #if RISCV64_DEBUG_CALL
3057  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
3058  #endif
3059  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
3060  #if RISCV64_DEBUG_CALL
3061  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
3062  #endif
3063  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
3064  #if RISCV64_DEBUG_CALL
3065  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
3066  #endif
3067  "}\n"
3068 
3069  "else\n"
3070  "{\n"
3071  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = (res | (etiss_uint64)" + toString(zimm) + ");\n"
3072  #if RISCV64_DEBUG_CALL
3073  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
3074  #endif
3075  "}\n"
3076 "}\n"
3077 
3078 "if(" + toString(rd) + " != 0)\n"
3079 "{\n"
3080  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
3081  #if RISCV64_DEBUG_CALL
3082  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
3083  #endif
3084 "}\n"
3085 
3086 
3087  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3088 
3089 ;
3090 return true;
3091 },
3092 0,
3093 nullptr
3094 );
3095 //-------------------------------------------------------------------------------------------------------------------
3096 static InstructionDefinition lwu_rd_imm_rs1_(
3097  ISA32_RISCV64,
3098  "lwu",
3099  (uint32_t)0x6003,
3100  (uint32_t) 0x707f,
3101  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3102  {
3103  etiss_uint64 rs1 = 0;
3104  static BitArrayRange R_rs1_0 (19,15);
3105  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3106  rs1 += rs1_0;
3107  etiss_uint64 rd = 0;
3108  static BitArrayRange R_rd_0 (11,7);
3109  etiss_uint64 rd_0 = R_rd_0.read(ba);
3110  rd += rd_0;
3111  etiss_int64 imm = 0;
3112  static BitArrayRange R_imm_0 (31,20);
3113  etiss_int64 imm_0 = R_imm_0.read(ba);
3114  imm += imm_0;
3115  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3116  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3117  partInit.getAffectedRegisters().add(reg_name[rd],64);
3118  partInit.getAffectedRegisters().add("instructionPointer",64);
3119  partInit.code() = std::string("//lwu\n")+
3120  "etiss_uint32 exception = 0;\n"
3121  "etiss_uint32 temp = 0;\n"
3122  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3123  #if RISCV64_Pipeline1
3124  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3125  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3126  "etiss_uint32 num_stages = 4;\n"
3127  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3128  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3129  #endif
3130  #if RISCV64_Pipeline2
3131  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3132  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3133  "etiss_uint32 num_stages = 4;\n"
3134  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3135  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3136  #endif
3137 
3138  "etiss_int64 offs = 0;\n"
3139  "etiss_int64 imm_extended = 0;\n"
3140 
3141 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
3142 "{\n"
3143  "imm_extended = 0;\n"
3144  #if RISCV64_DEBUG_CALL
3145  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3146  #endif
3147 "}\n"
3148 
3149 "else\n"
3150 "{\n"
3151  "imm_extended = 4294967295;\n"
3152  #if RISCV64_DEBUG_CALL
3153  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3154  #endif
3155  "imm_extended = (imm_extended << 32);\n"
3156  #if RISCV64_DEBUG_CALL
3157  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3158  #endif
3159  "imm_extended = imm_extended + 4294963200;\n"
3160  #if RISCV64_DEBUG_CALL
3161  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3162  #endif
3163 "}\n"
3164 "imm_extended = imm_extended + " + toString(imm) + ";\n"
3165 #if RISCV64_DEBUG_CALL
3166 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3167 #endif
3168 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
3169 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
3170 "{\n"
3171  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
3172 "}\n"
3173 "offs = (etiss_int64)cast_0 + imm_extended;\n"
3174 #if RISCV64_DEBUG_CALL
3175 "printf(\"offs = %#lx\\n\",offs); \n"
3176 #endif
3177 "if(" + toString(rd) + " != 0)\n"
3178 "{\n"
3179  "etiss_uint32 MEM_offs;\n"
3180  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
3181  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
3182  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)MEM_offs;\n"
3183  #if RISCV64_DEBUG_CALL
3184  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
3185  #endif
3186 "}\n"
3187 
3188 
3189  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3190 
3191  "return exception;\n"
3192 ;
3193 return true;
3194 },
3195 0,
3196 nullptr
3197 );
3198 //-------------------------------------------------------------------------------------------------------------------
3199 static InstructionDefinition bgeu_rs1_rs2_imm(
3200  ISA32_RISCV64,
3201  "bgeu",
3202  (uint32_t)0x7063,
3203  (uint32_t) 0x707f,
3204  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3205  {
3206  etiss_uint64 rs2 = 0;
3207  static BitArrayRange R_rs2_0 (24,20);
3208  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
3209  rs2 += rs2_0;
3210  etiss_uint64 rs1 = 0;
3211  static BitArrayRange R_rs1_0 (19,15);
3212  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3213  rs1 += rs1_0;
3214  etiss_int64 imm = 0;
3215  static BitArrayRange R_imm_12 (31,31);
3216  etiss_int64 imm_12 = R_imm_12.read(ba);
3217  imm += imm_12<<12;
3218  static BitArrayRange R_imm_5 (30,25);
3219  etiss_int64 imm_5 = R_imm_5.read(ba);
3220  imm += imm_5<<5;
3221  static BitArrayRange R_imm_1 (11,8);
3222  etiss_int64 imm_1 = R_imm_1.read(ba);
3223  imm += imm_1<<1;
3224  static BitArrayRange R_imm_11 (7,7);
3225  etiss_int64 imm_11 = R_imm_11.read(ba);
3226  imm += imm_11<<11;
3227  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3228  partInit.getRegisterDependencies().add(reg_name[rs2],64);
3229  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3230  partInit.getAffectedRegisters().add("instructionPointer",64);
3231  partInit.code() = std::string("//bgeu\n")+
3232  "etiss_uint32 temp = 0;\n"
3233  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3234  #if RISCV64_Pipeline1
3235  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3236  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3237  "etiss_uint32 num_stages = 4;\n"
3238  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3239  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3240  #endif
3241  #if RISCV64_Pipeline2
3242  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3243  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3244  "etiss_uint32 num_stages = 4;\n"
3245  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3246  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3247  #endif
3248 
3249  "etiss_int64 imm_extended = 0;\n"
3250  "etiss_int64 choose1 = 0;\n"
3251 
3252 "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n"
3253 "{\n"
3254  "imm_extended = 0;\n"
3255  #if RISCV64_DEBUG_CALL
3256  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3257  #endif
3258 "}\n"
3259 
3260 "else\n"
3261 "{\n"
3262  "imm_extended = 4294967295;\n"
3263  #if RISCV64_DEBUG_CALL
3264  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3265  #endif
3266  "imm_extended = (imm_extended << 32);\n"
3267  #if RISCV64_DEBUG_CALL
3268  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3269  #endif
3270  "imm_extended = imm_extended + 4294959104;\n"
3271  #if RISCV64_DEBUG_CALL
3272  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3273  #endif
3274 "}\n"
3275 "imm_extended = imm_extended + " + toString(imm) + ";\n"
3276 #if RISCV64_DEBUG_CALL
3277 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3278 #endif
3279 "if(*((RISCV64*)cpu)->X[" + toString(rs1) + "] >= *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
3280 "{\n"
3281  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
3282  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
3283  "{\n"
3284  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
3285  "}\n"
3286  "choose1 = (etiss_int64)cast_0 + imm_extended;\n"
3287  #if RISCV64_DEBUG_CALL
3288  "printf(\"choose1 = %#lx\\n\",choose1); \n"
3289  #endif
3290 // Explicit assignment to PC
3291 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3292 "}\n"
3293 
3294 "else\n"
3295 "{\n"
3296  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 4;\n"
3297  #if RISCV64_DEBUG_CALL
3298  "printf(\"choose1 = %#lx\\n\",choose1); \n"
3299  #endif
3300 "}\n"
3301 "cpu->instructionPointer = choose1;\n"
3302 #if RISCV64_DEBUG_CALL
3303 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
3304 #endif
3305 
3306  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
3307 
3308  "return 0;\n"
3309 ;
3310 return true;
3311 },
3312 0,
3313 nullptr
3314 );
3315 //-------------------------------------------------------------------------------------------------------------------
3316 static InstructionDefinition andi_rd_rs1_imm(
3317  ISA32_RISCV64,
3318  "andi",
3319  (uint32_t)0x7013,
3320  (uint32_t) 0x707f,
3321  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3322  {
3323  etiss_uint64 rs1 = 0;
3324  static BitArrayRange R_rs1_0 (19,15);
3325  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3326  rs1 += rs1_0;
3327  etiss_uint64 rd = 0;
3328  static BitArrayRange R_rd_0 (11,7);
3329  etiss_uint64 rd_0 = R_rd_0.read(ba);
3330  rd += rd_0;
3331  etiss_int64 imm = 0;
3332  static BitArrayRange R_imm_0 (31,20);
3333  etiss_int64 imm_0 = R_imm_0.read(ba);
3334  imm += imm_0;
3335  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3336  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3337  partInit.getAffectedRegisters().add(reg_name[rd],64);
3338  partInit.getAffectedRegisters().add("instructionPointer",64);
3339  partInit.code() = std::string("//andi\n")+
3340  "etiss_uint32 temp = 0;\n"
3341  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3342  #if RISCV64_Pipeline1
3343  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3344  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3345  "etiss_uint32 num_stages = 4;\n"
3346  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3347  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3348  #endif
3349  #if RISCV64_Pipeline2
3350  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3351  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3352  "etiss_uint32 num_stages = 4;\n"
3353  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3354  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3355  #endif
3356 
3357  "etiss_int64 imm_extended = 0;\n"
3358 
3359 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
3360 "{\n"
3361  "imm_extended = 0;\n"
3362  #if RISCV64_DEBUG_CALL
3363  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3364  #endif
3365 "}\n"
3366 
3367 "else\n"
3368 "{\n"
3369  "imm_extended = 4294967295;\n"
3370  #if RISCV64_DEBUG_CALL
3371  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3372  #endif
3373  "imm_extended = (imm_extended << 32);\n"
3374  #if RISCV64_DEBUG_CALL
3375  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3376  #endif
3377  "imm_extended = imm_extended + 4294963200;\n"
3378  #if RISCV64_DEBUG_CALL
3379  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3380  #endif
3381 "}\n"
3382 "imm_extended = imm_extended + " + toString(imm) + ";\n"
3383 #if RISCV64_DEBUG_CALL
3384 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3385 #endif
3386 "if(" + toString(rd) + " != 0)\n"
3387 "{\n"
3388  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
3389  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
3390  "{\n"
3391  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
3392  "}\n"
3393  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_0 & imm_extended);\n"
3394  #if RISCV64_DEBUG_CALL
3395  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
3396  #endif
3397 "}\n"
3398 
3399 
3400  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3401 
3402 ;
3403 return true;
3404 },
3405 0,
3406 nullptr
3407 );
3408 //-------------------------------------------------------------------------------------------------------------------
3409 static InstructionDefinition csrrci_rd_csr_zimm(
3410  ISA32_RISCV64,
3411  "csrrci",
3412  (uint32_t)0x7073,
3413  (uint32_t) 0x707f,
3414  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3415  {
3416  etiss_uint64 rd = 0;
3417  static BitArrayRange R_rd_0 (11,7);
3418  etiss_uint64 rd_0 = R_rd_0.read(ba);
3419  rd += rd_0;
3420  etiss_uint64 csr = 0;
3421  static BitArrayRange R_csr_0 (31,20);
3422  etiss_uint64 csr_0 = R_csr_0.read(ba);
3423  csr += csr_0;
3424  etiss_uint64 zimm = 0;
3425  static BitArrayRange R_zimm_0 (19,15);
3426  etiss_uint64 zimm_0 = R_zimm_0.read(ba);
3427  zimm += zimm_0;
3428  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3429  partInit.getAffectedRegisters().add(reg_name[rd],64);
3430  partInit.getAffectedRegisters().add("instructionPointer",64);
3431  partInit.code() = std::string("//csrrci\n")+
3432  "etiss_uint32 temp = 0;\n"
3433  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3434  #if RISCV64_Pipeline1
3435  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3436  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3437  "etiss_uint32 num_stages = 4;\n"
3438  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3439  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3440  #endif
3441  #if RISCV64_Pipeline2
3442  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3443  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3444  "etiss_uint32 num_stages = 4;\n"
3445  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3446  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3447  #endif
3448 
3449  "etiss_uint64 res = 0;\n"
3450  "etiss_int64 mAddr = 0;\n"
3451  "etiss_int64 writeMask = 0;\n"
3452  "etiss_int64 writeMaskU = 0;\n"
3453  "etiss_int64 sAddr = 0;\n"
3454  "etiss_int64 writeMaskS = 0;\n"
3455  "etiss_int64 uAddr = 0;\n"
3456  "etiss_int64 writeMaskM = 0;\n"
3457 
3458 "res = ((RISCV64*)cpu)->CSR[" + toString(csr) + "];\n"
3459 #if RISCV64_DEBUG_CALL
3460 "printf(\"res = %#lx\\n\",res); \n"
3461 #endif
3462 "if(" + toString(rd) + " != 0)\n"
3463 "{\n"
3464  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
3465  #if RISCV64_DEBUG_CALL
3466  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
3467  #endif
3468 "}\n"
3469 
3470 "if(" + toString(zimm) + " != 0)\n"
3471 "{\n"
3472  "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
3473  "{\n"
3474  "uAddr = 0;\n"
3475  #if RISCV64_DEBUG_CALL
3476  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
3477  #endif
3478  "sAddr = 256;\n"
3479  #if RISCV64_DEBUG_CALL
3480  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
3481  #endif
3482  "mAddr = 768;\n"
3483  #if RISCV64_DEBUG_CALL
3484  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
3485  #endif
3486  "writeMaskM = -9223372036846388805;\n"
3487  #if RISCV64_DEBUG_CALL
3488  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
3489  #endif
3490  "writeMaskS = -9223372036853866189;\n"
3491  #if RISCV64_DEBUG_CALL
3492  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
3493  #endif
3494  "writeMaskU = -9223372036853866479;\n"
3495  #if RISCV64_DEBUG_CALL
3496  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
3497  #endif
3498  "}\n"
3499 
3500  "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
3501  "{\n"
3502  "uAddr = 68;\n"
3503  #if RISCV64_DEBUG_CALL
3504  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
3505  #endif
3506  "sAddr = 324;\n"
3507  #if RISCV64_DEBUG_CALL
3508  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
3509  #endif
3510  "mAddr = 836;\n"
3511  #if RISCV64_DEBUG_CALL
3512  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
3513  #endif
3514  "writeMaskM = 3003;\n"
3515  #if RISCV64_DEBUG_CALL
3516  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
3517  #endif
3518  "writeMaskS = 819;\n"
3519  #if RISCV64_DEBUG_CALL
3520  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
3521  #endif
3522  "writeMaskU = 273;\n"
3523  #if RISCV64_DEBUG_CALL
3524  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
3525  #endif
3526  "}\n"
3527 
3528  "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
3529  "{\n"
3530  "uAddr = 4;\n"
3531  #if RISCV64_DEBUG_CALL
3532  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
3533  #endif
3534  "sAddr = 260;\n"
3535  #if RISCV64_DEBUG_CALL
3536  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
3537  #endif
3538  "mAddr = 772;\n"
3539  #if RISCV64_DEBUG_CALL
3540  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
3541  #endif
3542  "writeMaskM = 3003;\n"
3543  #if RISCV64_DEBUG_CALL
3544  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
3545  #endif
3546  "writeMaskS = 819;\n"
3547  #if RISCV64_DEBUG_CALL
3548  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
3549  #endif
3550  "writeMaskU = 273;\n"
3551  #if RISCV64_DEBUG_CALL
3552  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
3553  #endif
3554  "}\n"
3555 
3556  "if(uAddr != sAddr)\n"
3557  "{\n"
3558  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
3559  "{\n"
3560  "writeMask = writeMaskM;\n"
3561  #if RISCV64_DEBUG_CALL
3562  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
3563  #endif
3564  "}\n"
3565 
3566  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
3567  "{\n"
3568  "writeMask = writeMaskS;\n"
3569  #if RISCV64_DEBUG_CALL
3570  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
3571  #endif
3572  "}\n"
3573 
3574  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
3575  "{\n"
3576  "writeMask = writeMaskU;\n"
3577  #if RISCV64_DEBUG_CALL
3578  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
3579  #endif
3580  "}\n"
3581 
3582  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((res & ~(etiss_uint64)" + toString(zimm) + ") & writeMask))&0xffffffffffffffff&0xffffffffffffffff;\n"
3583  #if RISCV64_DEBUG_CALL
3584  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
3585  #endif
3586  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
3587  #if RISCV64_DEBUG_CALL
3588  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
3589  #endif
3590  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
3591  #if RISCV64_DEBUG_CALL
3592  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
3593  #endif
3594  "}\n"
3595 
3596  "else\n"
3597  "{\n"
3598  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = (res & ~(etiss_uint64)" + toString(zimm) + ")&0xffffffffffffffff;\n"
3599  #if RISCV64_DEBUG_CALL
3600  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
3601  #endif
3602  "}\n"
3603 "}\n"
3604 
3605 
3606  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3607 
3608 ;
3609 return true;
3610 },
3611 0,
3612 nullptr
3613 );
3614 //-------------------------------------------------------------------------------------------------------------------
3615 static InstructionDefinition lw_rd_imm_rs1_(
3616  ISA32_RISCV64,
3617  "lw",
3618  (uint32_t)0x2003,
3619  (uint32_t) 0x707f,
3620  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3621  {
3622  etiss_uint64 rs1 = 0;
3623  static BitArrayRange R_rs1_0 (19,15);
3624  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3625  rs1 += rs1_0;
3626  etiss_uint64 rd = 0;
3627  static BitArrayRange R_rd_0 (11,7);
3628  etiss_uint64 rd_0 = R_rd_0.read(ba);
3629  rd += rd_0;
3630  etiss_int64 imm = 0;
3631  static BitArrayRange R_imm_0 (31,20);
3632  etiss_int64 imm_0 = R_imm_0.read(ba);
3633  imm += imm_0;
3634  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3635  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3636  partInit.getAffectedRegisters().add(reg_name[rd],64);
3637  partInit.getAffectedRegisters().add("instructionPointer",64);
3638  partInit.code() = std::string("//lw\n")+
3639  "etiss_uint32 exception = 0;\n"
3640  "etiss_uint32 temp = 0;\n"
3641  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3642  #if RISCV64_Pipeline1
3643  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3644  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3645  "etiss_uint32 num_stages = 4;\n"
3646  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3647  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3648  #endif
3649  #if RISCV64_Pipeline2
3650  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3651  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3652  "etiss_uint32 num_stages = 4;\n"
3653  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3654  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3655  #endif
3656 
3657  "etiss_int64 offs = 0;\n"
3658  "etiss_int64 imm_extended = 0;\n"
3659 
3660 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
3661 "{\n"
3662  "imm_extended = 0;\n"
3663  #if RISCV64_DEBUG_CALL
3664  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3665  #endif
3666 "}\n"
3667 
3668 "else\n"
3669 "{\n"
3670  "imm_extended = 4294967295;\n"
3671  #if RISCV64_DEBUG_CALL
3672  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3673  #endif
3674  "imm_extended = (imm_extended << 32);\n"
3675  #if RISCV64_DEBUG_CALL
3676  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3677  #endif
3678  "imm_extended = imm_extended + 4294963200;\n"
3679  #if RISCV64_DEBUG_CALL
3680  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3681  #endif
3682 "}\n"
3683 "imm_extended = imm_extended + " + toString(imm) + ";\n"
3684 #if RISCV64_DEBUG_CALL
3685 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3686 #endif
3687 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
3688 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
3689 "{\n"
3690  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
3691 "}\n"
3692 "offs = (etiss_int64)cast_0 + imm_extended;\n"
3693 #if RISCV64_DEBUG_CALL
3694 "printf(\"offs = %#lx\\n\",offs); \n"
3695 #endif
3696 "if(" + toString(rd) + " != 0)\n"
3697 "{\n"
3698  "etiss_uint32 MEM_offs;\n"
3699  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
3700  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
3701  "etiss_int32 cast_1 = MEM_offs; \n"
3702  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
3703  "{\n"
3704  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
3705  "}\n"
3706  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
3707  #if RISCV64_DEBUG_CALL
3708  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
3709  #endif
3710 "}\n"
3711 
3712 
3713  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3714 
3715  "return exception;\n"
3716 ;
3717 return true;
3718 },
3719 0,
3720 nullptr
3721 );
3722 //-------------------------------------------------------------------------------------------------------------------
3723 static InstructionDefinition sw_rs2_imm_rs1_(
3724  ISA32_RISCV64,
3725  "sw",
3726  (uint32_t)0x2023,
3727  (uint32_t) 0x707f,
3728  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3729  {
3730  etiss_uint64 rs2 = 0;
3731  static BitArrayRange R_rs2_0 (24,20);
3732  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
3733  rs2 += rs2_0;
3734  etiss_uint64 rs1 = 0;
3735  static BitArrayRange R_rs1_0 (19,15);
3736  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3737  rs1 += rs1_0;
3738  etiss_int64 imm = 0;
3739  static BitArrayRange R_imm_5 (31,25);
3740  etiss_int64 imm_5 = R_imm_5.read(ba);
3741  imm += imm_5<<5;
3742  static BitArrayRange R_imm_0 (11,7);
3743  etiss_int64 imm_0 = R_imm_0.read(ba);
3744  imm += imm_0;
3745  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3746  partInit.getRegisterDependencies().add(reg_name[rs2],64);
3747  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3748  partInit.getAffectedRegisters().add("instructionPointer",64);
3749  partInit.code() = std::string("//sw\n")+
3750  "etiss_uint32 exception = 0;\n"
3751  "etiss_uint32 temp = 0;\n"
3752  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3753  #if RISCV64_Pipeline1
3754  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3755  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3756  "etiss_uint32 num_stages = 4;\n"
3757  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3758  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3759  #endif
3760  #if RISCV64_Pipeline2
3761  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3762  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3763  "etiss_uint32 num_stages = 4;\n"
3764  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3765  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3766  #endif
3767 
3768  "etiss_int64 offs = 0;\n"
3769  "etiss_int64 imm_extended = 0;\n"
3770 
3771 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
3772 "{\n"
3773  "imm_extended = 0;\n"
3774  #if RISCV64_DEBUG_CALL
3775  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3776  #endif
3777 "}\n"
3778 
3779 "else\n"
3780 "{\n"
3781  "imm_extended = 4294967295;\n"
3782  #if RISCV64_DEBUG_CALL
3783  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3784  #endif
3785  "imm_extended = (imm_extended << 32);\n"
3786  #if RISCV64_DEBUG_CALL
3787  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3788  #endif
3789  "imm_extended = imm_extended + 4294963200;\n"
3790  #if RISCV64_DEBUG_CALL
3791  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3792  #endif
3793 "}\n"
3794 "imm_extended = imm_extended + " + toString(imm) + ";\n"
3795 #if RISCV64_DEBUG_CALL
3796 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3797 #endif
3798 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
3799 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
3800 "{\n"
3801  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
3802 "}\n"
3803 "offs = (etiss_int64)cast_0 + imm_extended;\n"
3804 #if RISCV64_DEBUG_CALL
3805 "printf(\"offs = %#lx\\n\",offs); \n"
3806 #endif
3807  "etiss_uint32 MEM_offs;\n"
3808 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
3809 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
3810 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
3811 #if RISCV64_DEBUG_CALL
3812 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
3813 #endif
3814 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
3815 "{\n"
3816  "((RISCV64*)cpu)->RES = 0;\n"
3817  #if RISCV64_DEBUG_CALL
3818  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
3819  #endif
3820 "}\n"
3821 
3822 
3823  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3824 
3825  "return exception;\n"
3826 ;
3827 return true;
3828 },
3829 0,
3830 nullptr
3831 );
3832 //-------------------------------------------------------------------------------------------------------------------
3833 static InstructionDefinition slti_rd_rs1_imm(
3834  ISA32_RISCV64,
3835  "slti",
3836  (uint32_t)0x2013,
3837  (uint32_t) 0x707f,
3838  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3839  {
3840  etiss_uint64 rs1 = 0;
3841  static BitArrayRange R_rs1_0 (19,15);
3842  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3843  rs1 += rs1_0;
3844  etiss_uint64 rd = 0;
3845  static BitArrayRange R_rd_0 (11,7);
3846  etiss_uint64 rd_0 = R_rd_0.read(ba);
3847  rd += rd_0;
3848  etiss_int64 imm = 0;
3849  static BitArrayRange R_imm_0 (31,20);
3850  etiss_int64 imm_0 = R_imm_0.read(ba);
3851  imm += imm_0;
3852  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3853  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3854  partInit.getAffectedRegisters().add(reg_name[rd],64);
3855  partInit.getAffectedRegisters().add("instructionPointer",64);
3856  partInit.code() = std::string("//slti\n")+
3857  "etiss_uint32 temp = 0;\n"
3858  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3859  #if RISCV64_Pipeline1
3860  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3861  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3862  "etiss_uint32 num_stages = 4;\n"
3863  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3864  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3865  #endif
3866  #if RISCV64_Pipeline2
3867  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3868  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3869  "etiss_uint32 num_stages = 4;\n"
3870  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3871  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3872  #endif
3873 
3874  "etiss_int64 imm_extended = 0;\n"
3875  "etiss_int8 choose1 = 0;\n"
3876 
3877 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
3878 "{\n"
3879  "imm_extended = 0;\n"
3880  #if RISCV64_DEBUG_CALL
3881  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3882  #endif
3883 "}\n"
3884 
3885 "else\n"
3886 "{\n"
3887  "imm_extended = 4294967295;\n"
3888  #if RISCV64_DEBUG_CALL
3889  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
3890  #endif
3891  "imm_extended = (imm_extended << 32);\n"
3892  #if RISCV64_DEBUG_CALL
3893  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3894  #endif
3895  "imm_extended = imm_extended + 4294963200;\n"
3896  #if RISCV64_DEBUG_CALL
3897  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3898  #endif
3899 "}\n"
3900 "imm_extended = imm_extended + " + toString(imm) + ";\n"
3901 #if RISCV64_DEBUG_CALL
3902 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
3903 #endif
3904 "if(" + toString(rd) + " != 0)\n"
3905 "{\n"
3906  "etiss_int64 cast_0 = imm_extended; \n"
3907  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
3908  "{\n"
3909  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
3910  "}\n"
3911  "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
3912  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
3913  "{\n"
3914  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
3915  "}\n"
3916  "if((etiss_int64)cast_1 < (etiss_int64)cast_0)\n"
3917  "{\n"
3918  "choose1 = 1;\n"
3919  #if RISCV64_DEBUG_CALL
3920  "printf(\"choose1 = %#x\\n\",choose1); \n"
3921  #endif
3922  "}\n"
3923 
3924  "else\n"
3925  "{\n"
3926  "choose1 = 0;\n"
3927  #if RISCV64_DEBUG_CALL
3928  "printf(\"choose1 = %#x\\n\",choose1); \n"
3929  #endif
3930  "}\n"
3931  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = choose1;\n"
3932  #if RISCV64_DEBUG_CALL
3933  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
3934  #endif
3935 "}\n"
3936 
3937 
3938  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
3939 
3940 ;
3941 return true;
3942 },
3943 0,
3944 nullptr
3945 );
3946 //-------------------------------------------------------------------------------------------------------------------
3947 static InstructionDefinition csrrs_rd_csr_rs1(
3948  ISA32_RISCV64,
3949  "csrrs",
3950  (uint32_t)0x2073,
3951  (uint32_t) 0x707f,
3952  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
3953  {
3954  etiss_uint64 rs1 = 0;
3955  static BitArrayRange R_rs1_0 (19,15);
3956  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
3957  rs1 += rs1_0;
3958  etiss_uint64 rd = 0;
3959  static BitArrayRange R_rd_0 (11,7);
3960  etiss_uint64 rd_0 = R_rd_0.read(ba);
3961  rd += rd_0;
3962  etiss_uint64 csr = 0;
3963  static BitArrayRange R_csr_0 (31,20);
3964  etiss_uint64 csr_0 = R_csr_0.read(ba);
3965  csr += csr_0;
3966  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
3967  partInit.getRegisterDependencies().add(reg_name[rs1],64);
3968  partInit.getAffectedRegisters().add(reg_name[rd],64);
3969  partInit.getAffectedRegisters().add("instructionPointer",64);
3970  partInit.code() = std::string("//csrrs\n")+
3971  "etiss_uint32 temp = 0;\n"
3972  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
3973  #if RISCV64_Pipeline1
3974  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3975  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3976  "etiss_uint32 num_stages = 4;\n"
3977  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3978  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3979  #endif
3980  #if RISCV64_Pipeline2
3981  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
3982  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
3983  "etiss_uint32 num_stages = 4;\n"
3984  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
3985  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
3986  #endif
3987 
3988  "etiss_uint64 xrs1 = 0;\n"
3989  "etiss_int64 mAddr = 0;\n"
3990  "etiss_int64 writeMask = 0;\n"
3991  "etiss_int64 writeMaskU = 0;\n"
3992  "etiss_int64 sAddr = 0;\n"
3993  "etiss_int64 writeMaskS = 0;\n"
3994  "etiss_int64 uAddr = 0;\n"
3995  "etiss_uint64 xrd = 0;\n"
3996  "etiss_int64 writeMaskM = 0;\n"
3997 
3998 "xrd = ((RISCV64*)cpu)->CSR[" + toString(csr) + "];\n"
3999 #if RISCV64_DEBUG_CALL
4000 "printf(\"xrd = %#lx\\n\",xrd); \n"
4001 #endif
4002 "xrs1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
4003 #if RISCV64_DEBUG_CALL
4004 "printf(\"xrs1 = %#lx\\n\",xrs1); \n"
4005 #endif
4006 "if(" + toString(rd) + " != 0)\n"
4007 "{\n"
4008  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = xrd;\n"
4009  #if RISCV64_DEBUG_CALL
4010  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
4011  #endif
4012 "}\n"
4013 
4014 "if(" + toString(rs1) + " != 0)\n"
4015 "{\n"
4016  "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
4017  "{\n"
4018  "uAddr = 0;\n"
4019  #if RISCV64_DEBUG_CALL
4020  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
4021  #endif
4022  "sAddr = 256;\n"
4023  #if RISCV64_DEBUG_CALL
4024  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
4025  #endif
4026  "mAddr = 768;\n"
4027  #if RISCV64_DEBUG_CALL
4028  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
4029  #endif
4030  "writeMaskM = -9223372036846388805;\n"
4031  #if RISCV64_DEBUG_CALL
4032  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
4033  #endif
4034  "writeMaskS = -9223372036853866189;\n"
4035  #if RISCV64_DEBUG_CALL
4036  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
4037  #endif
4038  "writeMaskU = -9223372036853866479;\n"
4039  #if RISCV64_DEBUG_CALL
4040  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
4041  #endif
4042  "}\n"
4043 
4044  "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
4045  "{\n"
4046  "uAddr = 68;\n"
4047  #if RISCV64_DEBUG_CALL
4048  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
4049  #endif
4050  "sAddr = 324;\n"
4051  #if RISCV64_DEBUG_CALL
4052  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
4053  #endif
4054  "mAddr = 836;\n"
4055  #if RISCV64_DEBUG_CALL
4056  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
4057  #endif
4058  "writeMaskM = 3003;\n"
4059  #if RISCV64_DEBUG_CALL
4060  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
4061  #endif
4062  "writeMaskS = 819;\n"
4063  #if RISCV64_DEBUG_CALL
4064  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
4065  #endif
4066  "writeMaskU = 273;\n"
4067  #if RISCV64_DEBUG_CALL
4068  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
4069  #endif
4070  "}\n"
4071 
4072  "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
4073  "{\n"
4074  "uAddr = 4;\n"
4075  #if RISCV64_DEBUG_CALL
4076  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
4077  #endif
4078  "sAddr = 260;\n"
4079  #if RISCV64_DEBUG_CALL
4080  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
4081  #endif
4082  "mAddr = 772;\n"
4083  #if RISCV64_DEBUG_CALL
4084  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
4085  #endif
4086  "writeMaskM = 3003;\n"
4087  #if RISCV64_DEBUG_CALL
4088  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
4089  #endif
4090  "writeMaskS = 819;\n"
4091  #if RISCV64_DEBUG_CALL
4092  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
4093  #endif
4094  "writeMaskU = 273;\n"
4095  #if RISCV64_DEBUG_CALL
4096  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
4097  #endif
4098  "}\n"
4099 
4100  "if(uAddr != sAddr)\n"
4101  "{\n"
4102  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
4103  "{\n"
4104  "writeMask = writeMaskM;\n"
4105  #if RISCV64_DEBUG_CALL
4106  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
4107  #endif
4108  "}\n"
4109 
4110  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
4111  "{\n"
4112  "writeMask = writeMaskS;\n"
4113  #if RISCV64_DEBUG_CALL
4114  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
4115  #endif
4116  "}\n"
4117 
4118  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
4119  "{\n"
4120  "writeMask = writeMaskU;\n"
4121  #if RISCV64_DEBUG_CALL
4122  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
4123  #endif
4124  "}\n"
4125 
4126  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((xrd | xrs1) & writeMask))&0xffffffffffffffff;\n"
4127  #if RISCV64_DEBUG_CALL
4128  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
4129  #endif
4130  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
4131  #if RISCV64_DEBUG_CALL
4132  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
4133  #endif
4134  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
4135  #if RISCV64_DEBUG_CALL
4136  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
4137  #endif
4138  "}\n"
4139 
4140  "else\n"
4141  "{\n"
4142  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = (xrd | xrs1);\n"
4143  #if RISCV64_DEBUG_CALL
4144  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
4145  #endif
4146  "}\n"
4147 "}\n"
4148 
4149 
4150  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4151 
4152 ;
4153 return true;
4154 },
4155 0,
4156 nullptr
4157 );
4158 //-------------------------------------------------------------------------------------------------------------------
4159 static InstructionDefinition flw_rd_imm_xrs1_(
4160  ISA32_RISCV64,
4161  "flw",
4162  (uint32_t)0x2007,
4163  (uint32_t) 0x707f,
4164  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4165  {
4166  etiss_uint64 rs1 = 0;
4167  static BitArrayRange R_rs1_0 (19,15);
4168  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4169  rs1 += rs1_0;
4170  etiss_uint64 rd = 0;
4171  static BitArrayRange R_rd_0 (11,7);
4172  etiss_uint64 rd_0 = R_rd_0.read(ba);
4173  rd += rd_0;
4174  etiss_int64 imm = 0;
4175  static BitArrayRange R_imm_0 (31,20);
4176  etiss_int64 imm_0 = R_imm_0.read(ba);
4177  imm += imm_0;
4178  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4179  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4180  partInit.getAffectedRegisters().add(reg_name[rd],64);
4181  partInit.getAffectedRegisters().add("instructionPointer",64);
4182  partInit.code() = std::string("//flw\n")+
4183  "etiss_uint32 exception = 0;\n"
4184  "etiss_uint32 temp = 0;\n"
4185  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4186  #if RISCV64_Pipeline1
4187  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4188  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4189  "etiss_uint32 num_stages = 4;\n"
4190  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4191  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4192  #endif
4193  #if RISCV64_Pipeline2
4194  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4195  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4196  "etiss_uint32 num_stages = 4;\n"
4197  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4198  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4199  #endif
4200 
4201  "etiss_int64 offs = 0;\n"
4202  "etiss_int64 imm_extended = 0;\n"
4203  "etiss_uint32 res = 0;\n"
4204  "etiss_int64 upper = 0;\n"
4205 
4206 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
4207 "{\n"
4208  "imm_extended = 0;\n"
4209  #if RISCV64_DEBUG_CALL
4210  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4211  #endif
4212 "}\n"
4213 
4214 "else\n"
4215 "{\n"
4216  "imm_extended = 4294967295;\n"
4217  #if RISCV64_DEBUG_CALL
4218  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4219  #endif
4220  "imm_extended = (imm_extended << 32);\n"
4221  #if RISCV64_DEBUG_CALL
4222  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4223  #endif
4224  "imm_extended = imm_extended + 4294963200;\n"
4225  #if RISCV64_DEBUG_CALL
4226  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4227  #endif
4228 "}\n"
4229 "imm_extended = imm_extended + " + toString(imm) + ";\n"
4230 #if RISCV64_DEBUG_CALL
4231 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4232 #endif
4233 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
4234 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
4235 "{\n"
4236  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
4237 "}\n"
4238 "offs = (etiss_int64)cast_0 + imm_extended;\n"
4239 #if RISCV64_DEBUG_CALL
4240 "printf(\"offs = %#lx\\n\",offs); \n"
4241 #endif
4242  "etiss_uint32 MEM_offs;\n"
4243 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
4244 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
4245 "res = MEM_offs;\n"
4246 #if RISCV64_DEBUG_CALL
4247 "printf(\"res = %#x\\n\",res); \n"
4248 #endif
4249 "if(64 == 32)\n"
4250 "{\n"
4251  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
4252  #if RISCV64_DEBUG_CALL
4253  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
4254  #endif
4255 "}\n"
4256 
4257 "else\n"
4258 "{\n"
4259  "upper = - 1;\n"
4260  #if RISCV64_DEBUG_CALL
4261  "printf(\"upper = %#lx\\n\",upper); \n"
4262  #endif
4263  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
4264  #if RISCV64_DEBUG_CALL
4265  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
4266  #endif
4267 "}\n"
4268 
4269  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4270 
4271  "return exception;\n"
4272 ;
4273 return true;
4274 },
4275 0,
4276 nullptr
4277 );
4278 //-------------------------------------------------------------------------------------------------------------------
4279 static InstructionDefinition fsw_rs2_imm_xrs1_(
4280  ISA32_RISCV64,
4281  "fsw",
4282  (uint32_t)0x2027,
4283  (uint32_t) 0x707f,
4284  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4285  {
4286  etiss_uint64 rs2 = 0;
4287  static BitArrayRange R_rs2_0 (24,20);
4288  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
4289  rs2 += rs2_0;
4290  etiss_uint64 rs1 = 0;
4291  static BitArrayRange R_rs1_0 (19,15);
4292  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4293  rs1 += rs1_0;
4294  etiss_int64 imm = 0;
4295  static BitArrayRange R_imm_5 (31,25);
4296  etiss_int64 imm_5 = R_imm_5.read(ba);
4297  imm += imm_5<<5;
4298  static BitArrayRange R_imm_0 (11,7);
4299  etiss_int64 imm_0 = R_imm_0.read(ba);
4300  imm += imm_0;
4301  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4302  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4303  partInit.getRegisterDependencies().add(reg_name[rs2],64);
4304  partInit.getAffectedRegisters().add("instructionPointer",64);
4305  partInit.code() = std::string("//fsw\n")+
4306  "etiss_uint32 exception = 0;\n"
4307  "etiss_uint32 temp = 0;\n"
4308  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4309  #if RISCV64_Pipeline1
4310  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4311  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4312  "etiss_uint32 num_stages = 4;\n"
4313  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4314  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4315  #endif
4316  #if RISCV64_Pipeline2
4317  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4318  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4319  "etiss_uint32 num_stages = 4;\n"
4320  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4321  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4322  #endif
4323 
4324  "etiss_int64 offs = 0;\n"
4325  "etiss_int64 imm_extended = 0;\n"
4326 
4327 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
4328 "{\n"
4329  "imm_extended = 0;\n"
4330  #if RISCV64_DEBUG_CALL
4331  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4332  #endif
4333 "}\n"
4334 
4335 "else\n"
4336 "{\n"
4337  "imm_extended = 4294967295;\n"
4338  #if RISCV64_DEBUG_CALL
4339  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4340  #endif
4341  "imm_extended = (imm_extended << 32);\n"
4342  #if RISCV64_DEBUG_CALL
4343  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4344  #endif
4345  "imm_extended = imm_extended + 4294963200;\n"
4346  #if RISCV64_DEBUG_CALL
4347  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4348  #endif
4349 "}\n"
4350 "imm_extended = imm_extended + " + toString(imm) + ";\n"
4351 #if RISCV64_DEBUG_CALL
4352 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4353 #endif
4354 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
4355 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
4356 "{\n"
4357  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
4358 "}\n"
4359 "offs = (etiss_int64)cast_0 + imm_extended;\n"
4360 #if RISCV64_DEBUG_CALL
4361 "printf(\"offs = %#lx\\n\",offs); \n"
4362 #endif
4363  "etiss_uint32 MEM_offs;\n"
4364 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
4365 "MEM_offs = (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffff);\n"
4366 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
4367 #if RISCV64_DEBUG_CALL
4368 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
4369 #endif
4370 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
4371 "{\n"
4372  "((RISCV64*)cpu)->RES = 0;\n"
4373  #if RISCV64_DEBUG_CALL
4374  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
4375  #endif
4376 "}\n"
4377 
4378 
4379  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4380 
4381  "return exception;\n"
4382 ;
4383 return true;
4384 },
4385 0,
4386 nullptr
4387 );
4388 //-------------------------------------------------------------------------------------------------------------------
4389 static InstructionDefinition sltiu_rd_rs1_imm(
4390  ISA32_RISCV64,
4391  "sltiu",
4392  (uint32_t)0x3013,
4393  (uint32_t) 0x707f,
4394  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4395  {
4396  etiss_uint64 rs1 = 0;
4397  static BitArrayRange R_rs1_0 (19,15);
4398  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4399  rs1 += rs1_0;
4400  etiss_uint64 rd = 0;
4401  static BitArrayRange R_rd_0 (11,7);
4402  etiss_uint64 rd_0 = R_rd_0.read(ba);
4403  rd += rd_0;
4404  etiss_int64 imm = 0;
4405  static BitArrayRange R_imm_0 (31,20);
4406  etiss_int64 imm_0 = R_imm_0.read(ba);
4407  imm += imm_0;
4408  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4409  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4410  partInit.getAffectedRegisters().add(reg_name[rd],64);
4411  partInit.getAffectedRegisters().add("instructionPointer",64);
4412  partInit.code() = std::string("//sltiu\n")+
4413  "etiss_uint32 temp = 0;\n"
4414  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4415  #if RISCV64_Pipeline1
4416  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4417  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4418  "etiss_uint32 num_stages = 4;\n"
4419  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4420  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4421  #endif
4422  #if RISCV64_Pipeline2
4423  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4424  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4425  "etiss_uint32 num_stages = 4;\n"
4426  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4427  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4428  #endif
4429 
4430  "etiss_int64 imm_extended = 0;\n"
4431  "etiss_int64 full_imm = 0;\n"
4432  "etiss_int8 choose1 = 0;\n"
4433 
4434 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
4435 "{\n"
4436  "imm_extended = 0;\n"
4437  #if RISCV64_DEBUG_CALL
4438  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4439  #endif
4440 "}\n"
4441 
4442 "else\n"
4443 "{\n"
4444  "imm_extended = 4294967295;\n"
4445  #if RISCV64_DEBUG_CALL
4446  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4447  #endif
4448  "imm_extended = (imm_extended << 32);\n"
4449  #if RISCV64_DEBUG_CALL
4450  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4451  #endif
4452  "imm_extended = imm_extended + 4294963200;\n"
4453  #if RISCV64_DEBUG_CALL
4454  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4455  #endif
4456 "}\n"
4457 "imm_extended = imm_extended + " + toString(imm) + ";\n"
4458 #if RISCV64_DEBUG_CALL
4459 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4460 #endif
4461 "etiss_int64 cast_0 = imm_extended; \n"
4462 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
4463 "{\n"
4464  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
4465 "}\n"
4466 "full_imm = (etiss_int64)cast_0;\n"
4467 #if RISCV64_DEBUG_CALL
4468 "printf(\"full_imm = %#lx\\n\",full_imm); \n"
4469 #endif
4470 "if(" + toString(rd) + " != 0)\n"
4471 "{\n"
4472  "if((etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs1) + "] < (etiss_uint64)full_imm)\n"
4473  "{\n"
4474  "choose1 = 1;\n"
4475  #if RISCV64_DEBUG_CALL
4476  "printf(\"choose1 = %#x\\n\",choose1); \n"
4477  #endif
4478  "}\n"
4479 
4480  "else\n"
4481  "{\n"
4482  "choose1 = 0;\n"
4483  #if RISCV64_DEBUG_CALL
4484  "printf(\"choose1 = %#x\\n\",choose1); \n"
4485  #endif
4486  "}\n"
4487  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = choose1;\n"
4488  #if RISCV64_DEBUG_CALL
4489  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
4490  #endif
4491 "}\n"
4492 
4493 
4494  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4495 
4496 ;
4497 return true;
4498 },
4499 0,
4500 nullptr
4501 );
4502 //-------------------------------------------------------------------------------------------------------------------
4503 static InstructionDefinition csrrc_rd_csr_rs1(
4504  ISA32_RISCV64,
4505  "csrrc",
4506  (uint32_t)0x3073,
4507  (uint32_t) 0x707f,
4508  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4509  {
4510  etiss_uint64 rs1 = 0;
4511  static BitArrayRange R_rs1_0 (19,15);
4512  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4513  rs1 += rs1_0;
4514  etiss_uint64 rd = 0;
4515  static BitArrayRange R_rd_0 (11,7);
4516  etiss_uint64 rd_0 = R_rd_0.read(ba);
4517  rd += rd_0;
4518  etiss_uint64 csr = 0;
4519  static BitArrayRange R_csr_0 (31,20);
4520  etiss_uint64 csr_0 = R_csr_0.read(ba);
4521  csr += csr_0;
4522  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4523  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4524  partInit.getAffectedRegisters().add(reg_name[rd],64);
4525  partInit.getAffectedRegisters().add("instructionPointer",64);
4526  partInit.code() = std::string("//csrrc\n")+
4527  "etiss_uint32 temp = 0;\n"
4528  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4529  #if RISCV64_Pipeline1
4530  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4531  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4532  "etiss_uint32 num_stages = 4;\n"
4533  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4534  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4535  #endif
4536  #if RISCV64_Pipeline2
4537  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4538  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4539  "etiss_uint32 num_stages = 4;\n"
4540  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4541  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4542  #endif
4543 
4544  "etiss_uint64 xrs1 = 0;\n"
4545  "etiss_int64 mAddr = 0;\n"
4546  "etiss_int64 writeMask = 0;\n"
4547  "etiss_int64 writeMaskU = 0;\n"
4548  "etiss_int64 sAddr = 0;\n"
4549  "etiss_int64 writeMaskS = 0;\n"
4550  "etiss_int64 uAddr = 0;\n"
4551  "etiss_uint64 xrd = 0;\n"
4552  "etiss_int64 writeMaskM = 0;\n"
4553 
4554 "xrd = ((RISCV64*)cpu)->CSR[" + toString(csr) + "];\n"
4555 #if RISCV64_DEBUG_CALL
4556 "printf(\"xrd = %#lx\\n\",xrd); \n"
4557 #endif
4558 "xrs1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
4559 #if RISCV64_DEBUG_CALL
4560 "printf(\"xrs1 = %#lx\\n\",xrs1); \n"
4561 #endif
4562 "if(" + toString(rd) + " != 0)\n"
4563 "{\n"
4564  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = xrd;\n"
4565  #if RISCV64_DEBUG_CALL
4566  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
4567  #endif
4568 "}\n"
4569 
4570 "if(" + toString(rs1) + " != 0)\n"
4571 "{\n"
4572  "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n"
4573  "{\n"
4574  "uAddr = 0;\n"
4575  #if RISCV64_DEBUG_CALL
4576  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
4577  #endif
4578  "sAddr = 256;\n"
4579  #if RISCV64_DEBUG_CALL
4580  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
4581  #endif
4582  "mAddr = 768;\n"
4583  #if RISCV64_DEBUG_CALL
4584  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
4585  #endif
4586  "writeMaskM = -9223372036846388805;\n"
4587  #if RISCV64_DEBUG_CALL
4588  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
4589  #endif
4590  "writeMaskS = -9223372036853866189;\n"
4591  #if RISCV64_DEBUG_CALL
4592  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
4593  #endif
4594  "writeMaskU = -9223372036853866479;\n"
4595  #if RISCV64_DEBUG_CALL
4596  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
4597  #endif
4598  "}\n"
4599 
4600  "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n"
4601  "{\n"
4602  "uAddr = 68;\n"
4603  #if RISCV64_DEBUG_CALL
4604  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
4605  #endif
4606  "sAddr = 324;\n"
4607  #if RISCV64_DEBUG_CALL
4608  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
4609  #endif
4610  "mAddr = 836;\n"
4611  #if RISCV64_DEBUG_CALL
4612  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
4613  #endif
4614  "writeMaskM = 3003;\n"
4615  #if RISCV64_DEBUG_CALL
4616  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
4617  #endif
4618  "writeMaskS = 819;\n"
4619  #if RISCV64_DEBUG_CALL
4620  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
4621  #endif
4622  "writeMaskU = 273;\n"
4623  #if RISCV64_DEBUG_CALL
4624  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
4625  #endif
4626  "}\n"
4627 
4628  "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n"
4629  "{\n"
4630  "uAddr = 4;\n"
4631  #if RISCV64_DEBUG_CALL
4632  "printf(\"uAddr = %#lx\\n\",uAddr); \n"
4633  #endif
4634  "sAddr = 260;\n"
4635  #if RISCV64_DEBUG_CALL
4636  "printf(\"sAddr = %#lx\\n\",sAddr); \n"
4637  #endif
4638  "mAddr = 772;\n"
4639  #if RISCV64_DEBUG_CALL
4640  "printf(\"mAddr = %#lx\\n\",mAddr); \n"
4641  #endif
4642  "writeMaskM = 3003;\n"
4643  #if RISCV64_DEBUG_CALL
4644  "printf(\"writeMaskM = %#lx\\n\",writeMaskM); \n"
4645  #endif
4646  "writeMaskS = 819;\n"
4647  #if RISCV64_DEBUG_CALL
4648  "printf(\"writeMaskS = %#lx\\n\",writeMaskS); \n"
4649  #endif
4650  "writeMaskU = 273;\n"
4651  #if RISCV64_DEBUG_CALL
4652  "printf(\"writeMaskU = %#lx\\n\",writeMaskU); \n"
4653  #endif
4654  "}\n"
4655 
4656  "if(uAddr != sAddr)\n"
4657  "{\n"
4658  "if(((RISCV64*)cpu)->CSR[3088] == 3)\n"
4659  "{\n"
4660  "writeMask = writeMaskM;\n"
4661  #if RISCV64_DEBUG_CALL
4662  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
4663  #endif
4664  "}\n"
4665 
4666  "if(((RISCV64*)cpu)->CSR[3088] == 1)\n"
4667  "{\n"
4668  "writeMask = writeMaskS;\n"
4669  #if RISCV64_DEBUG_CALL
4670  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
4671  #endif
4672  "}\n"
4673 
4674  "if(((RISCV64*)cpu)->CSR[3088] == 0)\n"
4675  "{\n"
4676  "writeMask = writeMaskU;\n"
4677  #if RISCV64_DEBUG_CALL
4678  "printf(\"writeMask = %#lx\\n\",writeMask); \n"
4679  #endif
4680  "}\n"
4681 
4682  "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((xrd & ~xrs1) & writeMask))&0xffffffffffffffff&0xffffffffffffffff;\n"
4683  #if RISCV64_DEBUG_CALL
4684  "printf(\"((RISCV64*)cpu)->CSR[uAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[uAddr]); \n"
4685  #endif
4686  "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
4687  #if RISCV64_DEBUG_CALL
4688  "printf(\"((RISCV64*)cpu)->CSR[sAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[sAddr]); \n"
4689  #endif
4690  "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n"
4691  #if RISCV64_DEBUG_CALL
4692  "printf(\"((RISCV64*)cpu)->CSR[mAddr] = %#lx\\n\",((RISCV64*)cpu)->CSR[mAddr]); \n"
4693  #endif
4694  "}\n"
4695 
4696  "else\n"
4697  "{\n"
4698  "((RISCV64*)cpu)->CSR[" + toString(csr) + "] = (xrd & ~xrs1)&0xffffffffffffffff;\n"
4699  #if RISCV64_DEBUG_CALL
4700  "printf(\"((RISCV64*)cpu)->CSR[" + toString(csr) + "] = %#lx\\n\",((RISCV64*)cpu)->CSR[" + toString(csr) + "]); \n"
4701  #endif
4702  "}\n"
4703 "}\n"
4704 
4705 
4706  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4707 
4708 ;
4709 return true;
4710 },
4711 0,
4712 nullptr
4713 );
4714 //-------------------------------------------------------------------------------------------------------------------
4715 static InstructionDefinition ld_rd_imm_rs1_(
4716  ISA32_RISCV64,
4717  "ld",
4718  (uint32_t)0x3003,
4719  (uint32_t) 0x707f,
4720  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4721  {
4722  etiss_uint64 rs1 = 0;
4723  static BitArrayRange R_rs1_0 (19,15);
4724  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4725  rs1 += rs1_0;
4726  etiss_uint64 rd = 0;
4727  static BitArrayRange R_rd_0 (11,7);
4728  etiss_uint64 rd_0 = R_rd_0.read(ba);
4729  rd += rd_0;
4730  etiss_int64 imm = 0;
4731  static BitArrayRange R_imm_0 (31,20);
4732  etiss_int64 imm_0 = R_imm_0.read(ba);
4733  imm += imm_0;
4734  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4735  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4736  partInit.getAffectedRegisters().add(reg_name[rd],64);
4737  partInit.getAffectedRegisters().add("instructionPointer",64);
4738  partInit.code() = std::string("//ld\n")+
4739  "etiss_uint32 exception = 0;\n"
4740  "etiss_uint32 temp = 0;\n"
4741  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4742  #if RISCV64_Pipeline1
4743  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4744  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4745  "etiss_uint32 num_stages = 4;\n"
4746  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4747  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4748  #endif
4749  #if RISCV64_Pipeline2
4750  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4751  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4752  "etiss_uint32 num_stages = 4;\n"
4753  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4754  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4755  #endif
4756 
4757  "etiss_int64 offs = 0;\n"
4758  "etiss_int64 imm_extended = 0;\n"
4759 
4760 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
4761 "{\n"
4762  "imm_extended = 0;\n"
4763  #if RISCV64_DEBUG_CALL
4764  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4765  #endif
4766 "}\n"
4767 
4768 "else\n"
4769 "{\n"
4770  "imm_extended = 4294967295;\n"
4771  #if RISCV64_DEBUG_CALL
4772  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4773  #endif
4774  "imm_extended = (imm_extended << 32);\n"
4775  #if RISCV64_DEBUG_CALL
4776  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4777  #endif
4778  "imm_extended = imm_extended + 4294963200;\n"
4779  #if RISCV64_DEBUG_CALL
4780  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4781  #endif
4782 "}\n"
4783 "imm_extended = imm_extended + " + toString(imm) + ";\n"
4784 #if RISCV64_DEBUG_CALL
4785 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4786 #endif
4787 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
4788 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
4789 "{\n"
4790  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
4791 "}\n"
4792 "offs = (etiss_int64)cast_0 + imm_extended;\n"
4793 #if RISCV64_DEBUG_CALL
4794 "printf(\"offs = %#lx\\n\",offs); \n"
4795 #endif
4796 "if(" + toString(rd) + " != 0)\n"
4797 "{\n"
4798  "etiss_uint64 MEM_offs;\n"
4799  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
4800  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
4801  "etiss_int64 cast_1 = MEM_offs; \n"
4802  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
4803  "{\n"
4804  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
4805  "}\n"
4806  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
4807  #if RISCV64_DEBUG_CALL
4808  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
4809  #endif
4810 "}\n"
4811 
4812 
4813  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4814 
4815  "return exception;\n"
4816 ;
4817 return true;
4818 },
4819 0,
4820 nullptr
4821 );
4822 //-------------------------------------------------------------------------------------------------------------------
4823 static InstructionDefinition sd_rs2_imm_rs1_(
4824  ISA32_RISCV64,
4825  "sd",
4826  (uint32_t)0x3023,
4827  (uint32_t) 0x707f,
4828  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4829  {
4830  etiss_uint64 rs2 = 0;
4831  static BitArrayRange R_rs2_0 (24,20);
4832  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
4833  rs2 += rs2_0;
4834  etiss_uint64 rs1 = 0;
4835  static BitArrayRange R_rs1_0 (19,15);
4836  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4837  rs1 += rs1_0;
4838  etiss_int64 imm = 0;
4839  static BitArrayRange R_imm_5 (31,25);
4840  etiss_int64 imm_5 = R_imm_5.read(ba);
4841  imm += imm_5<<5;
4842  static BitArrayRange R_imm_0 (11,7);
4843  etiss_int64 imm_0 = R_imm_0.read(ba);
4844  imm += imm_0;
4845  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4846  partInit.getRegisterDependencies().add(reg_name[rs2],64);
4847  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4848  partInit.getAffectedRegisters().add("instructionPointer",64);
4849  partInit.code() = std::string("//sd\n")+
4850  "etiss_uint32 exception = 0;\n"
4851  "etiss_uint32 temp = 0;\n"
4852  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4853  #if RISCV64_Pipeline1
4854  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4855  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4856  "etiss_uint32 num_stages = 4;\n"
4857  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4858  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4859  #endif
4860  #if RISCV64_Pipeline2
4861  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4862  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4863  "etiss_uint32 num_stages = 4;\n"
4864  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4865  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4866  #endif
4867 
4868  "etiss_int64 offs = 0;\n"
4869  "etiss_int64 imm_extended = 0;\n"
4870 
4871 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
4872 "{\n"
4873  "imm_extended = 0;\n"
4874  #if RISCV64_DEBUG_CALL
4875  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4876  #endif
4877 "}\n"
4878 
4879 "else\n"
4880 "{\n"
4881  "imm_extended = 4294967295;\n"
4882  #if RISCV64_DEBUG_CALL
4883  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4884  #endif
4885  "imm_extended = (imm_extended << 32);\n"
4886  #if RISCV64_DEBUG_CALL
4887  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4888  #endif
4889  "imm_extended = imm_extended + 4294963200;\n"
4890  #if RISCV64_DEBUG_CALL
4891  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4892  #endif
4893 "}\n"
4894 "imm_extended = imm_extended + " + toString(imm) + ";\n"
4895 #if RISCV64_DEBUG_CALL
4896 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4897 #endif
4898 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
4899 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
4900 "{\n"
4901  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
4902 "}\n"
4903 "offs = (etiss_int64)cast_0 + imm_extended;\n"
4904 #if RISCV64_DEBUG_CALL
4905 "printf(\"offs = %#lx\\n\",offs); \n"
4906 #endif
4907  "etiss_uint64 MEM_offs;\n"
4908 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
4909 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
4910 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
4911 #if RISCV64_DEBUG_CALL
4912 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
4913 #endif
4914 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
4915 "{\n"
4916  "((RISCV64*)cpu)->RES = 0;\n"
4917  #if RISCV64_DEBUG_CALL
4918  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
4919  #endif
4920 "}\n"
4921 
4922 
4923  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
4924 
4925  "return exception;\n"
4926 ;
4927 return true;
4928 },
4929 0,
4930 nullptr
4931 );
4932 //-------------------------------------------------------------------------------------------------------------------
4933 static InstructionDefinition fld_rd_imm_rs1_(
4934  ISA32_RISCV64,
4935  "fld",
4936  (uint32_t)0x3007,
4937  (uint32_t) 0x707f,
4938  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
4939  {
4940  etiss_uint64 rs1 = 0;
4941  static BitArrayRange R_rs1_0 (19,15);
4942  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
4943  rs1 += rs1_0;
4944  etiss_uint64 rd = 0;
4945  static BitArrayRange R_rd_0 (11,7);
4946  etiss_uint64 rd_0 = R_rd_0.read(ba);
4947  rd += rd_0;
4948  etiss_int64 imm = 0;
4949  static BitArrayRange R_imm_0 (31,20);
4950  etiss_int64 imm_0 = R_imm_0.read(ba);
4951  imm += imm_0;
4952  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
4953  partInit.getRegisterDependencies().add(reg_name[rs1],64);
4954  partInit.getAffectedRegisters().add(reg_name[rd],64);
4955  partInit.getAffectedRegisters().add("instructionPointer",64);
4956  partInit.code() = std::string("//fld\n")+
4957  "etiss_uint32 exception = 0;\n"
4958  "etiss_uint32 temp = 0;\n"
4959  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
4960  #if RISCV64_Pipeline1
4961  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4962  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4963  "etiss_uint32 num_stages = 4;\n"
4964  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4965  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4966  #endif
4967  #if RISCV64_Pipeline2
4968  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
4969  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
4970  "etiss_uint32 num_stages = 4;\n"
4971  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
4972  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
4973  #endif
4974 
4975  "etiss_int64 offs = 0;\n"
4976  "etiss_int64 imm_extended = 0;\n"
4977  "etiss_uint64 res = 0;\n"
4978  "etiss_int64 upper = 0;\n"
4979 
4980 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
4981 "{\n"
4982  "imm_extended = 0;\n"
4983  #if RISCV64_DEBUG_CALL
4984  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4985  #endif
4986 "}\n"
4987 
4988 "else\n"
4989 "{\n"
4990  "imm_extended = 4294967295;\n"
4991  #if RISCV64_DEBUG_CALL
4992  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
4993  #endif
4994  "imm_extended = (imm_extended << 32);\n"
4995  #if RISCV64_DEBUG_CALL
4996  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
4997  #endif
4998  "imm_extended = imm_extended + 4294963200;\n"
4999  #if RISCV64_DEBUG_CALL
5000  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
5001  #endif
5002 "}\n"
5003 "imm_extended = imm_extended + " + toString(imm) + ";\n"
5004 #if RISCV64_DEBUG_CALL
5005 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
5006 #endif
5007 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
5008 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
5009 "{\n"
5010  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
5011 "}\n"
5012 "offs = (etiss_int64)cast_0 + imm_extended;\n"
5013 #if RISCV64_DEBUG_CALL
5014 "printf(\"offs = %#lx\\n\",offs); \n"
5015 #endif
5016  "etiss_uint64 MEM_offs;\n"
5017 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
5018 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
5019 "res = MEM_offs;\n"
5020 #if RISCV64_DEBUG_CALL
5021 "printf(\"res = %#lx\\n\",res); \n"
5022 #endif
5023 "if(64 == 64)\n"
5024 "{\n"
5025  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
5026  #if RISCV64_DEBUG_CALL
5027  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5028  #endif
5029 "}\n"
5030 
5031 "else\n"
5032 "{\n"
5033  "upper = - 1;\n"
5034  #if RISCV64_DEBUG_CALL
5035  "printf(\"upper = %#lx\\n\",upper); \n"
5036  #endif
5037  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
5038  #if RISCV64_DEBUG_CALL
5039  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5040  #endif
5041 "}\n"
5042 
5043  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5044 
5045  "return exception;\n"
5046 ;
5047 return true;
5048 },
5049 0,
5050 nullptr
5051 );
5052 //-------------------------------------------------------------------------------------------------------------------
5053 static InstructionDefinition fsd_rs2_imm_rs1_(
5054  ISA32_RISCV64,
5055  "fsd",
5056  (uint32_t)0x3027,
5057  (uint32_t) 0x707f,
5058  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5059  {
5060  etiss_uint64 rs2 = 0;
5061  static BitArrayRange R_rs2_0 (24,20);
5062  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5063  rs2 += rs2_0;
5064  etiss_uint64 rs1 = 0;
5065  static BitArrayRange R_rs1_0 (19,15);
5066  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5067  rs1 += rs1_0;
5068  etiss_int64 imm = 0;
5069  static BitArrayRange R_imm_5 (31,25);
5070  etiss_int64 imm_5 = R_imm_5.read(ba);
5071  imm += imm_5<<5;
5072  static BitArrayRange R_imm_0 (11,7);
5073  etiss_int64 imm_0 = R_imm_0.read(ba);
5074  imm += imm_0;
5075  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5076  partInit.getRegisterDependencies().add(reg_name[rs1],64);
5077  partInit.getRegisterDependencies().add(reg_name[rs2],64);
5078  partInit.getAffectedRegisters().add("instructionPointer",64);
5079  partInit.code() = std::string("//fsd\n")+
5080  "etiss_uint32 exception = 0;\n"
5081  "etiss_uint32 temp = 0;\n"
5082  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5083  #if RISCV64_Pipeline1
5084  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5085  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5086  "etiss_uint32 num_stages = 4;\n"
5087  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5088  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5089  #endif
5090  #if RISCV64_Pipeline2
5091  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5092  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5093  "etiss_uint32 num_stages = 4;\n"
5094  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5095  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5096  #endif
5097 
5098  "etiss_int64 offs = 0;\n"
5099  "etiss_int64 imm_extended = 0;\n"
5100 
5101 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
5102 "{\n"
5103  "imm_extended = 0;\n"
5104  #if RISCV64_DEBUG_CALL
5105  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
5106  #endif
5107 "}\n"
5108 
5109 "else\n"
5110 "{\n"
5111  "imm_extended = 4294967295;\n"
5112  #if RISCV64_DEBUG_CALL
5113  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
5114  #endif
5115  "imm_extended = (imm_extended << 32);\n"
5116  #if RISCV64_DEBUG_CALL
5117  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
5118  #endif
5119  "imm_extended = imm_extended + 4294963200;\n"
5120  #if RISCV64_DEBUG_CALL
5121  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
5122  #endif
5123 "}\n"
5124 "imm_extended = imm_extended + " + toString(imm) + ";\n"
5125 #if RISCV64_DEBUG_CALL
5126 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
5127 #endif
5128 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
5129 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
5130 "{\n"
5131  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
5132 "}\n"
5133 "offs = (etiss_int64)cast_0 + imm_extended;\n"
5134 #if RISCV64_DEBUG_CALL
5135 "printf(\"offs = %#lx\\n\",offs); \n"
5136 #endif
5137  "etiss_uint64 MEM_offs;\n"
5138 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
5139 "MEM_offs = (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff);\n"
5140 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
5141 #if RISCV64_DEBUG_CALL
5142 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
5143 #endif
5144 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
5145 "{\n"
5146  "((RISCV64*)cpu)->RES = 0;\n"
5147  #if RISCV64_DEBUG_CALL
5148  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
5149  #endif
5150 "}\n"
5151 
5152 
5153  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5154 
5155  "return exception;\n"
5156 ;
5157 return true;
5158 },
5159 0,
5160 nullptr
5161 );
5162 //-------------------------------------------------------------------------------------------------------------------
5163 static InstructionDefinition fmadd_s_rd_frs1_frs2_frs3(
5164  ISA32_RISCV64,
5165  "fmadd.s",
5166  (uint32_t)0x43,
5167  (uint32_t) 0x600007f,
5168  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5169  {
5170  etiss_uint64 rs2 = 0;
5171  static BitArrayRange R_rs2_0 (24,20);
5172  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5173  rs2 += rs2_0;
5174  etiss_uint64 rs1 = 0;
5175  static BitArrayRange R_rs1_0 (19,15);
5176  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5177  rs1 += rs1_0;
5178  etiss_uint64 rd = 0;
5179  static BitArrayRange R_rd_0 (11,7);
5180  etiss_uint64 rd_0 = R_rd_0.read(ba);
5181  rd += rd_0;
5182  etiss_uint64 rs3 = 0;
5183  static BitArrayRange R_rs3_0 (31,27);
5184  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5185  rs3 += rs3_0;
5186  etiss_uint64 rm = 0;
5187  static BitArrayRange R_rm_0 (14,12);
5188  etiss_uint64 rm_0 = R_rm_0.read(ba);
5189  rm += rm_0;
5190  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5191  partInit.getAffectedRegisters().add(reg_name[rd],64);
5192  partInit.getAffectedRegisters().add("instructionPointer",64);
5193  partInit.code() = std::string("//fmadd.s\n")+
5194  "etiss_uint32 temp = 0;\n"
5195  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5196  #if RISCV64_Pipeline1
5197  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5198  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5199  "etiss_uint32 num_stages = 4;\n"
5200  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5201  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5202  #endif
5203  #if RISCV64_Pipeline2
5204  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5205  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5206  "etiss_uint32 num_stages = 4;\n"
5207  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5208  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5209  #endif
5210 
5211  "etiss_uint32 res = 0;\n"
5212  "etiss_int64 upper = 0;\n"
5213  "etiss_uint32 flags = 0;\n"
5214  "etiss_uint32 frs1 = 0;\n"
5215  "etiss_uint32 choose1 = 0;\n"
5216  "etiss_uint32 frs2 = 0;\n"
5217  "etiss_uint32 frs3 = 0;\n"
5218 
5219 "if(64 == 32)\n"
5220 "{\n"
5221  "if(" + toString(rm) + " < 7)\n"
5222  "{\n"
5223  "choose1 = (" + toString(rm) + " & 0xff);\n"
5224  #if RISCV64_DEBUG_CALL
5225  "printf(\"choose1 = %#x\\n\",choose1); \n"
5226  #endif
5227  "}\n"
5228 
5229  "else\n"
5230  "{\n"
5231  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5232  #if RISCV64_DEBUG_CALL
5233  "printf(\"choose1 = %#x\\n\",choose1); \n"
5234  #endif
5235  "}\n"
5236  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fmadd_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], ((RISCV64*)cpu)->F[" + toString(rs3) + "], (etiss_uint32)0, choose1);\n"
5237  #if RISCV64_DEBUG_CALL
5238  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5239  #endif
5240 "}\n"
5241 
5242 "else\n"
5243 "{\n"
5244  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
5245  #if RISCV64_DEBUG_CALL
5246  "printf(\"frs1 = %#x\\n\",frs1); \n"
5247  #endif
5248  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
5249  #if RISCV64_DEBUG_CALL
5250  "printf(\"frs2 = %#x\\n\",frs2); \n"
5251  #endif
5252  "frs3 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs3) + "]);\n"
5253  #if RISCV64_DEBUG_CALL
5254  "printf(\"frs3 = %#x\\n\",frs3); \n"
5255  #endif
5256  "if(" + toString(rm) + " < 7)\n"
5257  "{\n"
5258  "choose1 = (" + toString(rm) + " & 0xff);\n"
5259  #if RISCV64_DEBUG_CALL
5260  "printf(\"choose1 = %#x\\n\",choose1); \n"
5261  #endif
5262  "}\n"
5263 
5264  "else\n"
5265  "{\n"
5266  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5267  #if RISCV64_DEBUG_CALL
5268  "printf(\"choose1 = %#x\\n\",choose1); \n"
5269  #endif
5270  "}\n"
5271  "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)0, choose1);\n"
5272  #if RISCV64_DEBUG_CALL
5273  "printf(\"res = %#x\\n\",res); \n"
5274  #endif
5275  "upper = - 1;\n"
5276  #if RISCV64_DEBUG_CALL
5277  "printf(\"upper = %#lx\\n\",upper); \n"
5278  #endif
5279  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
5280  #if RISCV64_DEBUG_CALL
5281  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5282  #endif
5283 "}\n"
5284 "flags = fget_flags();\n"
5285 #if RISCV64_DEBUG_CALL
5286 "printf(\"flags = %#x\\n\",flags); \n"
5287 #endif
5288 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
5289 #if RISCV64_DEBUG_CALL
5290 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
5291 #endif
5292 
5293  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5294 
5295 ;
5296 return true;
5297 },
5298 0,
5299 nullptr
5300 );
5301 //-------------------------------------------------------------------------------------------------------------------
5302 static InstructionDefinition fmsub_s_rd_frs1_frs2_frs3(
5303  ISA32_RISCV64,
5304  "fmsub.s",
5305  (uint32_t)0x47,
5306  (uint32_t) 0x600007f,
5307  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5308  {
5309  etiss_uint64 rs2 = 0;
5310  static BitArrayRange R_rs2_0 (24,20);
5311  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5312  rs2 += rs2_0;
5313  etiss_uint64 rs1 = 0;
5314  static BitArrayRange R_rs1_0 (19,15);
5315  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5316  rs1 += rs1_0;
5317  etiss_uint64 rd = 0;
5318  static BitArrayRange R_rd_0 (11,7);
5319  etiss_uint64 rd_0 = R_rd_0.read(ba);
5320  rd += rd_0;
5321  etiss_uint64 rs3 = 0;
5322  static BitArrayRange R_rs3_0 (31,27);
5323  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5324  rs3 += rs3_0;
5325  etiss_uint64 rm = 0;
5326  static BitArrayRange R_rm_0 (14,12);
5327  etiss_uint64 rm_0 = R_rm_0.read(ba);
5328  rm += rm_0;
5329  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5330  partInit.getAffectedRegisters().add(reg_name[rd],64);
5331  partInit.getAffectedRegisters().add("instructionPointer",64);
5332  partInit.code() = std::string("//fmsub.s\n")+
5333  "etiss_uint32 temp = 0;\n"
5334  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5335  #if RISCV64_Pipeline1
5336  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5337  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5338  "etiss_uint32 num_stages = 4;\n"
5339  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5340  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5341  #endif
5342  #if RISCV64_Pipeline2
5343  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5344  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5345  "etiss_uint32 num_stages = 4;\n"
5346  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5347  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5348  #endif
5349 
5350  "etiss_uint32 res = 0;\n"
5351  "etiss_int64 upper = 0;\n"
5352  "etiss_uint32 flags = 0;\n"
5353  "etiss_uint32 frs1 = 0;\n"
5354  "etiss_uint32 choose1 = 0;\n"
5355  "etiss_uint32 frs2 = 0;\n"
5356  "etiss_uint32 frs3 = 0;\n"
5357 
5358 "if(64 == 32)\n"
5359 "{\n"
5360  "if(" + toString(rm) + " < 7)\n"
5361  "{\n"
5362  "choose1 = (" + toString(rm) + " & 0xff);\n"
5363  #if RISCV64_DEBUG_CALL
5364  "printf(\"choose1 = %#x\\n\",choose1); \n"
5365  #endif
5366  "}\n"
5367 
5368  "else\n"
5369  "{\n"
5370  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5371  #if RISCV64_DEBUG_CALL
5372  "printf(\"choose1 = %#x\\n\",choose1); \n"
5373  #endif
5374  "}\n"
5375  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fmadd_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], ((RISCV64*)cpu)->F[" + toString(rs3) + "], (etiss_uint32)1, choose1);\n"
5376  #if RISCV64_DEBUG_CALL
5377  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5378  #endif
5379 "}\n"
5380 
5381 "else\n"
5382 "{\n"
5383  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
5384  #if RISCV64_DEBUG_CALL
5385  "printf(\"frs1 = %#x\\n\",frs1); \n"
5386  #endif
5387  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
5388  #if RISCV64_DEBUG_CALL
5389  "printf(\"frs2 = %#x\\n\",frs2); \n"
5390  #endif
5391  "frs3 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs3) + "]);\n"
5392  #if RISCV64_DEBUG_CALL
5393  "printf(\"frs3 = %#x\\n\",frs3); \n"
5394  #endif
5395  "if(" + toString(rm) + " < 7)\n"
5396  "{\n"
5397  "choose1 = (" + toString(rm) + " & 0xff);\n"
5398  #if RISCV64_DEBUG_CALL
5399  "printf(\"choose1 = %#x\\n\",choose1); \n"
5400  #endif
5401  "}\n"
5402 
5403  "else\n"
5404  "{\n"
5405  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5406  #if RISCV64_DEBUG_CALL
5407  "printf(\"choose1 = %#x\\n\",choose1); \n"
5408  #endif
5409  "}\n"
5410  "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)1, choose1);\n"
5411  #if RISCV64_DEBUG_CALL
5412  "printf(\"res = %#x\\n\",res); \n"
5413  #endif
5414  "upper = - 1;\n"
5415  #if RISCV64_DEBUG_CALL
5416  "printf(\"upper = %#lx\\n\",upper); \n"
5417  #endif
5418  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
5419  #if RISCV64_DEBUG_CALL
5420  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5421  #endif
5422 "}\n"
5423 "flags = fget_flags();\n"
5424 #if RISCV64_DEBUG_CALL
5425 "printf(\"flags = %#x\\n\",flags); \n"
5426 #endif
5427 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
5428 #if RISCV64_DEBUG_CALL
5429 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
5430 #endif
5431 
5432  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5433 
5434 ;
5435 return true;
5436 },
5437 0,
5438 nullptr
5439 );
5440 //-------------------------------------------------------------------------------------------------------------------
5441 static InstructionDefinition fnmadd_s_rd_frs1_frs2_frs3(
5442  ISA32_RISCV64,
5443  "fnmadd.s",
5444  (uint32_t)0x4f,
5445  (uint32_t) 0x600007f,
5446  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5447  {
5448  etiss_uint64 rs2 = 0;
5449  static BitArrayRange R_rs2_0 (24,20);
5450  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5451  rs2 += rs2_0;
5452  etiss_uint64 rs1 = 0;
5453  static BitArrayRange R_rs1_0 (19,15);
5454  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5455  rs1 += rs1_0;
5456  etiss_uint64 rd = 0;
5457  static BitArrayRange R_rd_0 (11,7);
5458  etiss_uint64 rd_0 = R_rd_0.read(ba);
5459  rd += rd_0;
5460  etiss_uint64 rs3 = 0;
5461  static BitArrayRange R_rs3_0 (31,27);
5462  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5463  rs3 += rs3_0;
5464  etiss_uint64 rm = 0;
5465  static BitArrayRange R_rm_0 (14,12);
5466  etiss_uint64 rm_0 = R_rm_0.read(ba);
5467  rm += rm_0;
5468  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5469  partInit.getAffectedRegisters().add(reg_name[rd],64);
5470  partInit.getAffectedRegisters().add("instructionPointer",64);
5471  partInit.code() = std::string("//fnmadd.s\n")+
5472  "etiss_uint32 temp = 0;\n"
5473  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5474  #if RISCV64_Pipeline1
5475  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5476  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5477  "etiss_uint32 num_stages = 4;\n"
5478  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5479  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5480  #endif
5481  #if RISCV64_Pipeline2
5482  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5483  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5484  "etiss_uint32 num_stages = 4;\n"
5485  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5486  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5487  #endif
5488 
5489  "etiss_uint32 res = 0;\n"
5490  "etiss_int64 upper = 0;\n"
5491  "etiss_uint32 flags = 0;\n"
5492  "etiss_uint32 frs1 = 0;\n"
5493  "etiss_uint32 choose1 = 0;\n"
5494  "etiss_uint32 frs2 = 0;\n"
5495  "etiss_uint32 frs3 = 0;\n"
5496 
5497 "if(64 == 32)\n"
5498 "{\n"
5499  "if(" + toString(rm) + " < 7)\n"
5500  "{\n"
5501  "choose1 = (" + toString(rm) + " & 0xff);\n"
5502  #if RISCV64_DEBUG_CALL
5503  "printf(\"choose1 = %#x\\n\",choose1); \n"
5504  #endif
5505  "}\n"
5506 
5507  "else\n"
5508  "{\n"
5509  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5510  #if RISCV64_DEBUG_CALL
5511  "printf(\"choose1 = %#x\\n\",choose1); \n"
5512  #endif
5513  "}\n"
5514  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fmadd_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], ((RISCV64*)cpu)->F[" + toString(rs3) + "], (etiss_uint32)2, choose1);\n"
5515  #if RISCV64_DEBUG_CALL
5516  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5517  #endif
5518 "}\n"
5519 
5520 "else\n"
5521 "{\n"
5522  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
5523  #if RISCV64_DEBUG_CALL
5524  "printf(\"frs1 = %#x\\n\",frs1); \n"
5525  #endif
5526  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
5527  #if RISCV64_DEBUG_CALL
5528  "printf(\"frs2 = %#x\\n\",frs2); \n"
5529  #endif
5530  "frs3 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs3) + "]);\n"
5531  #if RISCV64_DEBUG_CALL
5532  "printf(\"frs3 = %#x\\n\",frs3); \n"
5533  #endif
5534  "if(" + toString(rm) + " < 7)\n"
5535  "{\n"
5536  "choose1 = (" + toString(rm) + " & 0xff);\n"
5537  #if RISCV64_DEBUG_CALL
5538  "printf(\"choose1 = %#x\\n\",choose1); \n"
5539  #endif
5540  "}\n"
5541 
5542  "else\n"
5543  "{\n"
5544  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5545  #if RISCV64_DEBUG_CALL
5546  "printf(\"choose1 = %#x\\n\",choose1); \n"
5547  #endif
5548  "}\n"
5549  "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)2, choose1);\n"
5550  #if RISCV64_DEBUG_CALL
5551  "printf(\"res = %#x\\n\",res); \n"
5552  #endif
5553  "upper = - 1;\n"
5554  #if RISCV64_DEBUG_CALL
5555  "printf(\"upper = %#lx\\n\",upper); \n"
5556  #endif
5557  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
5558  #if RISCV64_DEBUG_CALL
5559  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5560  #endif
5561 "}\n"
5562 "flags = fget_flags();\n"
5563 #if RISCV64_DEBUG_CALL
5564 "printf(\"flags = %#x\\n\",flags); \n"
5565 #endif
5566 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
5567 #if RISCV64_DEBUG_CALL
5568 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
5569 #endif
5570 
5571  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5572 
5573 ;
5574 return true;
5575 },
5576 0,
5577 nullptr
5578 );
5579 //-------------------------------------------------------------------------------------------------------------------
5580 static InstructionDefinition fnmsub_s_rd_frs1_frs2_frs3(
5581  ISA32_RISCV64,
5582  "fnmsub.s",
5583  (uint32_t)0x4b,
5584  (uint32_t) 0x600007f,
5585  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5586  {
5587  etiss_uint64 rs2 = 0;
5588  static BitArrayRange R_rs2_0 (24,20);
5589  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5590  rs2 += rs2_0;
5591  etiss_uint64 rs1 = 0;
5592  static BitArrayRange R_rs1_0 (19,15);
5593  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5594  rs1 += rs1_0;
5595  etiss_uint64 rd = 0;
5596  static BitArrayRange R_rd_0 (11,7);
5597  etiss_uint64 rd_0 = R_rd_0.read(ba);
5598  rd += rd_0;
5599  etiss_uint64 rs3 = 0;
5600  static BitArrayRange R_rs3_0 (31,27);
5601  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5602  rs3 += rs3_0;
5603  etiss_uint64 rm = 0;
5604  static BitArrayRange R_rm_0 (14,12);
5605  etiss_uint64 rm_0 = R_rm_0.read(ba);
5606  rm += rm_0;
5607  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5608  partInit.getAffectedRegisters().add(reg_name[rd],64);
5609  partInit.getAffectedRegisters().add("instructionPointer",64);
5610  partInit.code() = std::string("//fnmsub.s\n")+
5611  "etiss_uint32 temp = 0;\n"
5612  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5613  #if RISCV64_Pipeline1
5614  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5615  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5616  "etiss_uint32 num_stages = 4;\n"
5617  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5618  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5619  #endif
5620  #if RISCV64_Pipeline2
5621  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5622  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5623  "etiss_uint32 num_stages = 4;\n"
5624  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5625  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5626  #endif
5627 
5628  "etiss_uint32 res = 0;\n"
5629  "etiss_int64 upper = 0;\n"
5630  "etiss_uint32 flags = 0;\n"
5631  "etiss_uint32 frs1 = 0;\n"
5632  "etiss_uint32 choose1 = 0;\n"
5633  "etiss_uint32 frs2 = 0;\n"
5634  "etiss_uint32 frs3 = 0;\n"
5635 
5636 "if(64 == 32)\n"
5637 "{\n"
5638  "if(" + toString(rm) + " < 7)\n"
5639  "{\n"
5640  "choose1 = (" + toString(rm) + " & 0xff);\n"
5641  #if RISCV64_DEBUG_CALL
5642  "printf(\"choose1 = %#x\\n\",choose1); \n"
5643  #endif
5644  "}\n"
5645 
5646  "else\n"
5647  "{\n"
5648  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5649  #if RISCV64_DEBUG_CALL
5650  "printf(\"choose1 = %#x\\n\",choose1); \n"
5651  #endif
5652  "}\n"
5653  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fmadd_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], ((RISCV64*)cpu)->F[" + toString(rs3) + "], (etiss_uint32)3, choose1);\n"
5654  #if RISCV64_DEBUG_CALL
5655  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5656  #endif
5657 "}\n"
5658 
5659 "else\n"
5660 "{\n"
5661  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
5662  #if RISCV64_DEBUG_CALL
5663  "printf(\"frs1 = %#x\\n\",frs1); \n"
5664  #endif
5665  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
5666  #if RISCV64_DEBUG_CALL
5667  "printf(\"frs2 = %#x\\n\",frs2); \n"
5668  #endif
5669  "frs3 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs3) + "]);\n"
5670  #if RISCV64_DEBUG_CALL
5671  "printf(\"frs3 = %#x\\n\",frs3); \n"
5672  #endif
5673  "if(" + toString(rm) + " < 7)\n"
5674  "{\n"
5675  "choose1 = (" + toString(rm) + " & 0xff);\n"
5676  #if RISCV64_DEBUG_CALL
5677  "printf(\"choose1 = %#x\\n\",choose1); \n"
5678  #endif
5679  "}\n"
5680 
5681  "else\n"
5682  "{\n"
5683  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5684  #if RISCV64_DEBUG_CALL
5685  "printf(\"choose1 = %#x\\n\",choose1); \n"
5686  #endif
5687  "}\n"
5688  "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)3, choose1);\n"
5689  #if RISCV64_DEBUG_CALL
5690  "printf(\"res = %#x\\n\",res); \n"
5691  #endif
5692  "upper = - 1;\n"
5693  #if RISCV64_DEBUG_CALL
5694  "printf(\"upper = %#lx\\n\",upper); \n"
5695  #endif
5696  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
5697  #if RISCV64_DEBUG_CALL
5698  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5699  #endif
5700 "}\n"
5701 "flags = fget_flags();\n"
5702 #if RISCV64_DEBUG_CALL
5703 "printf(\"flags = %#x\\n\",flags); \n"
5704 #endif
5705 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
5706 #if RISCV64_DEBUG_CALL
5707 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
5708 #endif
5709 
5710  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5711 
5712 ;
5713 return true;
5714 },
5715 0,
5716 nullptr
5717 );
5718 //-------------------------------------------------------------------------------------------------------------------
5719 static InstructionDefinition fmadd_d_rd_frs1_frs2_frs3(
5720  ISA32_RISCV64,
5721  "fmadd.d",
5722  (uint32_t)0x2000043,
5723  (uint32_t) 0x600007f,
5724  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5725  {
5726  etiss_uint64 rs2 = 0;
5727  static BitArrayRange R_rs2_0 (24,20);
5728  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5729  rs2 += rs2_0;
5730  etiss_uint64 rs1 = 0;
5731  static BitArrayRange R_rs1_0 (19,15);
5732  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5733  rs1 += rs1_0;
5734  etiss_uint64 rd = 0;
5735  static BitArrayRange R_rd_0 (11,7);
5736  etiss_uint64 rd_0 = R_rd_0.read(ba);
5737  rd += rd_0;
5738  etiss_uint64 rs3 = 0;
5739  static BitArrayRange R_rs3_0 (31,27);
5740  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5741  rs3 += rs3_0;
5742  etiss_uint64 rm = 0;
5743  static BitArrayRange R_rm_0 (14,12);
5744  etiss_uint64 rm_0 = R_rm_0.read(ba);
5745  rm += rm_0;
5746  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5747  partInit.getAffectedRegisters().add(reg_name[rd],64);
5748  partInit.getAffectedRegisters().add("instructionPointer",64);
5749  partInit.code() = std::string("//fmadd.d\n")+
5750  "etiss_uint32 temp = 0;\n"
5751  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5752  #if RISCV64_Pipeline1
5753  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5754  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5755  "etiss_uint32 num_stages = 4;\n"
5756  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5757  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5758  #endif
5759  #if RISCV64_Pipeline2
5760  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5761  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5762  "etiss_uint32 num_stages = 4;\n"
5763  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5764  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5765  #endif
5766 
5767  "etiss_uint64 res = 0;\n"
5768  "etiss_int64 upper = 0;\n"
5769  "etiss_uint32 flags = 0;\n"
5770  "etiss_uint32 choose1 = 0;\n"
5771 
5772 "if(" + toString(rm) + " < 7)\n"
5773 "{\n"
5774  "choose1 = (" + toString(rm) + " & 0xff);\n"
5775  #if RISCV64_DEBUG_CALL
5776  "printf(\"choose1 = %#x\\n\",choose1); \n"
5777  #endif
5778 "}\n"
5779 
5780 "else\n"
5781 "{\n"
5782  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5783  #if RISCV64_DEBUG_CALL
5784  "printf(\"choose1 = %#x\\n\",choose1); \n"
5785  #endif
5786 "}\n"
5787 "res = fmadd_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs3) + "] & 0xffffffffffffffff), (etiss_uint64)0, choose1);\n"
5788 #if RISCV64_DEBUG_CALL
5789 "printf(\"res = %#lx\\n\",res); \n"
5790 #endif
5791 "if(64 == 64)\n"
5792 "{\n"
5793  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
5794  #if RISCV64_DEBUG_CALL
5795  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5796  #endif
5797 "}\n"
5798 
5799 "else\n"
5800 "{\n"
5801  "upper = - 1;\n"
5802  #if RISCV64_DEBUG_CALL
5803  "printf(\"upper = %#lx\\n\",upper); \n"
5804  #endif
5805  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
5806  #if RISCV64_DEBUG_CALL
5807  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5808  #endif
5809 "}\n"
5810 "flags = fget_flags();\n"
5811 #if RISCV64_DEBUG_CALL
5812 "printf(\"flags = %#x\\n\",flags); \n"
5813 #endif
5814 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
5815 #if RISCV64_DEBUG_CALL
5816 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
5817 #endif
5818 
5819  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5820 
5821 ;
5822 return true;
5823 },
5824 0,
5825 nullptr
5826 );
5827 //-------------------------------------------------------------------------------------------------------------------
5828 static InstructionDefinition fmsub_d_rd_frs1_frs2_frs3(
5829  ISA32_RISCV64,
5830  "fmsub.d",
5831  (uint32_t)0x2000047,
5832  (uint32_t) 0x600007f,
5833  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5834  {
5835  etiss_uint64 rs2 = 0;
5836  static BitArrayRange R_rs2_0 (24,20);
5837  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5838  rs2 += rs2_0;
5839  etiss_uint64 rs1 = 0;
5840  static BitArrayRange R_rs1_0 (19,15);
5841  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5842  rs1 += rs1_0;
5843  etiss_uint64 rd = 0;
5844  static BitArrayRange R_rd_0 (11,7);
5845  etiss_uint64 rd_0 = R_rd_0.read(ba);
5846  rd += rd_0;
5847  etiss_uint64 rs3 = 0;
5848  static BitArrayRange R_rs3_0 (31,27);
5849  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5850  rs3 += rs3_0;
5851  etiss_uint64 rm = 0;
5852  static BitArrayRange R_rm_0 (14,12);
5853  etiss_uint64 rm_0 = R_rm_0.read(ba);
5854  rm += rm_0;
5855  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5856  partInit.getAffectedRegisters().add(reg_name[rd],64);
5857  partInit.getAffectedRegisters().add("instructionPointer",64);
5858  partInit.code() = std::string("//fmsub.d\n")+
5859  "etiss_uint32 temp = 0;\n"
5860  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5861  #if RISCV64_Pipeline1
5862  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5863  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5864  "etiss_uint32 num_stages = 4;\n"
5865  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5866  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5867  #endif
5868  #if RISCV64_Pipeline2
5869  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5870  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5871  "etiss_uint32 num_stages = 4;\n"
5872  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5873  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5874  #endif
5875 
5876  "etiss_uint64 res = 0;\n"
5877  "etiss_int64 upper = 0;\n"
5878  "etiss_uint32 flags = 0;\n"
5879  "etiss_uint32 choose1 = 0;\n"
5880 
5881 "if(" + toString(rm) + " < 7)\n"
5882 "{\n"
5883  "choose1 = (" + toString(rm) + " & 0xff);\n"
5884  #if RISCV64_DEBUG_CALL
5885  "printf(\"choose1 = %#x\\n\",choose1); \n"
5886  #endif
5887 "}\n"
5888 
5889 "else\n"
5890 "{\n"
5891  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
5892  #if RISCV64_DEBUG_CALL
5893  "printf(\"choose1 = %#x\\n\",choose1); \n"
5894  #endif
5895 "}\n"
5896 "res = fmadd_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs3) + "] & 0xffffffffffffffff), (etiss_uint32)1, choose1);\n"
5897 #if RISCV64_DEBUG_CALL
5898 "printf(\"res = %#lx\\n\",res); \n"
5899 #endif
5900 "if(64 == 64)\n"
5901 "{\n"
5902  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
5903  #if RISCV64_DEBUG_CALL
5904  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5905  #endif
5906 "}\n"
5907 
5908 "else\n"
5909 "{\n"
5910  "upper = - 1;\n"
5911  #if RISCV64_DEBUG_CALL
5912  "printf(\"upper = %#lx\\n\",upper); \n"
5913  #endif
5914  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
5915  #if RISCV64_DEBUG_CALL
5916  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
5917  #endif
5918 "}\n"
5919 "flags = fget_flags();\n"
5920 #if RISCV64_DEBUG_CALL
5921 "printf(\"flags = %#x\\n\",flags); \n"
5922 #endif
5923 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
5924 #if RISCV64_DEBUG_CALL
5925 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
5926 #endif
5927 
5928  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
5929 
5930 ;
5931 return true;
5932 },
5933 0,
5934 nullptr
5935 );
5936 //-------------------------------------------------------------------------------------------------------------------
5937 static InstructionDefinition fnmadd_d_rd_frs1_frs2_frs3(
5938  ISA32_RISCV64,
5939  "fnmadd.d",
5940  (uint32_t)0x200004f,
5941  (uint32_t) 0x600007f,
5942  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
5943  {
5944  etiss_uint64 rs2 = 0;
5945  static BitArrayRange R_rs2_0 (24,20);
5946  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
5947  rs2 += rs2_0;
5948  etiss_uint64 rs1 = 0;
5949  static BitArrayRange R_rs1_0 (19,15);
5950  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
5951  rs1 += rs1_0;
5952  etiss_uint64 rd = 0;
5953  static BitArrayRange R_rd_0 (11,7);
5954  etiss_uint64 rd_0 = R_rd_0.read(ba);
5955  rd += rd_0;
5956  etiss_uint64 rs3 = 0;
5957  static BitArrayRange R_rs3_0 (31,27);
5958  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
5959  rs3 += rs3_0;
5960  etiss_uint64 rm = 0;
5961  static BitArrayRange R_rm_0 (14,12);
5962  etiss_uint64 rm_0 = R_rm_0.read(ba);
5963  rm += rm_0;
5964  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
5965  partInit.getAffectedRegisters().add(reg_name[rd],64);
5966  partInit.getAffectedRegisters().add("instructionPointer",64);
5967  partInit.code() = std::string("//fnmadd.d\n")+
5968  "etiss_uint32 temp = 0;\n"
5969  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
5970  #if RISCV64_Pipeline1
5971  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5972  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5973  "etiss_uint32 num_stages = 4;\n"
5974  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5975  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5976  #endif
5977  #if RISCV64_Pipeline2
5978  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
5979  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
5980  "etiss_uint32 num_stages = 4;\n"
5981  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
5982  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
5983  #endif
5984 
5985  "etiss_uint64 res = 0;\n"
5986  "etiss_int64 upper = 0;\n"
5987  "etiss_uint32 flags = 0;\n"
5988  "etiss_uint32 choose1 = 0;\n"
5989 
5990 "if(" + toString(rm) + " < 7)\n"
5991 "{\n"
5992  "choose1 = (" + toString(rm) + " & 0xff);\n"
5993  #if RISCV64_DEBUG_CALL
5994  "printf(\"choose1 = %#x\\n\",choose1); \n"
5995  #endif
5996 "}\n"
5997 
5998 "else\n"
5999 "{\n"
6000  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
6001  #if RISCV64_DEBUG_CALL
6002  "printf(\"choose1 = %#x\\n\",choose1); \n"
6003  #endif
6004 "}\n"
6005 "res = fmadd_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs3) + "] & 0xffffffffffffffff), (etiss_uint32)2, choose1);\n"
6006 #if RISCV64_DEBUG_CALL
6007 "printf(\"res = %#lx\\n\",res); \n"
6008 #endif
6009 "if(64 == 64)\n"
6010 "{\n"
6011  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
6012  #if RISCV64_DEBUG_CALL
6013  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
6014  #endif
6015 "}\n"
6016 
6017 "else\n"
6018 "{\n"
6019  "upper = - 1;\n"
6020  #if RISCV64_DEBUG_CALL
6021  "printf(\"upper = %#lx\\n\",upper); \n"
6022  #endif
6023  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
6024  #if RISCV64_DEBUG_CALL
6025  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
6026  #endif
6027 "}\n"
6028 "flags = fget_flags();\n"
6029 #if RISCV64_DEBUG_CALL
6030 "printf(\"flags = %#x\\n\",flags); \n"
6031 #endif
6032 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
6033 #if RISCV64_DEBUG_CALL
6034 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
6035 #endif
6036 
6037  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6038 
6039 ;
6040 return true;
6041 },
6042 0,
6043 nullptr
6044 );
6045 //-------------------------------------------------------------------------------------------------------------------
6046 static InstructionDefinition fnmsub_d_rd_frs1_frs2_frs3(
6047  ISA32_RISCV64,
6048  "fnmsub.d",
6049  (uint32_t)0x200004b,
6050  (uint32_t) 0x600007f,
6051  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6052  {
6053  etiss_uint64 rs2 = 0;
6054  static BitArrayRange R_rs2_0 (24,20);
6055  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6056  rs2 += rs2_0;
6057  etiss_uint64 rs1 = 0;
6058  static BitArrayRange R_rs1_0 (19,15);
6059  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6060  rs1 += rs1_0;
6061  etiss_uint64 rd = 0;
6062  static BitArrayRange R_rd_0 (11,7);
6063  etiss_uint64 rd_0 = R_rd_0.read(ba);
6064  rd += rd_0;
6065  etiss_uint64 rs3 = 0;
6066  static BitArrayRange R_rs3_0 (31,27);
6067  etiss_uint64 rs3_0 = R_rs3_0.read(ba);
6068  rs3 += rs3_0;
6069  etiss_uint64 rm = 0;
6070  static BitArrayRange R_rm_0 (14,12);
6071  etiss_uint64 rm_0 = R_rm_0.read(ba);
6072  rm += rm_0;
6073  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6074  partInit.getAffectedRegisters().add(reg_name[rd],64);
6075  partInit.getAffectedRegisters().add("instructionPointer",64);
6076  partInit.code() = std::string("//fnmsub.d\n")+
6077  "etiss_uint32 temp = 0;\n"
6078  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6079  #if RISCV64_Pipeline1
6080  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6081  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6082  "etiss_uint32 num_stages = 4;\n"
6083  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6084  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6085  #endif
6086  #if RISCV64_Pipeline2
6087  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6088  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6089  "etiss_uint32 num_stages = 4;\n"
6090  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6091  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6092  #endif
6093 
6094  "etiss_uint64 res = 0;\n"
6095  "etiss_int64 upper = 0;\n"
6096  "etiss_uint32 flags = 0;\n"
6097  "etiss_uint32 choose1 = 0;\n"
6098 
6099 "if(" + toString(rm) + " < 7)\n"
6100 "{\n"
6101  "choose1 = (" + toString(rm) + " & 0xff);\n"
6102  #if RISCV64_DEBUG_CALL
6103  "printf(\"choose1 = %#x\\n\",choose1); \n"
6104  #endif
6105 "}\n"
6106 
6107 "else\n"
6108 "{\n"
6109  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
6110  #if RISCV64_DEBUG_CALL
6111  "printf(\"choose1 = %#x\\n\",choose1); \n"
6112  #endif
6113 "}\n"
6114 "res = fmadd_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs3) + "] & 0xffffffffffffffff), (etiss_uint32)3, choose1);\n"
6115 #if RISCV64_DEBUG_CALL
6116 "printf(\"res = %#lx\\n\",res); \n"
6117 #endif
6118 "if(64 == 64)\n"
6119 "{\n"
6120  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
6121  #if RISCV64_DEBUG_CALL
6122  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
6123  #endif
6124 "}\n"
6125 
6126 "else\n"
6127 "{\n"
6128  "upper = - 1;\n"
6129  #if RISCV64_DEBUG_CALL
6130  "printf(\"upper = %#lx\\n\",upper); \n"
6131  #endif
6132  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
6133  #if RISCV64_DEBUG_CALL
6134  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
6135  #endif
6136 "}\n"
6137 "flags = fget_flags();\n"
6138 #if RISCV64_DEBUG_CALL
6139 "printf(\"flags = %#x\\n\",flags); \n"
6140 #endif
6141 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
6142 #if RISCV64_DEBUG_CALL
6143 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
6144 #endif
6145 
6146  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6147 
6148 ;
6149 return true;
6150 },
6151 0,
6152 nullptr
6153 );
6154 //-------------------------------------------------------------------------------------------------------------------
6155 static InstructionDefinition slli_rd_rs1_shamt(
6156  ISA32_RISCV64,
6157  "slli",
6158  (uint32_t)0x1013,
6159  (uint32_t) 0xfc00707f,
6160  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6161  {
6162  etiss_uint64 rs1 = 0;
6163  static BitArrayRange R_rs1_0 (19,15);
6164  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6165  rs1 += rs1_0;
6166  etiss_uint64 rd = 0;
6167  static BitArrayRange R_rd_0 (11,7);
6168  etiss_uint64 rd_0 = R_rd_0.read(ba);
6169  rd += rd_0;
6170  etiss_uint64 shamt = 0;
6171  static BitArrayRange R_shamt_0 (25,20);
6172  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
6173  shamt += shamt_0;
6174  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6175  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6176  partInit.getAffectedRegisters().add(reg_name[rd],64);
6177  partInit.getAffectedRegisters().add("instructionPointer",64);
6178  partInit.code() = std::string("//slli\n")+
6179  "etiss_uint32 temp = 0;\n"
6180  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6181  #if RISCV64_Pipeline1
6182  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6183  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6184  "etiss_uint32 num_stages = 4;\n"
6185  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6186  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6187  #endif
6188  #if RISCV64_Pipeline2
6189  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6190  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6191  "etiss_uint32 num_stages = 4;\n"
6192  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6193  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6194  #endif
6195 
6196 
6197 "if(" + toString(rd) + " != 0)\n"
6198 "{\n"
6199  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] << " + toString(shamt) + ");\n"
6200  #if RISCV64_DEBUG_CALL
6201  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6202  #endif
6203 "}\n"
6204 
6205 
6206  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6207 
6208 ;
6209 return true;
6210 },
6211 0,
6212 nullptr
6213 );
6214 //-------------------------------------------------------------------------------------------------------------------
6215 static InstructionDefinition srli_rd_rs1_shamt(
6216  ISA32_RISCV64,
6217  "srli",
6218  (uint32_t)0x5013,
6219  (uint32_t) 0xfc00707f,
6220  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6221  {
6222  etiss_uint64 rs1 = 0;
6223  static BitArrayRange R_rs1_0 (19,15);
6224  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6225  rs1 += rs1_0;
6226  etiss_uint64 rd = 0;
6227  static BitArrayRange R_rd_0 (11,7);
6228  etiss_uint64 rd_0 = R_rd_0.read(ba);
6229  rd += rd_0;
6230  etiss_uint64 shamt = 0;
6231  static BitArrayRange R_shamt_0 (25,20);
6232  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
6233  shamt += shamt_0;
6234  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6235  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6236  partInit.getAffectedRegisters().add(reg_name[rd],64);
6237  partInit.getAffectedRegisters().add("instructionPointer",64);
6238  partInit.code() = std::string("//srli\n")+
6239  "etiss_uint32 temp = 0;\n"
6240  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6241  #if RISCV64_Pipeline1
6242  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6243  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6244  "etiss_uint32 num_stages = 4;\n"
6245  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6246  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6247  #endif
6248  #if RISCV64_Pipeline2
6249  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6250  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6251  "etiss_uint32 num_stages = 4;\n"
6252  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6253  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6254  #endif
6255 
6256 
6257 "if(" + toString(rd) + " != 0)\n"
6258 "{\n"
6259  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] >> " + toString(shamt) + ");\n"
6260  #if RISCV64_DEBUG_CALL
6261  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6262  #endif
6263 "}\n"
6264 
6265 
6266  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6267 
6268 ;
6269 return true;
6270 },
6271 0,
6272 nullptr
6273 );
6274 //-------------------------------------------------------------------------------------------------------------------
6275 static InstructionDefinition srai_rd_rs1_shamt(
6276  ISA32_RISCV64,
6277  "srai",
6278  (uint32_t)0x40005013,
6279  (uint32_t) 0xfc00707f,
6280  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6281  {
6282  etiss_uint64 rs1 = 0;
6283  static BitArrayRange R_rs1_0 (19,15);
6284  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6285  rs1 += rs1_0;
6286  etiss_uint64 rd = 0;
6287  static BitArrayRange R_rd_0 (11,7);
6288  etiss_uint64 rd_0 = R_rd_0.read(ba);
6289  rd += rd_0;
6290  etiss_uint64 shamt = 0;
6291  static BitArrayRange R_shamt_0 (25,20);
6292  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
6293  shamt += shamt_0;
6294  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6295  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6296  partInit.getAffectedRegisters().add(reg_name[rd],64);
6297  partInit.getAffectedRegisters().add("instructionPointer",64);
6298  partInit.code() = std::string("//srai\n")+
6299  "etiss_uint32 temp = 0;\n"
6300  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6301  #if RISCV64_Pipeline1
6302  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6303  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6304  "etiss_uint32 num_stages = 4;\n"
6305  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6306  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6307  #endif
6308  #if RISCV64_Pipeline2
6309  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6310  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6311  "etiss_uint32 num_stages = 4;\n"
6312  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6313  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6314  #endif
6315 
6316 
6317 "if(" + toString(rd) + " != 0)\n"
6318 "{\n"
6319  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
6320  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
6321  "{\n"
6322  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
6323  "}\n"
6324  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_0 >> " + toString(shamt) + ");\n"
6325  #if RISCV64_DEBUG_CALL
6326  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6327  #endif
6328 "}\n"
6329 
6330 
6331  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6332 
6333 ;
6334 return true;
6335 },
6336 0,
6337 nullptr
6338 );
6339 //-------------------------------------------------------------------------------------------------------------------
6340 static InstructionDefinition add_rd_rs1_rs2(
6341  ISA32_RISCV64,
6342  "add",
6343  (uint32_t)0x33,
6344  (uint32_t) 0xfe00707f,
6345  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6346  {
6347  etiss_uint64 rs2 = 0;
6348  static BitArrayRange R_rs2_0 (24,20);
6349  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6350  rs2 += rs2_0;
6351  etiss_uint64 rs1 = 0;
6352  static BitArrayRange R_rs1_0 (19,15);
6353  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6354  rs1 += rs1_0;
6355  etiss_uint64 rd = 0;
6356  static BitArrayRange R_rd_0 (11,7);
6357  etiss_uint64 rd_0 = R_rd_0.read(ba);
6358  rd += rd_0;
6359  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6360  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6361  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6362  partInit.getAffectedRegisters().add(reg_name[rd],64);
6363  partInit.getAffectedRegisters().add("instructionPointer",64);
6364  partInit.code() = std::string("//add\n")+
6365  "etiss_uint32 temp = 0;\n"
6366  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6367  #if RISCV64_Pipeline1
6368  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6369  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6370  "etiss_uint32 num_stages = 4;\n"
6371  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6372  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6373  #endif
6374  #if RISCV64_Pipeline2
6375  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6376  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6377  "etiss_uint32 num_stages = 4;\n"
6378  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6379  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6380  #endif
6381 
6382 
6383 "if(" + toString(rd) + " != 0)\n"
6384 "{\n"
6385  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = *((RISCV64*)cpu)->X[" + toString(rs1) + "] + *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
6386  #if RISCV64_DEBUG_CALL
6387  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6388  #endif
6389 "}\n"
6390 
6391 
6392  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6393 
6394 ;
6395 return true;
6396 },
6397 0,
6398 nullptr
6399 );
6400 //-------------------------------------------------------------------------------------------------------------------
6401 static InstructionDefinition addw_(
6402  ISA32_RISCV64,
6403  "addw",
6404  (uint32_t)0x3b,
6405  (uint32_t) 0xfe00707f,
6406  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6407  {
6408  etiss_uint64 rs2 = 0;
6409  static BitArrayRange R_rs2_0 (24,20);
6410  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6411  rs2 += rs2_0;
6412  etiss_uint64 rs1 = 0;
6413  static BitArrayRange R_rs1_0 (19,15);
6414  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6415  rs1 += rs1_0;
6416  etiss_uint64 rd = 0;
6417  static BitArrayRange R_rd_0 (11,7);
6418  etiss_uint64 rd_0 = R_rd_0.read(ba);
6419  rd += rd_0;
6420  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6421  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6422  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6423  partInit.getAffectedRegisters().add(reg_name[rd],64);
6424  partInit.getAffectedRegisters().add("instructionPointer",64);
6425  partInit.code() = std::string("//addw\n")+
6426  "etiss_uint32 temp = 0;\n"
6427  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6428  #if RISCV64_Pipeline1
6429  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6430  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6431  "etiss_uint32 num_stages = 4;\n"
6432  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6433  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6434  #endif
6435  #if RISCV64_Pipeline2
6436  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6437  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6438  "etiss_uint32 num_stages = 4;\n"
6439  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6440  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6441  #endif
6442 
6443  "etiss_uint32 res = 0;\n"
6444 
6445 "if(" + toString(rd) + " != 0)\n"
6446 "{\n"
6447  "res = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) + (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff);\n"
6448  #if RISCV64_DEBUG_CALL
6449  "printf(\"res = %#x\\n\",res); \n"
6450  #endif
6451  "etiss_int32 cast_0 = res; \n"
6452  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
6453  "{\n"
6454  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
6455  "}\n"
6456  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
6457  #if RISCV64_DEBUG_CALL
6458  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6459  #endif
6460 "}\n"
6461 
6462 
6463  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6464 
6465 ;
6466 return true;
6467 },
6468 0,
6469 nullptr
6470 );
6471 //-------------------------------------------------------------------------------------------------------------------
6472 static InstructionDefinition sll_rd_rs1_rs2(
6473  ISA32_RISCV64,
6474  "sll",
6475  (uint32_t)0x1033,
6476  (uint32_t) 0xfe00707f,
6477  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6478  {
6479  etiss_uint64 rs2 = 0;
6480  static BitArrayRange R_rs2_0 (24,20);
6481  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6482  rs2 += rs2_0;
6483  etiss_uint64 rs1 = 0;
6484  static BitArrayRange R_rs1_0 (19,15);
6485  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6486  rs1 += rs1_0;
6487  etiss_uint64 rd = 0;
6488  static BitArrayRange R_rd_0 (11,7);
6489  etiss_uint64 rd_0 = R_rd_0.read(ba);
6490  rd += rd_0;
6491  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6492  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6493  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6494  partInit.getAffectedRegisters().add(reg_name[rd],64);
6495  partInit.getAffectedRegisters().add("instructionPointer",64);
6496  partInit.code() = std::string("//sll\n")+
6497  "etiss_uint32 temp = 0;\n"
6498  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6499  #if RISCV64_Pipeline1
6500  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6501  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {4, 5}, {6, 7}};\n"
6502  "etiss_uint32 num_stages = 4;\n"
6503  "etiss_uint32 num_resources[100] = {2, 1, 2, 2};\n"
6504  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6505  #endif
6506  #if RISCV64_Pipeline2
6507  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6508  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {4, 5}, {6, 7}};\n"
6509  "etiss_uint32 num_stages = 4;\n"
6510  "etiss_uint32 num_resources[100] = {2, 1, 2, 2};\n"
6511  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6512  #endif
6513 
6514 
6515 "if(" + toString(rd) + " != 0)\n"
6516 "{\n"
6517  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] << (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 64 - 1));\n"
6518  #if RISCV64_DEBUG_CALL
6519  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6520  #endif
6521 "}\n"
6522 
6523 
6524  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6525 
6526 ;
6527 return true;
6528 },
6529 0,
6530 nullptr
6531 );
6532 //-------------------------------------------------------------------------------------------------------------------
6533 static InstructionDefinition slliw_rd_rs1_shamt(
6534  ISA32_RISCV64,
6535  "slliw",
6536  (uint32_t)0x101b,
6537  (uint32_t) 0xfe00707f,
6538  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6539  {
6540  etiss_uint64 rs1 = 0;
6541  static BitArrayRange R_rs1_0 (19,15);
6542  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6543  rs1 += rs1_0;
6544  etiss_uint64 rd = 0;
6545  static BitArrayRange R_rd_0 (11,7);
6546  etiss_uint64 rd_0 = R_rd_0.read(ba);
6547  rd += rd_0;
6548  etiss_uint64 shamt = 0;
6549  static BitArrayRange R_shamt_0 (24,20);
6550  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
6551  shamt += shamt_0;
6552  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6553  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6554  partInit.getAffectedRegisters().add(reg_name[rd],64);
6555  partInit.getAffectedRegisters().add("instructionPointer",64);
6556  partInit.code() = std::string("//slliw\n")+
6557  "etiss_uint32 temp = 0;\n"
6558  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6559  #if RISCV64_Pipeline1
6560  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6561  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6562  "etiss_uint32 num_stages = 4;\n"
6563  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6564  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6565  #endif
6566  #if RISCV64_Pipeline2
6567  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6568  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6569  "etiss_uint32 num_stages = 4;\n"
6570  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6571  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6572  #endif
6573 
6574  "etiss_uint32 sh_val = 0;\n"
6575 
6576 "if(" + toString(rd) + " != 0)\n"
6577 "{\n"
6578  "sh_val = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) << " + toString(shamt) + ");\n"
6579  #if RISCV64_DEBUG_CALL
6580  "printf(\"sh_val = %#x\\n\",sh_val); \n"
6581  #endif
6582  "etiss_int32 cast_0 = sh_val; \n"
6583  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
6584  "{\n"
6585  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
6586  "}\n"
6587  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
6588  #if RISCV64_DEBUG_CALL
6589  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6590  #endif
6591 "}\n"
6592 
6593 
6594  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6595 
6596 ;
6597 return true;
6598 },
6599 0,
6600 nullptr
6601 );
6602 //-------------------------------------------------------------------------------------------------------------------
6603 static InstructionDefinition sllw_rd_rs1_rs2(
6604  ISA32_RISCV64,
6605  "sllw",
6606  (uint32_t)0x103b,
6607  (uint32_t) 0xfe00707f,
6608  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6609  {
6610  etiss_uint64 rs2 = 0;
6611  static BitArrayRange R_rs2_0 (24,20);
6612  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6613  rs2 += rs2_0;
6614  etiss_uint64 rs1 = 0;
6615  static BitArrayRange R_rs1_0 (19,15);
6616  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6617  rs1 += rs1_0;
6618  etiss_uint64 rd = 0;
6619  static BitArrayRange R_rd_0 (11,7);
6620  etiss_uint64 rd_0 = R_rd_0.read(ba);
6621  rd += rd_0;
6622  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6623  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6624  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6625  partInit.getAffectedRegisters().add(reg_name[rd],64);
6626  partInit.getAffectedRegisters().add("instructionPointer",64);
6627  partInit.code() = std::string("//sllw\n")+
6628  "etiss_uint32 temp = 0;\n"
6629  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6630  #if RISCV64_Pipeline1
6631  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6632  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6633  "etiss_uint32 num_stages = 4;\n"
6634  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6635  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6636  #endif
6637  #if RISCV64_Pipeline2
6638  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6639  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6640  "etiss_uint32 num_stages = 4;\n"
6641  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6642  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6643  #endif
6644 
6645  "etiss_uint32 sh_val = 0;\n"
6646  "etiss_uint32 count = 0;\n"
6647  "etiss_int32 mask = 0;\n"
6648 
6649 "if(" + toString(rd) + " != 0)\n"
6650 "{\n"
6651  "mask = 31;\n"
6652  #if RISCV64_DEBUG_CALL
6653  "printf(\"mask = %#x\\n\",mask); \n"
6654  #endif
6655  "count = ((*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff) & mask);\n"
6656  #if RISCV64_DEBUG_CALL
6657  "printf(\"count = %#x\\n\",count); \n"
6658  #endif
6659  "sh_val = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) << count);\n"
6660  #if RISCV64_DEBUG_CALL
6661  "printf(\"sh_val = %#x\\n\",sh_val); \n"
6662  #endif
6663  "etiss_int32 cast_0 = sh_val; \n"
6664  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
6665  "{\n"
6666  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
6667  "}\n"
6668  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
6669  #if RISCV64_DEBUG_CALL
6670  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6671  #endif
6672 "}\n"
6673 
6674 
6675  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6676 
6677 ;
6678 return true;
6679 },
6680 0,
6681 nullptr
6682 );
6683 //-------------------------------------------------------------------------------------------------------------------
6684 static InstructionDefinition slt_rd_rs1_rs2(
6685  ISA32_RISCV64,
6686  "slt",
6687  (uint32_t)0x2033,
6688  (uint32_t) 0xfe00707f,
6689  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6690  {
6691  etiss_uint64 rs2 = 0;
6692  static BitArrayRange R_rs2_0 (24,20);
6693  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6694  rs2 += rs2_0;
6695  etiss_uint64 rs1 = 0;
6696  static BitArrayRange R_rs1_0 (19,15);
6697  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6698  rs1 += rs1_0;
6699  etiss_uint64 rd = 0;
6700  static BitArrayRange R_rd_0 (11,7);
6701  etiss_uint64 rd_0 = R_rd_0.read(ba);
6702  rd += rd_0;
6703  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6704  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6705  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6706  partInit.getAffectedRegisters().add(reg_name[rd],64);
6707  partInit.getAffectedRegisters().add("instructionPointer",64);
6708  partInit.code() = std::string("//slt\n")+
6709  "etiss_uint32 temp = 0;\n"
6710  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6711  #if RISCV64_Pipeline1
6712  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6713  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6714  "etiss_uint32 num_stages = 4;\n"
6715  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6716  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6717  #endif
6718  #if RISCV64_Pipeline2
6719  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6720  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6721  "etiss_uint32 num_stages = 4;\n"
6722  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6723  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6724  #endif
6725 
6726  "etiss_int8 choose1 = 0;\n"
6727 
6728 "if(" + toString(rd) + " != 0)\n"
6729 "{\n"
6730  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
6731  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
6732  "{\n"
6733  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
6734  "}\n"
6735  "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
6736  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
6737  "{\n"
6738  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
6739  "}\n"
6740  "if((etiss_int64)cast_1 < (etiss_int64)cast_0)\n"
6741  "{\n"
6742  "choose1 = 1;\n"
6743  #if RISCV64_DEBUG_CALL
6744  "printf(\"choose1 = %#x\\n\",choose1); \n"
6745  #endif
6746  "}\n"
6747 
6748  "else\n"
6749  "{\n"
6750  "choose1 = 0;\n"
6751  #if RISCV64_DEBUG_CALL
6752  "printf(\"choose1 = %#x\\n\",choose1); \n"
6753  #endif
6754  "}\n"
6755  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = choose1;\n"
6756  #if RISCV64_DEBUG_CALL
6757  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6758  #endif
6759 "}\n"
6760 
6761 
6762  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6763 
6764 ;
6765 return true;
6766 },
6767 0,
6768 nullptr
6769 );
6770 //-------------------------------------------------------------------------------------------------------------------
6771 static InstructionDefinition sltu_rd_rs1_rs2(
6772  ISA32_RISCV64,
6773  "sltu",
6774  (uint32_t)0x3033,
6775  (uint32_t) 0xfe00707f,
6776  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6777  {
6778  etiss_uint64 rs2 = 0;
6779  static BitArrayRange R_rs2_0 (24,20);
6780  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6781  rs2 += rs2_0;
6782  etiss_uint64 rs1 = 0;
6783  static BitArrayRange R_rs1_0 (19,15);
6784  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6785  rs1 += rs1_0;
6786  etiss_uint64 rd = 0;
6787  static BitArrayRange R_rd_0 (11,7);
6788  etiss_uint64 rd_0 = R_rd_0.read(ba);
6789  rd += rd_0;
6790  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6791  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6792  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6793  partInit.getAffectedRegisters().add(reg_name[rd],64);
6794  partInit.getAffectedRegisters().add("instructionPointer",64);
6795  partInit.code() = std::string("//sltu\n")+
6796  "etiss_uint32 temp = 0;\n"
6797  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6798  #if RISCV64_Pipeline1
6799  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6800  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6801  "etiss_uint32 num_stages = 4;\n"
6802  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6803  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6804  #endif
6805  #if RISCV64_Pipeline2
6806  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6807  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6808  "etiss_uint32 num_stages = 4;\n"
6809  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6810  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6811  #endif
6812 
6813  "etiss_int8 choose1 = 0;\n"
6814 
6815 "if(" + toString(rd) + " != 0)\n"
6816 "{\n"
6817  "if((etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs1) + "] < (etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
6818  "{\n"
6819  "choose1 = 1;\n"
6820  #if RISCV64_DEBUG_CALL
6821  "printf(\"choose1 = %#x\\n\",choose1); \n"
6822  #endif
6823  "}\n"
6824 
6825  "else\n"
6826  "{\n"
6827  "choose1 = 0;\n"
6828  #if RISCV64_DEBUG_CALL
6829  "printf(\"choose1 = %#x\\n\",choose1); \n"
6830  #endif
6831  "}\n"
6832  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = choose1;\n"
6833  #if RISCV64_DEBUG_CALL
6834  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6835  #endif
6836 "}\n"
6837 
6838 
6839  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6840 
6841 ;
6842 return true;
6843 },
6844 0,
6845 nullptr
6846 );
6847 //-------------------------------------------------------------------------------------------------------------------
6848 static InstructionDefinition xor_rd_rs1_rs2(
6849  ISA32_RISCV64,
6850  "xor",
6851  (uint32_t)0x4033,
6852  (uint32_t) 0xfe00707f,
6853  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6854  {
6855  etiss_uint64 rs2 = 0;
6856  static BitArrayRange R_rs2_0 (24,20);
6857  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6858  rs2 += rs2_0;
6859  etiss_uint64 rs1 = 0;
6860  static BitArrayRange R_rs1_0 (19,15);
6861  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6862  rs1 += rs1_0;
6863  etiss_uint64 rd = 0;
6864  static BitArrayRange R_rd_0 (11,7);
6865  etiss_uint64 rd_0 = R_rd_0.read(ba);
6866  rd += rd_0;
6867  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6868  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6869  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6870  partInit.getAffectedRegisters().add(reg_name[rd],64);
6871  partInit.getAffectedRegisters().add("instructionPointer",64);
6872  partInit.code() = std::string("//xor\n")+
6873  "etiss_uint32 temp = 0;\n"
6874  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6875  #if RISCV64_Pipeline1
6876  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6877  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6878  "etiss_uint32 num_stages = 4;\n"
6879  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6880  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6881  #endif
6882  #if RISCV64_Pipeline2
6883  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6884  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6885  "etiss_uint32 num_stages = 4;\n"
6886  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6887  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6888  #endif
6889 
6890 
6891 "if(" + toString(rd) + " != 0)\n"
6892 "{\n"
6893  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] ^ *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
6894  #if RISCV64_DEBUG_CALL
6895  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6896  #endif
6897 "}\n"
6898 
6899 
6900  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6901 
6902 ;
6903 return true;
6904 },
6905 0,
6906 nullptr
6907 );
6908 //-------------------------------------------------------------------------------------------------------------------
6909 static InstructionDefinition srl_rd_rs1_rs2(
6910  ISA32_RISCV64,
6911  "srl",
6912  (uint32_t)0x5033,
6913  (uint32_t) 0xfe00707f,
6914  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6915  {
6916  etiss_uint64 rs2 = 0;
6917  static BitArrayRange R_rs2_0 (24,20);
6918  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
6919  rs2 += rs2_0;
6920  etiss_uint64 rs1 = 0;
6921  static BitArrayRange R_rs1_0 (19,15);
6922  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6923  rs1 += rs1_0;
6924  etiss_uint64 rd = 0;
6925  static BitArrayRange R_rd_0 (11,7);
6926  etiss_uint64 rd_0 = R_rd_0.read(ba);
6927  rd += rd_0;
6928  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6929  partInit.getRegisterDependencies().add(reg_name[rs2],64);
6930  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6931  partInit.getAffectedRegisters().add(reg_name[rd],64);
6932  partInit.getAffectedRegisters().add("instructionPointer",64);
6933  partInit.code() = std::string("//srl\n")+
6934  "etiss_uint32 temp = 0;\n"
6935  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6936  #if RISCV64_Pipeline1
6937  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6938  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6939  "etiss_uint32 num_stages = 4;\n"
6940  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6941  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6942  #endif
6943  #if RISCV64_Pipeline2
6944  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6945  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6946  "etiss_uint32 num_stages = 4;\n"
6947  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
6948  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
6949  #endif
6950 
6951 
6952 "if(" + toString(rd) + " != 0)\n"
6953 "{\n"
6954  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] >> (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 64 - 1));\n"
6955  #if RISCV64_DEBUG_CALL
6956  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
6957  #endif
6958 "}\n"
6959 
6960 
6961  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
6962 
6963 ;
6964 return true;
6965 },
6966 0,
6967 nullptr
6968 );
6969 //-------------------------------------------------------------------------------------------------------------------
6970 static InstructionDefinition srliw_rd_rs1_shamt(
6971  ISA32_RISCV64,
6972  "srliw",
6973  (uint32_t)0x501b,
6974  (uint32_t) 0xfe00707f,
6975  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
6976  {
6977  etiss_uint64 rs1 = 0;
6978  static BitArrayRange R_rs1_0 (19,15);
6979  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
6980  rs1 += rs1_0;
6981  etiss_uint64 rd = 0;
6982  static BitArrayRange R_rd_0 (11,7);
6983  etiss_uint64 rd_0 = R_rd_0.read(ba);
6984  rd += rd_0;
6985  etiss_uint64 shamt = 0;
6986  static BitArrayRange R_shamt_0 (24,20);
6987  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
6988  shamt += shamt_0;
6989  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
6990  partInit.getRegisterDependencies().add(reg_name[rs1],64);
6991  partInit.getAffectedRegisters().add(reg_name[rd],64);
6992  partInit.getAffectedRegisters().add("instructionPointer",64);
6993  partInit.code() = std::string("//srliw\n")+
6994  "etiss_uint32 temp = 0;\n"
6995  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
6996  #if RISCV64_Pipeline1
6997  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
6998  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
6999  "etiss_uint32 num_stages = 4;\n"
7000  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7001  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7002  #endif
7003  #if RISCV64_Pipeline2
7004  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7005  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7006  "etiss_uint32 num_stages = 4;\n"
7007  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7008  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7009  #endif
7010 
7011  "etiss_uint32 sh_val = 0;\n"
7012 
7013 "if(" + toString(rd) + " != 0)\n"
7014 "{\n"
7015  "sh_val = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) >> " + toString(shamt) + ");\n"
7016  #if RISCV64_DEBUG_CALL
7017  "printf(\"sh_val = %#x\\n\",sh_val); \n"
7018  #endif
7019  "etiss_int32 cast_0 = sh_val; \n"
7020  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
7021  "{\n"
7022  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
7023  "}\n"
7024  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
7025  #if RISCV64_DEBUG_CALL
7026  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7027  #endif
7028 "}\n"
7029 
7030 
7031  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7032 
7033 ;
7034 return true;
7035 },
7036 0,
7037 nullptr
7038 );
7039 //-------------------------------------------------------------------------------------------------------------------
7040 static InstructionDefinition srlw_rd_rs1_rs2(
7041  ISA32_RISCV64,
7042  "srlw",
7043  (uint32_t)0x503b,
7044  (uint32_t) 0xfe00707f,
7045  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7046  {
7047  etiss_uint64 rs2 = 0;
7048  static BitArrayRange R_rs2_0 (24,20);
7049  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7050  rs2 += rs2_0;
7051  etiss_uint64 rs1 = 0;
7052  static BitArrayRange R_rs1_0 (19,15);
7053  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7054  rs1 += rs1_0;
7055  etiss_uint64 rd = 0;
7056  static BitArrayRange R_rd_0 (11,7);
7057  etiss_uint64 rd_0 = R_rd_0.read(ba);
7058  rd += rd_0;
7059  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7060  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7061  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7062  partInit.getAffectedRegisters().add(reg_name[rd],64);
7063  partInit.getAffectedRegisters().add("instructionPointer",64);
7064  partInit.code() = std::string("//srlw\n")+
7065  "etiss_uint32 temp = 0;\n"
7066  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7067  #if RISCV64_Pipeline1
7068  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7069  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7070  "etiss_uint32 num_stages = 4;\n"
7071  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7072  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7073  #endif
7074  #if RISCV64_Pipeline2
7075  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7076  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7077  "etiss_uint32 num_stages = 4;\n"
7078  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7079  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7080  #endif
7081 
7082  "etiss_uint32 sh_val = 0;\n"
7083  "etiss_uint32 count = 0;\n"
7084  "etiss_int32 mask = 0;\n"
7085 
7086 "if(" + toString(rd) + " != 0)\n"
7087 "{\n"
7088  "mask = 31;\n"
7089  #if RISCV64_DEBUG_CALL
7090  "printf(\"mask = %#x\\n\",mask); \n"
7091  #endif
7092  "count = ((*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff) & mask);\n"
7093  #if RISCV64_DEBUG_CALL
7094  "printf(\"count = %#x\\n\",count); \n"
7095  #endif
7096  "sh_val = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) >> count);\n"
7097  #if RISCV64_DEBUG_CALL
7098  "printf(\"sh_val = %#x\\n\",sh_val); \n"
7099  #endif
7100  "etiss_int32 cast_0 = sh_val; \n"
7101  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
7102  "{\n"
7103  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
7104  "}\n"
7105  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
7106  #if RISCV64_DEBUG_CALL
7107  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7108  #endif
7109 "}\n"
7110 
7111 
7112  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7113 
7114 ;
7115 return true;
7116 },
7117 0,
7118 nullptr
7119 );
7120 //-------------------------------------------------------------------------------------------------------------------
7121 static InstructionDefinition or_rd_rs1_rs2(
7122  ISA32_RISCV64,
7123  "or",
7124  (uint32_t)0x6033,
7125  (uint32_t) 0xfe00707f,
7126  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7127  {
7128  etiss_uint64 rs2 = 0;
7129  static BitArrayRange R_rs2_0 (24,20);
7130  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7131  rs2 += rs2_0;
7132  etiss_uint64 rs1 = 0;
7133  static BitArrayRange R_rs1_0 (19,15);
7134  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7135  rs1 += rs1_0;
7136  etiss_uint64 rd = 0;
7137  static BitArrayRange R_rd_0 (11,7);
7138  etiss_uint64 rd_0 = R_rd_0.read(ba);
7139  rd += rd_0;
7140  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7141  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7142  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7143  partInit.getAffectedRegisters().add(reg_name[rd],64);
7144  partInit.getAffectedRegisters().add("instructionPointer",64);
7145  partInit.code() = std::string("//or\n")+
7146  "etiss_uint32 temp = 0;\n"
7147  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7148  #if RISCV64_Pipeline1
7149  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7150  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7151  "etiss_uint32 num_stages = 4;\n"
7152  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7153  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7154  #endif
7155  #if RISCV64_Pipeline2
7156  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7157  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7158  "etiss_uint32 num_stages = 4;\n"
7159  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7160  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7161  #endif
7162 
7163 
7164 "if(" + toString(rd) + " != 0)\n"
7165 "{\n"
7166  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] | *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
7167  #if RISCV64_DEBUG_CALL
7168  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7169  #endif
7170 "}\n"
7171 
7172 
7173  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7174 
7175 ;
7176 return true;
7177 },
7178 0,
7179 nullptr
7180 );
7181 //-------------------------------------------------------------------------------------------------------------------
7182 static InstructionDefinition and_rd_rs1_rs2(
7183  ISA32_RISCV64,
7184  "and",
7185  (uint32_t)0x7033,
7186  (uint32_t) 0xfe00707f,
7187  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7188  {
7189  etiss_uint64 rs2 = 0;
7190  static BitArrayRange R_rs2_0 (24,20);
7191  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7192  rs2 += rs2_0;
7193  etiss_uint64 rs1 = 0;
7194  static BitArrayRange R_rs1_0 (19,15);
7195  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7196  rs1 += rs1_0;
7197  etiss_uint64 rd = 0;
7198  static BitArrayRange R_rd_0 (11,7);
7199  etiss_uint64 rd_0 = R_rd_0.read(ba);
7200  rd += rd_0;
7201  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7202  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7203  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7204  partInit.getAffectedRegisters().add(reg_name[rd],64);
7205  partInit.getAffectedRegisters().add("instructionPointer",64);
7206  partInit.code() = std::string("//and\n")+
7207  "etiss_uint32 temp = 0;\n"
7208  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7209  #if RISCV64_Pipeline1
7210  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7211  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7212  "etiss_uint32 num_stages = 4;\n"
7213  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7214  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7215  #endif
7216  #if RISCV64_Pipeline2
7217  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7218  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7219  "etiss_uint32 num_stages = 4;\n"
7220  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7221  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7222  #endif
7223 
7224 
7225 "if(" + toString(rd) + " != 0)\n"
7226 "{\n"
7227  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
7228  #if RISCV64_DEBUG_CALL
7229  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7230  #endif
7231 "}\n"
7232 
7233 
7234  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7235 
7236 ;
7237 return true;
7238 },
7239 0,
7240 nullptr
7241 );
7242 //-------------------------------------------------------------------------------------------------------------------
7243 static InstructionDefinition uret_(
7244  ISA32_RISCV64,
7245  "uret",
7246  (uint32_t)0x200073,
7247  (uint32_t) 0xffffffff,
7248  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7249  {
7250  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7251  partInit.getAffectedRegisters().add("instructionPointer",64);
7252  partInit.code() = std::string("//uret\n")+
7253  "etiss_uint32 temp = 0;\n"
7254  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7255  #if RISCV64_Pipeline1
7256  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7257  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7258  "etiss_uint32 num_stages = 4;\n"
7259  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7260  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7261  #endif
7262  #if RISCV64_Pipeline2
7263  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7264  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7265  "etiss_uint32 num_stages = 4;\n"
7266  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7267  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7268  #endif
7269 
7270 
7271 "((RISCV64*)cpu)->CSR[3088] = 0;\n"//PRIVLV=0
7272 "((RISCV64*)cpu)->CSR[0] ^= ((etiss_uint32)((((RISCV64*)cpu)->CSR[0] & 0x10)>>4)) ^ (((RISCV64*)cpu)->CSR[0] & 0x1);\n"//UIE=UPIE
7273 "cpu->instructionPointer = ((RISCV64*)cpu)->CSR[65];\n"//PC=UEPC
7274 "((RISCV64*)cpu)->CSR[768]= ((RISCV64*)cpu)->CSR[0];\n"//keep MSTATUS synchronous to USTATUS
7275 "((RISCV64*)cpu)->CSR[256]=((RISCV64*)cpu)->CSR[0];\n"//keep SSTATUS synchronous to USTATUS
7276 
7277  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
7278 
7279  "return 0;\n"
7280 ;
7281 return true;
7282 },
7283 0,
7284 nullptr
7285 );
7286 //-------------------------------------------------------------------------------------------------------------------
7287 static InstructionDefinition fadd_s_rd_frs1_frs2(
7288  ISA32_RISCV64,
7289  "fadd.s",
7290  (uint32_t)0x53,
7291  (uint32_t) 0xfe00007f,
7292  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7293  {
7294  etiss_uint64 rs2 = 0;
7295  static BitArrayRange R_rs2_0 (24,20);
7296  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7297  rs2 += rs2_0;
7298  etiss_uint64 rs1 = 0;
7299  static BitArrayRange R_rs1_0 (19,15);
7300  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7301  rs1 += rs1_0;
7302  etiss_uint64 rd = 0;
7303  static BitArrayRange R_rd_0 (11,7);
7304  etiss_uint64 rd_0 = R_rd_0.read(ba);
7305  rd += rd_0;
7306  etiss_uint64 rm = 0;
7307  static BitArrayRange R_rm_0 (14,12);
7308  etiss_uint64 rm_0 = R_rm_0.read(ba);
7309  rm += rm_0;
7310  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7311  partInit.getAffectedRegisters().add(reg_name[rd],64);
7312  partInit.getAffectedRegisters().add("instructionPointer",64);
7313  partInit.code() = std::string("//fadd.s\n")+
7314  "etiss_uint32 temp = 0;\n"
7315  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7316  #if RISCV64_Pipeline1
7317  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7318  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7319  "etiss_uint32 num_stages = 4;\n"
7320  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7321  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7322  #endif
7323  #if RISCV64_Pipeline2
7324  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7325  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7326  "etiss_uint32 num_stages = 4;\n"
7327  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7328  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7329  #endif
7330 
7331  "etiss_uint32 res = 0;\n"
7332  "etiss_int64 upper = 0;\n"
7333  "etiss_uint32 flags = 0;\n"
7334  "etiss_uint32 frs1 = 0;\n"
7335  "etiss_uint32 choose1 = 0;\n"
7336  "etiss_uint32 frs2 = 0;\n"
7337 
7338 "if(64 == 32)\n"
7339 "{\n"
7340  "if(" + toString(rm) + " < 7)\n"
7341  "{\n"
7342  "choose1 = (" + toString(rm) + " & 0xff);\n"
7343  #if RISCV64_DEBUG_CALL
7344  "printf(\"choose1 = %#x\\n\",choose1); \n"
7345  #endif
7346  "}\n"
7347 
7348  "else\n"
7349  "{\n"
7350  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
7351  #if RISCV64_DEBUG_CALL
7352  "printf(\"choose1 = %#x\\n\",choose1); \n"
7353  #endif
7354  "}\n"
7355  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fadd_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], choose1);\n"
7356  #if RISCV64_DEBUG_CALL
7357  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
7358  #endif
7359 "}\n"
7360 
7361 "else\n"
7362 "{\n"
7363  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
7364  #if RISCV64_DEBUG_CALL
7365  "printf(\"frs1 = %#x\\n\",frs1); \n"
7366  #endif
7367  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
7368  #if RISCV64_DEBUG_CALL
7369  "printf(\"frs2 = %#x\\n\",frs2); \n"
7370  #endif
7371  "if(" + toString(rm) + " < 7)\n"
7372  "{\n"
7373  "choose1 = (" + toString(rm) + " & 0xff);\n"
7374  #if RISCV64_DEBUG_CALL
7375  "printf(\"choose1 = %#x\\n\",choose1); \n"
7376  #endif
7377  "}\n"
7378 
7379  "else\n"
7380  "{\n"
7381  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
7382  #if RISCV64_DEBUG_CALL
7383  "printf(\"choose1 = %#x\\n\",choose1); \n"
7384  #endif
7385  "}\n"
7386  "res = fadd_s(frs1, frs2, choose1);\n"
7387  #if RISCV64_DEBUG_CALL
7388  "printf(\"res = %#x\\n\",res); \n"
7389  #endif
7390  "upper = - 1;\n"
7391  #if RISCV64_DEBUG_CALL
7392  "printf(\"upper = %#lx\\n\",upper); \n"
7393  #endif
7394  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
7395  #if RISCV64_DEBUG_CALL
7396  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
7397  #endif
7398 "}\n"
7399 "flags = fget_flags();\n"
7400 #if RISCV64_DEBUG_CALL
7401 "printf(\"flags = %#x\\n\",flags); \n"
7402 #endif
7403 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
7404 #if RISCV64_DEBUG_CALL
7405 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
7406 #endif
7407 
7408  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7409 
7410 ;
7411 return true;
7412 },
7413 0,
7414 nullptr
7415 );
7416 //-------------------------------------------------------------------------------------------------------------------
7417 static InstructionDefinition sub_rd_rs1_rs2(
7418  ISA32_RISCV64,
7419  "sub",
7420  (uint32_t)0x40000033,
7421  (uint32_t) 0xfe00707f,
7422  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7423  {
7424  etiss_uint64 rs2 = 0;
7425  static BitArrayRange R_rs2_0 (24,20);
7426  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7427  rs2 += rs2_0;
7428  etiss_uint64 rs1 = 0;
7429  static BitArrayRange R_rs1_0 (19,15);
7430  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7431  rs1 += rs1_0;
7432  etiss_uint64 rd = 0;
7433  static BitArrayRange R_rd_0 (11,7);
7434  etiss_uint64 rd_0 = R_rd_0.read(ba);
7435  rd += rd_0;
7436  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7437  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7438  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7439  partInit.getAffectedRegisters().add(reg_name[rd],64);
7440  partInit.getAffectedRegisters().add("instructionPointer",64);
7441  partInit.code() = std::string("//sub\n")+
7442  "etiss_uint32 temp = 0;\n"
7443  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7444  #if RISCV64_Pipeline1
7445  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7446  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7447  "etiss_uint32 num_stages = 4;\n"
7448  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7449  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7450  #endif
7451  #if RISCV64_Pipeline2
7452  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7453  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7454  "etiss_uint32 num_stages = 4;\n"
7455  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7456  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7457  #endif
7458 
7459 
7460 "if(" + toString(rd) + " != 0)\n"
7461 "{\n"
7462  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = *((RISCV64*)cpu)->X[" + toString(rs1) + "] - *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
7463  #if RISCV64_DEBUG_CALL
7464  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7465  #endif
7466 "}\n"
7467 
7468 
7469  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7470 
7471 ;
7472 return true;
7473 },
7474 0,
7475 nullptr
7476 );
7477 //-------------------------------------------------------------------------------------------------------------------
7478 static InstructionDefinition subw_(
7479  ISA32_RISCV64,
7480  "subw",
7481  (uint32_t)0x4000003b,
7482  (uint32_t) 0xfe00707f,
7483  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7484  {
7485  etiss_uint64 rs2 = 0;
7486  static BitArrayRange R_rs2_0 (24,20);
7487  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7488  rs2 += rs2_0;
7489  etiss_uint64 rs1 = 0;
7490  static BitArrayRange R_rs1_0 (19,15);
7491  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7492  rs1 += rs1_0;
7493  etiss_uint64 rd = 0;
7494  static BitArrayRange R_rd_0 (11,7);
7495  etiss_uint64 rd_0 = R_rd_0.read(ba);
7496  rd += rd_0;
7497  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7498  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7499  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7500  partInit.getAffectedRegisters().add(reg_name[rd],64);
7501  partInit.getAffectedRegisters().add("instructionPointer",64);
7502  partInit.code() = std::string("//subw\n")+
7503  "etiss_uint32 temp = 0;\n"
7504  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7505  #if RISCV64_Pipeline1
7506  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7507  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7508  "etiss_uint32 num_stages = 4;\n"
7509  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7510  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7511  #endif
7512  #if RISCV64_Pipeline2
7513  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7514  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7515  "etiss_uint32 num_stages = 4;\n"
7516  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7517  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7518  #endif
7519 
7520  "etiss_uint32 res = 0;\n"
7521 
7522 "if(" + toString(rd) + " != 0)\n"
7523 "{\n"
7524  "res = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) - (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff);\n"
7525  #if RISCV64_DEBUG_CALL
7526  "printf(\"res = %#x\\n\",res); \n"
7527  #endif
7528  "etiss_int32 cast_0 = res; \n"
7529  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
7530  "{\n"
7531  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
7532  "}\n"
7533  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
7534  #if RISCV64_DEBUG_CALL
7535  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7536  #endif
7537 "}\n"
7538 
7539 
7540  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7541 
7542 ;
7543 return true;
7544 },
7545 0,
7546 nullptr
7547 );
7548 //-------------------------------------------------------------------------------------------------------------------
7549 static InstructionDefinition sra_rd_rs1_rs2(
7550  ISA32_RISCV64,
7551  "sra",
7552  (uint32_t)0x40005033,
7553  (uint32_t) 0xfe00707f,
7554  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7555  {
7556  etiss_uint64 rs2 = 0;
7557  static BitArrayRange R_rs2_0 (24,20);
7558  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7559  rs2 += rs2_0;
7560  etiss_uint64 rs1 = 0;
7561  static BitArrayRange R_rs1_0 (19,15);
7562  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7563  rs1 += rs1_0;
7564  etiss_uint64 rd = 0;
7565  static BitArrayRange R_rd_0 (11,7);
7566  etiss_uint64 rd_0 = R_rd_0.read(ba);
7567  rd += rd_0;
7568  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7569  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7570  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7571  partInit.getAffectedRegisters().add(reg_name[rd],64);
7572  partInit.getAffectedRegisters().add("instructionPointer",64);
7573  partInit.code() = std::string("//sra\n")+
7574  "etiss_uint32 temp = 0;\n"
7575  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7576  #if RISCV64_Pipeline1
7577  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7578  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7579  "etiss_uint32 num_stages = 4;\n"
7580  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7581  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7582  #endif
7583  #if RISCV64_Pipeline2
7584  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7585  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7586  "etiss_uint32 num_stages = 4;\n"
7587  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7588  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7589  #endif
7590 
7591 
7592 "if(" + toString(rd) + " != 0)\n"
7593 "{\n"
7594  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
7595  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
7596  "{\n"
7597  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
7598  "}\n"
7599  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_0 >> (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 64 - 1));\n"
7600  #if RISCV64_DEBUG_CALL
7601  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7602  #endif
7603 "}\n"
7604 
7605 
7606  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7607 
7608 ;
7609 return true;
7610 },
7611 0,
7612 nullptr
7613 );
7614 //-------------------------------------------------------------------------------------------------------------------
7615 static InstructionDefinition sraiw_rd_rs1_shamt(
7616  ISA32_RISCV64,
7617  "sraiw",
7618  (uint32_t)0x4000501b,
7619  (uint32_t) 0xfe00707f,
7620  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7621  {
7622  etiss_uint64 rs1 = 0;
7623  static BitArrayRange R_rs1_0 (19,15);
7624  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7625  rs1 += rs1_0;
7626  etiss_uint64 rd = 0;
7627  static BitArrayRange R_rd_0 (11,7);
7628  etiss_uint64 rd_0 = R_rd_0.read(ba);
7629  rd += rd_0;
7630  etiss_uint64 shamt = 0;
7631  static BitArrayRange R_shamt_0 (24,20);
7632  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
7633  shamt += shamt_0;
7634  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7635  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7636  partInit.getAffectedRegisters().add(reg_name[rd],64);
7637  partInit.getAffectedRegisters().add("instructionPointer",64);
7638  partInit.code() = std::string("//sraiw\n")+
7639  "etiss_uint32 temp = 0;\n"
7640  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7641  #if RISCV64_Pipeline1
7642  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7643  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7644  "etiss_uint32 num_stages = 4;\n"
7645  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7646  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7647  #endif
7648  #if RISCV64_Pipeline2
7649  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7650  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7651  "etiss_uint32 num_stages = 4;\n"
7652  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7653  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7654  #endif
7655 
7656  "etiss_int32 sh_val = 0;\n"
7657 
7658 "if(" + toString(rd) + " != 0)\n"
7659 "{\n"
7660  "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
7661  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
7662  "{\n"
7663  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
7664  "}\n"
7665  "sh_val = ((etiss_int32)cast_0 >> " + toString(shamt) + ");\n"
7666  #if RISCV64_DEBUG_CALL
7667  "printf(\"sh_val = %#x\\n\",sh_val); \n"
7668  #endif
7669  "etiss_int32 cast_1 = sh_val; \n"
7670  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
7671  "{\n"
7672  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
7673  "}\n"
7674  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
7675  #if RISCV64_DEBUG_CALL
7676  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7677  #endif
7678 "}\n"
7679 
7680 
7681  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7682 
7683 ;
7684 return true;
7685 },
7686 0,
7687 nullptr
7688 );
7689 //-------------------------------------------------------------------------------------------------------------------
7690 static InstructionDefinition sraw_rd_rs1_rs2(
7691  ISA32_RISCV64,
7692  "sraw",
7693  (uint32_t)0x4000503b,
7694  (uint32_t) 0xfe00707f,
7695  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7696  {
7697  etiss_uint64 rs2 = 0;
7698  static BitArrayRange R_rs2_0 (24,20);
7699  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
7700  rs2 += rs2_0;
7701  etiss_uint64 rs1 = 0;
7702  static BitArrayRange R_rs1_0 (19,15);
7703  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7704  rs1 += rs1_0;
7705  etiss_uint64 rd = 0;
7706  static BitArrayRange R_rd_0 (11,7);
7707  etiss_uint64 rd_0 = R_rd_0.read(ba);
7708  rd += rd_0;
7709  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7710  partInit.getRegisterDependencies().add(reg_name[rs2],64);
7711  partInit.getRegisterDependencies().add(reg_name[rs1],64);
7712  partInit.getAffectedRegisters().add(reg_name[rd],64);
7713  partInit.getAffectedRegisters().add("instructionPointer",64);
7714  partInit.code() = std::string("//sraw\n")+
7715  "etiss_uint32 temp = 0;\n"
7716  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7717  #if RISCV64_Pipeline1
7718  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7719  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7720  "etiss_uint32 num_stages = 4;\n"
7721  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7722  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7723  #endif
7724  #if RISCV64_Pipeline2
7725  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7726  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7727  "etiss_uint32 num_stages = 4;\n"
7728  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7729  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7730  #endif
7731 
7732  "etiss_uint32 sh_val = 0;\n"
7733  "etiss_uint32 count = 0;\n"
7734  "etiss_int32 mask = 0;\n"
7735 
7736 "if(" + toString(rd) + " != 0)\n"
7737 "{\n"
7738  "mask = 31;\n"
7739  #if RISCV64_DEBUG_CALL
7740  "printf(\"mask = %#x\\n\",mask); \n"
7741  #endif
7742  "count = ((*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff) & mask);\n"
7743  #if RISCV64_DEBUG_CALL
7744  "printf(\"count = %#x\\n\",count); \n"
7745  #endif
7746  "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
7747  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
7748  "{\n"
7749  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
7750  "}\n"
7751  "sh_val = ((etiss_int32)cast_0 >> count);\n"
7752  #if RISCV64_DEBUG_CALL
7753  "printf(\"sh_val = %#x\\n\",sh_val); \n"
7754  #endif
7755  "etiss_int32 cast_1 = sh_val; \n"
7756  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
7757  "{\n"
7758  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
7759  "}\n"
7760  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
7761  #if RISCV64_DEBUG_CALL
7762  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
7763  #endif
7764 "}\n"
7765 
7766 
7767  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7768 
7769 ;
7770 return true;
7771 },
7772 0,
7773 nullptr
7774 );
7775 //-------------------------------------------------------------------------------------------------------------------
7776 static InstructionDefinition fcvt_s_d_rd_frs1(
7777  ISA32_RISCV64,
7778  "fcvt.s.d",
7779  (uint32_t)0x40100053,
7780  (uint32_t) 0xfff0007f,
7781  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7782  {
7783  etiss_uint64 rs1 = 0;
7784  static BitArrayRange R_rs1_0 (19,15);
7785  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7786  rs1 += rs1_0;
7787  etiss_uint64 rd = 0;
7788  static BitArrayRange R_rd_0 (11,7);
7789  etiss_uint64 rd_0 = R_rd_0.read(ba);
7790  rd += rd_0;
7791  etiss_uint64 rm = 0;
7792  static BitArrayRange R_rm_0 (14,12);
7793  etiss_uint64 rm_0 = R_rm_0.read(ba);
7794  rm += rm_0;
7795  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7796  partInit.getAffectedRegisters().add(reg_name[rd],64);
7797  partInit.getAffectedRegisters().add("instructionPointer",64);
7798  partInit.code() = std::string("//fcvt.s.d\n")+
7799  "etiss_uint32 temp = 0;\n"
7800  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7801  #if RISCV64_Pipeline1
7802  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7803  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7804  "etiss_uint32 num_stages = 4;\n"
7805  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7806  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7807  #endif
7808  #if RISCV64_Pipeline2
7809  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7810  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7811  "etiss_uint32 num_stages = 4;\n"
7812  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7813  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7814  #endif
7815 
7816  "etiss_uint32 res = 0;\n"
7817  "etiss_int64 upper = 0;\n"
7818 
7819 "res = fconv_d2f(((RISCV64*)cpu)->F[" + toString(rs1) + "], (" + toString(rm) + " & 0xff));\n"
7820 #if RISCV64_DEBUG_CALL
7821 "printf(\"res = %#x\\n\",res); \n"
7822 #endif
7823 "upper = - 1;\n"
7824 #if RISCV64_DEBUG_CALL
7825 "printf(\"upper = %#lx\\n\",upper); \n"
7826 #endif
7827 "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
7828 #if RISCV64_DEBUG_CALL
7829 "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
7830 #endif
7831 
7832  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7833 
7834 ;
7835 return true;
7836 },
7837 0,
7838 nullptr
7839 );
7840 //-------------------------------------------------------------------------------------------------------------------
7841 static InstructionDefinition fence_(
7842  ISA32_RISCV64,
7843  "fence",
7844  (uint32_t)0xf,
7845  (uint32_t) 0xf000707f,
7846  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7847  {
7848  etiss_uint64 rs1 = 0;
7849  static BitArrayRange R_rs1_0 (19,15);
7850  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
7851  rs1 += rs1_0;
7852  etiss_uint64 rd = 0;
7853  static BitArrayRange R_rd_0 (11,7);
7854  etiss_uint64 rd_0 = R_rd_0.read(ba);
7855  rd += rd_0;
7856  etiss_uint64 succ = 0;
7857  static BitArrayRange R_succ_0 (23,20);
7858  etiss_uint64 succ_0 = R_succ_0.read(ba);
7859  succ += succ_0;
7860  etiss_uint64 pred = 0;
7861  static BitArrayRange R_pred_0 (27,24);
7862  etiss_uint64 pred_0 = R_pred_0.read(ba);
7863  pred += pred_0;
7864  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7865  partInit.getAffectedRegisters().add(reg_name[0],64);
7866  partInit.getAffectedRegisters().add("instructionPointer",64);
7867  partInit.code() = std::string("//fence\n")+
7868  "etiss_uint32 temp = 0;\n"
7869  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7870  #if RISCV64_Pipeline1
7871  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7872  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7873  "etiss_uint32 num_stages = 4;\n"
7874  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7875  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7876  #endif
7877  #if RISCV64_Pipeline2
7878  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7879  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7880  "etiss_uint32 num_stages = 4;\n"
7881  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7882  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7883  #endif
7884 
7885 
7886 "((RISCV64*)cpu)->FENCE[0] = ((" + toString(pred) + " << 4) | " + toString(succ) + ");\n"
7887 #if RISCV64_DEBUG_CALL
7888 "printf(\"((RISCV64*)cpu)->FENCE[0] = %#lx\\n\",((RISCV64*)cpu)->FENCE[0]); \n"
7889 #endif
7890 
7891  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7892 
7893 ;
7894 return true;
7895 },
7896 0,
7897 nullptr
7898 );
7899 //-------------------------------------------------------------------------------------------------------------------
7900 static InstructionDefinition ecall_(
7901  ISA32_RISCV64,
7902  "ecall",
7903  (uint32_t)0x73,
7904  (uint32_t) 0xffffffff,
7905  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7906  {
7907  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7908  partInit.getAffectedRegisters().add("instructionPointer",64);
7909  partInit.code() = std::string("//ecall\n")+
7910  "etiss_uint32 exception = 0;\n"
7911  "etiss_uint32 temp = 0;\n"
7912  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7913  #if RISCV64_Pipeline1
7914  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7915  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7916  "etiss_uint32 num_stages = 4;\n"
7917  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7918  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7919  #endif
7920  #if RISCV64_Pipeline2
7921  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7922  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7923  "etiss_uint32 num_stages = 4;\n"
7924  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7925  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7926  #endif
7927 
7928 
7929 "exception = ETISS_RETURNCODE_SYSCALL; \n"
7930 
7931  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7932 
7933  "return exception;\n"
7934 ;
7935 return true;
7936 },
7937 0,
7938 nullptr
7939 );
7940 //-------------------------------------------------------------------------------------------------------------------
7941 static InstructionDefinition ebreak_(
7942  ISA32_RISCV64,
7943  "ebreak",
7944  (uint32_t)0x100073,
7945  (uint32_t) 0xffffffff,
7946  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7947  {
7948  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7949  partInit.getAffectedRegisters().add("instructionPointer",64);
7950  partInit.code() = std::string("//ebreak\n")+
7951  "etiss_uint32 exception = 0;\n"
7952  "etiss_uint32 temp = 0;\n"
7953  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7954  #if RISCV64_Pipeline1
7955  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7956  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7957  "etiss_uint32 num_stages = 4;\n"
7958  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7959  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7960  #endif
7961  #if RISCV64_Pipeline2
7962  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7963  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7964  "etiss_uint32 num_stages = 4;\n"
7965  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7966  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
7967  #endif
7968 
7969 
7970 "return ETISS_RETURNCODE_CPUFINISHED; \n"
7971 
7972  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
7973 
7974  "return exception;\n"
7975 ;
7976 return true;
7977 },
7978 0,
7979 nullptr
7980 );
7981 //-------------------------------------------------------------------------------------------------------------------
7982 static InstructionDefinition sret_(
7983  ISA32_RISCV64,
7984  "sret",
7985  (uint32_t)0x10200073,
7986  (uint32_t) 0xffffffff,
7987  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
7988  {
7989  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
7990  partInit.getAffectedRegisters().add("instructionPointer",64);
7991  partInit.code() = std::string("//sret\n")+
7992  "etiss_uint32 temp = 0;\n"
7993  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
7994  #if RISCV64_Pipeline1
7995  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
7996  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
7997  "etiss_uint32 num_stages = 4;\n"
7998  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
7999  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8000  #endif
8001  #if RISCV64_Pipeline2
8002  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8003  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8004  "etiss_uint32 num_stages = 4;\n"
8005  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8006  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8007  #endif
8008 
8009 
8010 "((RISCV64*)cpu)->CSR[3088] = (((RISCV64*)cpu)->CSR[256] & 0x100)>>8;\n"//PRIVLV=SPP
8011 "((RISCV64*)cpu)->CSR[256] ^= (((RISCV64*)cpu)->CSR[256] & 0x100);\n"//SPP=0
8012 "((RISCV64*)cpu)->CSR[256] ^= ((etiss_uint32)((((RISCV64*)cpu)->CSR[256] & 0x20)>>4)) ^ (((RISCV64*)cpu)->CSR[256] & 0x2);\n"//SIE=SPIE
8013 "cpu->instructionPointer = ((RISCV64*)cpu)->CSR[321];\n"//PC=SEPC
8014 "((RISCV64*)cpu)->CSR[768]= ((RISCV64*)cpu)->CSR[256];\n"//keep MSTATUS synchronous to SSTATUS
8015 "((RISCV64*)cpu)->CSR[0]=((RISCV64*)cpu)->CSR[256];\n"//keep USTATUS synchronous to SSTATUS
8016 
8017  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
8018 
8019  "return 0;\n"
8020 ;
8021 return true;
8022 },
8023 0,
8024 nullptr
8025 );
8026 //-------------------------------------------------------------------------------------------------------------------
8027 static InstructionDefinition wfi_(
8028  ISA32_RISCV64,
8029  "wfi",
8030  (uint32_t)0x10500073,
8031  (uint32_t) 0xffffffff,
8032  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8033  {
8034  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8035  partInit.getAffectedRegisters().add("instructionPointer",64);
8036  partInit.code() = std::string("//wfi\n")+
8037  "etiss_uint32 exception = 0;\n"
8038  "etiss_uint32 temp = 0;\n"
8039  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8040  #if RISCV64_Pipeline1
8041  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8042  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8043  "etiss_uint32 num_stages = 4;\n"
8044  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8045  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8046  #endif
8047  #if RISCV64_Pipeline2
8048  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8049  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8050  "etiss_uint32 num_stages = 4;\n"
8051  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8052  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8053  #endif
8054 
8055 
8056 "return ETISS_RETURNCODE_CPUFINISHED; \n"
8057 
8058  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8059 
8060  "return exception;\n"
8061 ;
8062 return true;
8063 },
8064 0,
8065 nullptr
8066 );
8067 //-------------------------------------------------------------------------------------------------------------------
8068 static InstructionDefinition fmul_s_rd_frs1_frs2(
8069  ISA32_RISCV64,
8070  "fmul.s",
8071  (uint32_t)0x10000053,
8072  (uint32_t) 0xfe00007f,
8073  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8074  {
8075  etiss_uint64 rs2 = 0;
8076  static BitArrayRange R_rs2_0 (24,20);
8077  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8078  rs2 += rs2_0;
8079  etiss_uint64 rs1 = 0;
8080  static BitArrayRange R_rs1_0 (19,15);
8081  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8082  rs1 += rs1_0;
8083  etiss_uint64 rd = 0;
8084  static BitArrayRange R_rd_0 (11,7);
8085  etiss_uint64 rd_0 = R_rd_0.read(ba);
8086  rd += rd_0;
8087  etiss_uint64 rm = 0;
8088  static BitArrayRange R_rm_0 (14,12);
8089  etiss_uint64 rm_0 = R_rm_0.read(ba);
8090  rm += rm_0;
8091  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8092  partInit.getAffectedRegisters().add(reg_name[rd],64);
8093  partInit.getAffectedRegisters().add("instructionPointer",64);
8094  partInit.code() = std::string("//fmul.s\n")+
8095  "etiss_uint32 temp = 0;\n"
8096  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8097  #if RISCV64_Pipeline1
8098  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8099  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8100  "etiss_uint32 num_stages = 4;\n"
8101  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8102  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8103  #endif
8104  #if RISCV64_Pipeline2
8105  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8106  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8107  "etiss_uint32 num_stages = 4;\n"
8108  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8109  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8110  #endif
8111 
8112  "etiss_uint32 res = 0;\n"
8113  "etiss_int64 upper = 0;\n"
8114  "etiss_uint32 flags = 0;\n"
8115  "etiss_uint32 frs1 = 0;\n"
8116  "etiss_uint32 choose1 = 0;\n"
8117  "etiss_uint32 frs2 = 0;\n"
8118 
8119 "if(64 == 32)\n"
8120 "{\n"
8121  "if(" + toString(rm) + " < 7)\n"
8122  "{\n"
8123  "choose1 = (" + toString(rm) + " & 0xff);\n"
8124  #if RISCV64_DEBUG_CALL
8125  "printf(\"choose1 = %#x\\n\",choose1); \n"
8126  #endif
8127  "}\n"
8128 
8129  "else\n"
8130  "{\n"
8131  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
8132  #if RISCV64_DEBUG_CALL
8133  "printf(\"choose1 = %#x\\n\",choose1); \n"
8134  #endif
8135  "}\n"
8136  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fmul_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], choose1);\n"
8137  #if RISCV64_DEBUG_CALL
8138  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
8139  #endif
8140 "}\n"
8141 
8142 "else\n"
8143 "{\n"
8144  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
8145  #if RISCV64_DEBUG_CALL
8146  "printf(\"frs1 = %#x\\n\",frs1); \n"
8147  #endif
8148  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
8149  #if RISCV64_DEBUG_CALL
8150  "printf(\"frs2 = %#x\\n\",frs2); \n"
8151  #endif
8152  "if(" + toString(rm) + " < 7)\n"
8153  "{\n"
8154  "choose1 = (" + toString(rm) + " & 0xff);\n"
8155  #if RISCV64_DEBUG_CALL
8156  "printf(\"choose1 = %#x\\n\",choose1); \n"
8157  #endif
8158  "}\n"
8159 
8160  "else\n"
8161  "{\n"
8162  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
8163  #if RISCV64_DEBUG_CALL
8164  "printf(\"choose1 = %#x\\n\",choose1); \n"
8165  #endif
8166  "}\n"
8167  "res = fmul_s(frs1, frs2, choose1);\n"
8168  #if RISCV64_DEBUG_CALL
8169  "printf(\"res = %#x\\n\",res); \n"
8170  #endif
8171  "upper = - 1;\n"
8172  #if RISCV64_DEBUG_CALL
8173  "printf(\"upper = %#lx\\n\",upper); \n"
8174  #endif
8175  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
8176  #if RISCV64_DEBUG_CALL
8177  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
8178  #endif
8179 "}\n"
8180 "flags = fget_flags();\n"
8181 #if RISCV64_DEBUG_CALL
8182 "printf(\"flags = %#x\\n\",flags); \n"
8183 #endif
8184 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
8185 #if RISCV64_DEBUG_CALL
8186 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
8187 #endif
8188 
8189  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8190 
8191 ;
8192 return true;
8193 },
8194 0,
8195 nullptr
8196 );
8197 //-------------------------------------------------------------------------------------------------------------------
8198 static InstructionDefinition mret_(
8199  ISA32_RISCV64,
8200  "mret",
8201  (uint32_t)0x30200073,
8202  (uint32_t) 0xffffffff,
8203  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8204  {
8205  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8206  partInit.getAffectedRegisters().add("instructionPointer",64);
8207  partInit.code() = std::string("//mret\n")+
8208  "etiss_uint32 temp = 0;\n"
8209  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8210  #if RISCV64_Pipeline1
8211  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8212  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8213  "etiss_uint32 num_stages = 4;\n"
8214  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8215  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8216  #endif
8217  #if RISCV64_Pipeline2
8218  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8219  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8220  "etiss_uint32 num_stages = 4;\n"
8221  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8222  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8223  #endif
8224 
8225 
8226 "((RISCV64*)cpu)->CSR[3088] = (((RISCV64*)cpu)->CSR[768] & 0x1800)>>11;\n"//PRIVLV=MPP
8227 "((RISCV64*)cpu)->CSR[768] ^= (((RISCV64*)cpu)->CSR[768] & 0x1800);\n"//MPP=0
8228 "((RISCV64*)cpu)->CSR[768] ^= ((etiss_uint32)((((RISCV64*)cpu)->CSR[768] & 0x80)>>4)) ^ (((RISCV64*)cpu)->CSR[768] & 0x8);\n"//MIE=MPIE
8229 "cpu->instructionPointer = ((RISCV64*)cpu)->CSR[833];\n"//PC=MEPC
8230 "((RISCV64*)cpu)->CSR[0]= ((RISCV64*)cpu)->CSR[768];\n"//keep USTATUS synchronous to MSTATUS
8231 "((RISCV64*)cpu)->CSR[256]=((RISCV64*)cpu)->CSR[768];\n"//keep SSTATUS synchronous to MSTATUS
8232 
8233  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
8234 
8235  "return 0;\n"
8236 ;
8237 return true;
8238 },
8239 0,
8240 nullptr
8241 );
8242 //-------------------------------------------------------------------------------------------------------------------
8243 static InstructionDefinition sfence_vma_(
8244  ISA32_RISCV64,
8245  "sfence.vma",
8246  (uint32_t)0x12000073,
8247  (uint32_t) 0xfe007fff,
8248  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8249  {
8250  etiss_uint64 rs2 = 0;
8251  static BitArrayRange R_rs2_0 (24,20);
8252  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8253  rs2 += rs2_0;
8254  etiss_uint64 rs1 = 0;
8255  static BitArrayRange R_rs1_0 (19,15);
8256  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8257  rs1 += rs1_0;
8258  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8259  partInit.getAffectedRegisters().add(reg_name[2],64);
8260  partInit.getAffectedRegisters().add(reg_name[3],64);
8261  partInit.getAffectedRegisters().add("instructionPointer",64);
8262  partInit.code() = std::string("//sfence.vma\n")+
8263  "etiss_uint32 temp = 0;\n"
8264  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8265  #if RISCV64_Pipeline1
8266  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8267  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8268  "etiss_uint32 num_stages = 4;\n"
8269  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8270  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8271  #endif
8272  #if RISCV64_Pipeline2
8273  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8274  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8275  "etiss_uint32 num_stages = 4;\n"
8276  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8277  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8278  #endif
8279 
8280 
8281 "((RISCV64*)cpu)->FENCE[2] = " + toString(rs1) + ";\n"
8282 #if RISCV64_DEBUG_CALL
8283 "printf(\"((RISCV64*)cpu)->FENCE[2] = %#lx\\n\",((RISCV64*)cpu)->FENCE[2]); \n"
8284 #endif
8285 "((RISCV64*)cpu)->FENCE[3] = " + toString(rs2) + ";\n"
8286 #if RISCV64_DEBUG_CALL
8287 "printf(\"((RISCV64*)cpu)->FENCE[3] = %#lx\\n\",((RISCV64*)cpu)->FENCE[3]); \n"
8288 #endif
8289 
8290  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8291 
8292 ;
8293 return true;
8294 },
8295 0,
8296 nullptr
8297 );
8298 //-------------------------------------------------------------------------------------------------------------------
8299 static InstructionDefinition fmul_d_rd_frs1_frs2(
8300  ISA32_RISCV64,
8301  "fmul.d",
8302  (uint32_t)0x12000053,
8303  (uint32_t) 0xfe00007f,
8304  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8305  {
8306  etiss_uint64 rs2 = 0;
8307  static BitArrayRange R_rs2_0 (24,20);
8308  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8309  rs2 += rs2_0;
8310  etiss_uint64 rs1 = 0;
8311  static BitArrayRange R_rs1_0 (19,15);
8312  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8313  rs1 += rs1_0;
8314  etiss_uint64 rd = 0;
8315  static BitArrayRange R_rd_0 (11,7);
8316  etiss_uint64 rd_0 = R_rd_0.read(ba);
8317  rd += rd_0;
8318  etiss_uint64 rm = 0;
8319  static BitArrayRange R_rm_0 (14,12);
8320  etiss_uint64 rm_0 = R_rm_0.read(ba);
8321  rm += rm_0;
8322  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8323  partInit.getAffectedRegisters().add(reg_name[rd],64);
8324  partInit.getAffectedRegisters().add("instructionPointer",64);
8325  partInit.code() = std::string("//fmul.d\n")+
8326  "etiss_uint32 temp = 0;\n"
8327  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8328  #if RISCV64_Pipeline1
8329  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8330  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8331  "etiss_uint32 num_stages = 4;\n"
8332  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8333  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8334  #endif
8335  #if RISCV64_Pipeline2
8336  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8337  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8338  "etiss_uint32 num_stages = 4;\n"
8339  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8340  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8341  #endif
8342 
8343  "etiss_uint64 res = 0;\n"
8344  "etiss_int64 upper = 0;\n"
8345  "etiss_uint32 flags = 0;\n"
8346  "etiss_uint32 choose1 = 0;\n"
8347 
8348 "if(" + toString(rm) + " < 7)\n"
8349 "{\n"
8350  "choose1 = (" + toString(rm) + " & 0xff);\n"
8351  #if RISCV64_DEBUG_CALL
8352  "printf(\"choose1 = %#x\\n\",choose1); \n"
8353  #endif
8354 "}\n"
8355 
8356 "else\n"
8357 "{\n"
8358  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
8359  #if RISCV64_DEBUG_CALL
8360  "printf(\"choose1 = %#x\\n\",choose1); \n"
8361  #endif
8362 "}\n"
8363 "res = fmul_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), choose1);\n"
8364 #if RISCV64_DEBUG_CALL
8365 "printf(\"res = %#lx\\n\",res); \n"
8366 #endif
8367 "if(64 == 64)\n"
8368 "{\n"
8369  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
8370  #if RISCV64_DEBUG_CALL
8371  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
8372  #endif
8373 "}\n"
8374 
8375 "else\n"
8376 "{\n"
8377  "upper = - 1;\n"
8378  #if RISCV64_DEBUG_CALL
8379  "printf(\"upper = %#lx\\n\",upper); \n"
8380  #endif
8381  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
8382  #if RISCV64_DEBUG_CALL
8383  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
8384  #endif
8385 "}\n"
8386 "flags = fget_flags();\n"
8387 #if RISCV64_DEBUG_CALL
8388 "printf(\"flags = %#x\\n\",flags); \n"
8389 #endif
8390 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
8391 #if RISCV64_DEBUG_CALL
8392 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
8393 #endif
8394 
8395  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8396 
8397 ;
8398 return true;
8399 },
8400 0,
8401 nullptr
8402 );
8403 //-------------------------------------------------------------------------------------------------------------------
8404 static InstructionDefinition mul_rd_rs1_rs2(
8405  ISA32_RISCV64,
8406  "mul",
8407  (uint32_t)0x2000033,
8408  (uint32_t) 0xfe00707f,
8409  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8410  {
8411  etiss_uint64 rs2 = 0;
8412  static BitArrayRange R_rs2_0 (24,20);
8413  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8414  rs2 += rs2_0;
8415  etiss_uint64 rs1 = 0;
8416  static BitArrayRange R_rs1_0 (19,15);
8417  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8418  rs1 += rs1_0;
8419  etiss_uint64 rd = 0;
8420  static BitArrayRange R_rd_0 (11,7);
8421  etiss_uint64 rd_0 = R_rd_0.read(ba);
8422  rd += rd_0;
8423  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8424  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8425  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8426  partInit.getAffectedRegisters().add(reg_name[rd],64);
8427  partInit.getAffectedRegisters().add("instructionPointer",64);
8428  partInit.code() = std::string("//mul\n")+
8429  "etiss_uint32 temp = 0;\n"
8430  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8431  #if RISCV64_Pipeline1
8432  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8433  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {3}, {6, 7}};\n"
8434  "etiss_uint32 num_stages = 4;\n"
8435  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8436  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8437  #endif
8438  #if RISCV64_Pipeline2
8439  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8440  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {8}, {6, 7}};\n"
8441  "etiss_uint32 num_stages = 4;\n"
8442  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8443  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8444  #endif
8445 
8446  "etiss_uint64 res = 0;\n"
8447 
8448 "if(" + toString(rd) + " != 0)\n"
8449 "{\n"
8450  "res = ((etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs1) + "] * (etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
8451  #if RISCV64_DEBUG_CALL
8452  "printf(\"res = %#lx\\n\",res); \n"
8453  #endif
8454  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)res;\n"
8455  #if RISCV64_DEBUG_CALL
8456  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8457  #endif
8458 "}\n"
8459 
8460 
8461  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8462 
8463 ;
8464 return true;
8465 },
8466 0,
8467 nullptr
8468 );
8469 //-------------------------------------------------------------------------------------------------------------------
8470 static InstructionDefinition mulw_rd_rs1_rs2(
8471  ISA32_RISCV64,
8472  "mulw",
8473  (uint32_t)0x200003b,
8474  (uint32_t) 0xfe00707f,
8475  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8476  {
8477  etiss_uint64 rs2 = 0;
8478  static BitArrayRange R_rs2_0 (24,20);
8479  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8480  rs2 += rs2_0;
8481  etiss_uint64 rs1 = 0;
8482  static BitArrayRange R_rs1_0 (19,15);
8483  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8484  rs1 += rs1_0;
8485  etiss_uint64 rd = 0;
8486  static BitArrayRange R_rd_0 (11,7);
8487  etiss_uint64 rd_0 = R_rd_0.read(ba);
8488  rd += rd_0;
8489  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8490  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8491  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8492  partInit.getAffectedRegisters().add(reg_name[rd],64);
8493  partInit.getAffectedRegisters().add("instructionPointer",64);
8494  partInit.code() = std::string("//mulw\n")+
8495  "etiss_uint32 temp = 0;\n"
8496  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8497  #if RISCV64_Pipeline1
8498  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8499  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8500  "etiss_uint32 num_stages = 4;\n"
8501  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8502  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8503  #endif
8504  #if RISCV64_Pipeline2
8505  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8506  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8507  "etiss_uint32 num_stages = 4;\n"
8508  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8509  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8510  #endif
8511 
8512 
8513 "if(" + toString(rd) + " != 0)\n"
8514 "{\n"
8515  "etiss_int64 cast_0 = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) * (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff)); \n"
8516  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
8517  "{\n"
8518  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
8519  "}\n"
8520  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
8521  #if RISCV64_DEBUG_CALL
8522  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8523  #endif
8524 "}\n"
8525 
8526 
8527  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8528 
8529 ;
8530 return true;
8531 },
8532 0,
8533 nullptr
8534 );
8535 //-------------------------------------------------------------------------------------------------------------------
8536 static InstructionDefinition mulh_rd_rs1_rs2(
8537  ISA32_RISCV64,
8538  "mulh",
8539  (uint32_t)0x2001033,
8540  (uint32_t) 0xfe00707f,
8541  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8542  {
8543  etiss_uint64 rs2 = 0;
8544  static BitArrayRange R_rs2_0 (24,20);
8545  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8546  rs2 += rs2_0;
8547  etiss_uint64 rs1 = 0;
8548  static BitArrayRange R_rs1_0 (19,15);
8549  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8550  rs1 += rs1_0;
8551  etiss_uint64 rd = 0;
8552  static BitArrayRange R_rd_0 (11,7);
8553  etiss_uint64 rd_0 = R_rd_0.read(ba);
8554  rd += rd_0;
8555  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8556  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8557  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8558  partInit.getAffectedRegisters().add(reg_name[rd],64);
8559  partInit.getAffectedRegisters().add("instructionPointer",64);
8560  partInit.code() = std::string("//mulh\n")+
8561  "etiss_uint32 temp = 0;\n"
8562  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8563  #if RISCV64_Pipeline1
8564  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8565  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8566  "etiss_uint32 num_stages = 4;\n"
8567  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8568  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8569  #endif
8570  #if RISCV64_Pipeline2
8571  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8572  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8573  "etiss_uint32 num_stages = 4;\n"
8574  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8575  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8576  #endif
8577 
8578  "etiss_int64 res = 0;\n"
8579 
8580 "if(" + toString(rd) + " != 0)\n"
8581 "{\n"
8582  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
8583  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
8584  "{\n"
8585  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
8586  "}\n"
8587  "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
8588  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
8589  "{\n"
8590  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
8591  "}\n"
8592  "res = ((etiss_int64)cast_1 * (etiss_int64)cast_0);\n"
8593  #if RISCV64_DEBUG_CALL
8594  "printf(\"res = %#lx\\n\",res); \n"
8595  #endif
8596  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)(res >> 64);\n"
8597  #if RISCV64_DEBUG_CALL
8598  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8599  #endif
8600 "}\n"
8601 
8602 
8603  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8604 
8605 ;
8606 return true;
8607 },
8608 0,
8609 nullptr
8610 );
8611 //-------------------------------------------------------------------------------------------------------------------
8612 static InstructionDefinition mulhsu_rd_rs1_rs2(
8613  ISA32_RISCV64,
8614  "mulhsu",
8615  (uint32_t)0x2002033,
8616  (uint32_t) 0xfe00707f,
8617  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8618  {
8619  etiss_uint64 rs2 = 0;
8620  static BitArrayRange R_rs2_0 (24,20);
8621  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8622  rs2 += rs2_0;
8623  etiss_uint64 rs1 = 0;
8624  static BitArrayRange R_rs1_0 (19,15);
8625  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8626  rs1 += rs1_0;
8627  etiss_uint64 rd = 0;
8628  static BitArrayRange R_rd_0 (11,7);
8629  etiss_uint64 rd_0 = R_rd_0.read(ba);
8630  rd += rd_0;
8631  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8632  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8633  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8634  partInit.getAffectedRegisters().add(reg_name[rd],64);
8635  partInit.getAffectedRegisters().add("instructionPointer",64);
8636  partInit.code() = std::string("//mulhsu\n")+
8637  "etiss_uint32 temp = 0;\n"
8638  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8639  #if RISCV64_Pipeline1
8640  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8641  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8642  "etiss_uint32 num_stages = 4;\n"
8643  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8644  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8645  #endif
8646  #if RISCV64_Pipeline2
8647  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8648  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8649  "etiss_uint32 num_stages = 4;\n"
8650  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8651  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8652  #endif
8653 
8654  "etiss_uint64 res = 0;\n"
8655 
8656 "if(" + toString(rd) + " != 0)\n"
8657 "{\n"
8658  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
8659  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
8660  "{\n"
8661  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
8662  "}\n"
8663  "res = ((etiss_int64)cast_0 * (etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
8664  #if RISCV64_DEBUG_CALL
8665  "printf(\"res = %#lx\\n\",res); \n"
8666  #endif
8667  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)(res >> 64);\n"
8668  #if RISCV64_DEBUG_CALL
8669  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8670  #endif
8671 "}\n"
8672 
8673 
8674  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8675 
8676 ;
8677 return true;
8678 },
8679 0,
8680 nullptr
8681 );
8682 //-------------------------------------------------------------------------------------------------------------------
8683 static InstructionDefinition mulhu_rd_rs1_rs2(
8684  ISA32_RISCV64,
8685  "mulhu",
8686  (uint32_t)0x2003033,
8687  (uint32_t) 0xfe00707f,
8688  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8689  {
8690  etiss_uint64 rs2 = 0;
8691  static BitArrayRange R_rs2_0 (24,20);
8692  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8693  rs2 += rs2_0;
8694  etiss_uint64 rs1 = 0;
8695  static BitArrayRange R_rs1_0 (19,15);
8696  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8697  rs1 += rs1_0;
8698  etiss_uint64 rd = 0;
8699  static BitArrayRange R_rd_0 (11,7);
8700  etiss_uint64 rd_0 = R_rd_0.read(ba);
8701  rd += rd_0;
8702  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8703  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8704  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8705  partInit.getAffectedRegisters().add(reg_name[rd],64);
8706  partInit.getAffectedRegisters().add("instructionPointer",64);
8707  partInit.code() = std::string("//mulhu\n")+
8708  "etiss_uint32 temp = 0;\n"
8709  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8710  #if RISCV64_Pipeline1
8711  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8712  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8713  "etiss_uint32 num_stages = 4;\n"
8714  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8715  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8716  #endif
8717  #if RISCV64_Pipeline2
8718  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8719  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8720  "etiss_uint32 num_stages = 4;\n"
8721  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8722  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8723  #endif
8724 
8725  "etiss_uint64 res = 0;\n"
8726 
8727 "if(" + toString(rd) + " != 0)\n"
8728 "{\n"
8729  "res = ((etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs1) + "] * (etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
8730  #if RISCV64_DEBUG_CALL
8731  "printf(\"res = %#lx\\n\",res); \n"
8732  #endif
8733  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)(res >> 64);\n"
8734  #if RISCV64_DEBUG_CALL
8735  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8736  #endif
8737 "}\n"
8738 
8739 
8740  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8741 
8742 ;
8743 return true;
8744 },
8745 0,
8746 nullptr
8747 );
8748 //-------------------------------------------------------------------------------------------------------------------
8749 static InstructionDefinition div_rd_rs1_rs2(
8750  ISA32_RISCV64,
8751  "div",
8752  (uint32_t)0x2004033,
8753  (uint32_t) 0xfe00707f,
8754  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8755  {
8756  etiss_uint64 rs2 = 0;
8757  static BitArrayRange R_rs2_0 (24,20);
8758  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8759  rs2 += rs2_0;
8760  etiss_uint64 rs1 = 0;
8761  static BitArrayRange R_rs1_0 (19,15);
8762  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8763  rs1 += rs1_0;
8764  etiss_uint64 rd = 0;
8765  static BitArrayRange R_rd_0 (11,7);
8766  etiss_uint64 rd_0 = R_rd_0.read(ba);
8767  rd += rd_0;
8768  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8769  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8770  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8771  partInit.getAffectedRegisters().add(reg_name[rd],64);
8772  partInit.getAffectedRegisters().add("instructionPointer",64);
8773  partInit.code() = std::string("//div\n")+
8774  "etiss_uint32 temp = 0;\n"
8775  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8776  #if RISCV64_Pipeline1
8777  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8778  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8779  "etiss_uint32 num_stages = 4;\n"
8780  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8781  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8782  #endif
8783  #if RISCV64_Pipeline2
8784  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8785  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8786  "etiss_uint32 num_stages = 4;\n"
8787  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8788  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8789  #endif
8790 
8791  "etiss_int8 XLM1 = 0;\n"
8792  "etiss_int64 MMIN = 0;\n"
8793  "etiss_int64 M1 = 0;\n"
8794  "etiss_int64 ONE = 0;\n"
8795 
8796 "if(" + toString(rd) + " != 0)\n"
8797 "{\n"
8798  "if(*((RISCV64*)cpu)->X[" + toString(rs2) + "] != 0)\n"
8799  "{\n"
8800  "M1 = - 1;\n"
8801  #if RISCV64_DEBUG_CALL
8802  "printf(\"M1 = %#lx\\n\",M1); \n"
8803  #endif
8804  "XLM1 = 64 - 1;\n"
8805  #if RISCV64_DEBUG_CALL
8806  "printf(\"XLM1 = %#x\\n\",XLM1); \n"
8807  #endif
8808  "ONE = 1;\n"
8809  #if RISCV64_DEBUG_CALL
8810  "printf(\"ONE = %#lx\\n\",ONE); \n"
8811  #endif
8812  "MMIN = (ONE << XLM1);\n"
8813  #if RISCV64_DEBUG_CALL
8814  "printf(\"MMIN = %#lx\\n\",MMIN); \n"
8815  #endif
8816  "if((*((RISCV64*)cpu)->X[" + toString(rs1) + "] == MMIN) && (*((RISCV64*)cpu)->X[" + toString(rs2) + "] == M1))\n"
8817  "{\n"
8818  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = MMIN;\n"
8819  #if RISCV64_DEBUG_CALL
8820  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8821  #endif
8822  "}\n"
8823 
8824  "else\n"
8825  "{\n"
8826  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
8827  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
8828  "{\n"
8829  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
8830  "}\n"
8831  "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
8832  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
8833  "{\n"
8834  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
8835  "}\n"
8836  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_1 / (etiss_int64)cast_0);\n"
8837  #if RISCV64_DEBUG_CALL
8838  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8839  #endif
8840  "}\n"
8841  "}\n"
8842 
8843  "else\n"
8844  "{\n"
8845  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = - 1;\n"
8846  #if RISCV64_DEBUG_CALL
8847  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8848  #endif
8849  "}\n"
8850 "}\n"
8851 
8852 
8853  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8854 
8855 ;
8856 return true;
8857 },
8858 0,
8859 nullptr
8860 );
8861 //-------------------------------------------------------------------------------------------------------------------
8862 static InstructionDefinition divw_rd_rs1_rs2(
8863  ISA32_RISCV64,
8864  "divw",
8865  (uint32_t)0x200403b,
8866  (uint32_t) 0xfe00707f,
8867  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8868  {
8869  etiss_uint64 rs2 = 0;
8870  static BitArrayRange R_rs2_0 (24,20);
8871  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8872  rs2 += rs2_0;
8873  etiss_uint64 rs1 = 0;
8874  static BitArrayRange R_rs1_0 (19,15);
8875  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8876  rs1 += rs1_0;
8877  etiss_uint64 rd = 0;
8878  static BitArrayRange R_rd_0 (11,7);
8879  etiss_uint64 rd_0 = R_rd_0.read(ba);
8880  rd += rd_0;
8881  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8882  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8883  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8884  partInit.getAffectedRegisters().add(reg_name[rd],64);
8885  partInit.getAffectedRegisters().add("instructionPointer",64);
8886  partInit.code() = std::string("//divw\n")+
8887  "etiss_uint32 temp = 0;\n"
8888  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
8889  #if RISCV64_Pipeline1
8890  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8891  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8892  "etiss_uint32 num_stages = 4;\n"
8893  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8894  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8895  #endif
8896  #if RISCV64_Pipeline2
8897  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
8898  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
8899  "etiss_uint32 num_stages = 4;\n"
8900  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
8901  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
8902  #endif
8903 
8904  "etiss_int32 MMIN = 0;\n"
8905  "etiss_int32 M1 = 0;\n"
8906  "etiss_int32 ONE = 0;\n"
8907 
8908 "if(" + toString(rd) + " != 0)\n"
8909 "{\n"
8910  "if(*((RISCV64*)cpu)->X[" + toString(rs2) + "] != 0)\n"
8911  "{\n"
8912  "M1 = - 1;\n"
8913  #if RISCV64_DEBUG_CALL
8914  "printf(\"M1 = %#x\\n\",M1); \n"
8915  #endif
8916  "ONE = 1;\n"
8917  #if RISCV64_DEBUG_CALL
8918  "printf(\"ONE = %#x\\n\",ONE); \n"
8919  #endif
8920  "MMIN = (ONE << 31);\n"
8921  #if RISCV64_DEBUG_CALL
8922  "printf(\"MMIN = %#x\\n\",MMIN); \n"
8923  #endif
8924  "if(((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) == MMIN) && ((*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff) == M1))\n"
8925  "{\n"
8926  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ( - 1 << 31);\n"
8927  #if RISCV64_DEBUG_CALL
8928  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8929  #endif
8930  "}\n"
8931 
8932  "else\n"
8933  "{\n"
8934  "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff); \n"
8935  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
8936  "{\n"
8937  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
8938  "}\n"
8939  "etiss_int64 cast_1 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
8940  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
8941  "{\n"
8942  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
8943  "}\n"
8944  "etiss_int64 cast_2 = ((etiss_int64)cast_1 / (etiss_int64)cast_0); \n"
8945  "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
8946  "{\n"
8947  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
8948  "}\n"
8949  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_2;\n"
8950  #if RISCV64_DEBUG_CALL
8951  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8952  #endif
8953  "}\n"
8954  "}\n"
8955 
8956  "else\n"
8957  "{\n"
8958  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = - 1;\n"
8959  #if RISCV64_DEBUG_CALL
8960  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
8961  #endif
8962  "}\n"
8963 "}\n"
8964 
8965 
8966  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
8967 
8968 ;
8969 return true;
8970 },
8971 0,
8972 nullptr
8973 );
8974 //-------------------------------------------------------------------------------------------------------------------
8975 static InstructionDefinition divu_rd_rs1_rs2(
8976  ISA32_RISCV64,
8977  "divu",
8978  (uint32_t)0x2005033,
8979  (uint32_t) 0xfe00707f,
8980  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
8981  {
8982  etiss_uint64 rs2 = 0;
8983  static BitArrayRange R_rs2_0 (24,20);
8984  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
8985  rs2 += rs2_0;
8986  etiss_uint64 rs1 = 0;
8987  static BitArrayRange R_rs1_0 (19,15);
8988  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
8989  rs1 += rs1_0;
8990  etiss_uint64 rd = 0;
8991  static BitArrayRange R_rd_0 (11,7);
8992  etiss_uint64 rd_0 = R_rd_0.read(ba);
8993  rd += rd_0;
8994  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
8995  partInit.getRegisterDependencies().add(reg_name[rs2],64);
8996  partInit.getRegisterDependencies().add(reg_name[rs1],64);
8997  partInit.getAffectedRegisters().add(reg_name[rd],64);
8998  partInit.getAffectedRegisters().add("instructionPointer",64);
8999  partInit.code() = std::string("//divu\n")+
9000  "etiss_uint32 temp = 0;\n"
9001  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9002  #if RISCV64_Pipeline1
9003  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9004  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9005  "etiss_uint32 num_stages = 4;\n"
9006  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9007  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9008  #endif
9009  #if RISCV64_Pipeline2
9010  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9011  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9012  "etiss_uint32 num_stages = 4;\n"
9013  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9014  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9015  #endif
9016 
9017 
9018 "if(" + toString(rd) + " != 0)\n"
9019 "{\n"
9020  "if(*((RISCV64*)cpu)->X[" + toString(rs2) + "] != 0)\n"
9021  "{\n"
9022  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] / *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
9023  #if RISCV64_DEBUG_CALL
9024  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9025  #endif
9026  "}\n"
9027 
9028  "else\n"
9029  "{\n"
9030  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = - 1;\n"
9031  #if RISCV64_DEBUG_CALL
9032  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9033  #endif
9034  "}\n"
9035 "}\n"
9036 
9037 
9038  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9039 
9040 ;
9041 return true;
9042 },
9043 0,
9044 nullptr
9045 );
9046 //-------------------------------------------------------------------------------------------------------------------
9047 static InstructionDefinition divuw_rd_rs1_rs2(
9048  ISA32_RISCV64,
9049  "divuw",
9050  (uint32_t)0x200503b,
9051  (uint32_t) 0xfe00707f,
9052  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9053  {
9054  etiss_uint64 rs2 = 0;
9055  static BitArrayRange R_rs2_0 (24,20);
9056  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9057  rs2 += rs2_0;
9058  etiss_uint64 rs1 = 0;
9059  static BitArrayRange R_rs1_0 (19,15);
9060  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9061  rs1 += rs1_0;
9062  etiss_uint64 rd = 0;
9063  static BitArrayRange R_rd_0 (11,7);
9064  etiss_uint64 rd_0 = R_rd_0.read(ba);
9065  rd += rd_0;
9066  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9067  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9068  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9069  partInit.getAffectedRegisters().add(reg_name[rd],64);
9070  partInit.getAffectedRegisters().add("instructionPointer",64);
9071  partInit.code() = std::string("//divuw\n")+
9072  "etiss_uint32 temp = 0;\n"
9073  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9074  #if RISCV64_Pipeline1
9075  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9076  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9077  "etiss_uint32 num_stages = 4;\n"
9078  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9079  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9080  #endif
9081  #if RISCV64_Pipeline2
9082  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9083  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9084  "etiss_uint32 num_stages = 4;\n"
9085  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9086  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9087  #endif
9088 
9089 
9090 "if(" + toString(rd) + " != 0)\n"
9091 "{\n"
9092  "if((*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff) != 0)\n"
9093  "{\n"
9094  "etiss_int64 cast_0 = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) / (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff)); \n"
9095  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
9096  "{\n"
9097  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
9098  "}\n"
9099  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
9100  #if RISCV64_DEBUG_CALL
9101  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9102  #endif
9103  "}\n"
9104 
9105  "else\n"
9106  "{\n"
9107  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = - 1;\n"
9108  #if RISCV64_DEBUG_CALL
9109  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9110  #endif
9111  "}\n"
9112 "}\n"
9113 
9114 
9115  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9116 
9117 ;
9118 return true;
9119 },
9120 0,
9121 nullptr
9122 );
9123 //-------------------------------------------------------------------------------------------------------------------
9124 static InstructionDefinition rem_rd_rs1_rs2(
9125  ISA32_RISCV64,
9126  "rem",
9127  (uint32_t)0x2006033,
9128  (uint32_t) 0xfe00707f,
9129  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9130  {
9131  etiss_uint64 rs2 = 0;
9132  static BitArrayRange R_rs2_0 (24,20);
9133  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9134  rs2 += rs2_0;
9135  etiss_uint64 rs1 = 0;
9136  static BitArrayRange R_rs1_0 (19,15);
9137  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9138  rs1 += rs1_0;
9139  etiss_uint64 rd = 0;
9140  static BitArrayRange R_rd_0 (11,7);
9141  etiss_uint64 rd_0 = R_rd_0.read(ba);
9142  rd += rd_0;
9143  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9144  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9145  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9146  partInit.getAffectedRegisters().add(reg_name[rd],64);
9147  partInit.getAffectedRegisters().add("instructionPointer",64);
9148  partInit.code() = std::string("//rem\n")+
9149  "etiss_uint32 temp = 0;\n"
9150  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9151  #if RISCV64_Pipeline1
9152  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9153  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9154  "etiss_uint32 num_stages = 4;\n"
9155  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9156  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9157  #endif
9158  #if RISCV64_Pipeline2
9159  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9160  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9161  "etiss_uint32 num_stages = 4;\n"
9162  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9163  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9164  #endif
9165 
9166  "etiss_int32 XLM1 = 0;\n"
9167  "etiss_int64 MMIN = 0;\n"
9168  "etiss_int64 M1 = 0;\n"
9169  "etiss_int64 ONE = 0;\n"
9170 
9171 "if(" + toString(rd) + " != 0)\n"
9172 "{\n"
9173  "if(*((RISCV64*)cpu)->X[" + toString(rs2) + "] != 0)\n"
9174  "{\n"
9175  "M1 = - 1;\n"
9176  #if RISCV64_DEBUG_CALL
9177  "printf(\"M1 = %#lx\\n\",M1); \n"
9178  #endif
9179  "XLM1 = 64 - 1;\n"
9180  #if RISCV64_DEBUG_CALL
9181  "printf(\"XLM1 = %#x\\n\",XLM1); \n"
9182  #endif
9183  "ONE = 1;\n"
9184  #if RISCV64_DEBUG_CALL
9185  "printf(\"ONE = %#lx\\n\",ONE); \n"
9186  #endif
9187  "MMIN = (ONE << XLM1);\n"
9188  #if RISCV64_DEBUG_CALL
9189  "printf(\"MMIN = %#lx\\n\",MMIN); \n"
9190  #endif
9191  "if((*((RISCV64*)cpu)->X[" + toString(rs1) + "] == MMIN) && (*((RISCV64*)cpu)->X[" + toString(rs2) + "] == M1))\n"
9192  "{\n"
9193  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = 0;\n"
9194  #if RISCV64_DEBUG_CALL
9195  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9196  #endif
9197  "}\n"
9198 
9199  "else\n"
9200  "{\n"
9201  "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
9202  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
9203  "{\n"
9204  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
9205  "}\n"
9206  "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
9207  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
9208  "{\n"
9209  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
9210  "}\n"
9211  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = ((etiss_int64)cast_1 % (etiss_int64)cast_0);\n"
9212  #if RISCV64_DEBUG_CALL
9213  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9214  #endif
9215  "}\n"
9216  "}\n"
9217 
9218  "else\n"
9219  "{\n"
9220  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
9221  #if RISCV64_DEBUG_CALL
9222  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9223  #endif
9224  "}\n"
9225 "}\n"
9226 
9227 
9228  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9229 
9230 ;
9231 return true;
9232 },
9233 0,
9234 nullptr
9235 );
9236 //-------------------------------------------------------------------------------------------------------------------
9237 static InstructionDefinition remw_rd_rs1_rs2(
9238  ISA32_RISCV64,
9239  "remw",
9240  (uint32_t)0x200603b,
9241  (uint32_t) 0xfe00707f,
9242  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9243  {
9244  etiss_uint64 rs2 = 0;
9245  static BitArrayRange R_rs2_0 (24,20);
9246  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9247  rs2 += rs2_0;
9248  etiss_uint64 rs1 = 0;
9249  static BitArrayRange R_rs1_0 (19,15);
9250  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9251  rs1 += rs1_0;
9252  etiss_uint64 rd = 0;
9253  static BitArrayRange R_rd_0 (11,7);
9254  etiss_uint64 rd_0 = R_rd_0.read(ba);
9255  rd += rd_0;
9256  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9257  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9258  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9259  partInit.getAffectedRegisters().add(reg_name[rd],64);
9260  partInit.getAffectedRegisters().add("instructionPointer",64);
9261  partInit.code() = std::string("//remw\n")+
9262  "etiss_uint32 temp = 0;\n"
9263  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9264  #if RISCV64_Pipeline1
9265  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9266  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9267  "etiss_uint32 num_stages = 4;\n"
9268  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9269  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9270  #endif
9271  #if RISCV64_Pipeline2
9272  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9273  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9274  "etiss_uint32 num_stages = 4;\n"
9275  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9276  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9277  #endif
9278 
9279  "etiss_int32 MMIN = 0;\n"
9280  "etiss_int32 M1 = 0;\n"
9281  "etiss_int32 ONE = 0;\n"
9282 
9283 "if(" + toString(rd) + " != 0)\n"
9284 "{\n"
9285  "if(*((RISCV64*)cpu)->X[" + toString(rs2) + "] != 0)\n"
9286  "{\n"
9287  "M1 = - 1;\n"
9288  #if RISCV64_DEBUG_CALL
9289  "printf(\"M1 = %#x\\n\",M1); \n"
9290  #endif
9291  "ONE = 1;\n"
9292  #if RISCV64_DEBUG_CALL
9293  "printf(\"ONE = %#x\\n\",ONE); \n"
9294  #endif
9295  "MMIN = (ONE << 31);\n"
9296  #if RISCV64_DEBUG_CALL
9297  "printf(\"MMIN = %#x\\n\",MMIN); \n"
9298  #endif
9299  "if(((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) == MMIN) && (*((RISCV64*)cpu)->X[" + toString(rs2) + "] == M1))\n"
9300  "{\n"
9301  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = 0;\n"
9302  #if RISCV64_DEBUG_CALL
9303  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9304  #endif
9305  "}\n"
9306 
9307  "else\n"
9308  "{\n"
9309  "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff); \n"
9310  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
9311  "{\n"
9312  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
9313  "}\n"
9314  "etiss_int64 cast_1 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
9315  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
9316  "{\n"
9317  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
9318  "}\n"
9319  "etiss_int64 cast_2 = ((etiss_int64)cast_1 % (etiss_int64)cast_0); \n"
9320  "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
9321  "{\n"
9322  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
9323  "}\n"
9324  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_2;\n"
9325  #if RISCV64_DEBUG_CALL
9326  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9327  #endif
9328  "}\n"
9329  "}\n"
9330 
9331  "else\n"
9332  "{\n"
9333  "etiss_int64 cast_3 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
9334  "if((etiss_int64)((etiss_uint64)cast_3 - 0x8000000000000000) > 0x0)\n"
9335  "{\n"
9336  "cast_3 =0x0 + (etiss_uint64)cast_3 ;\n"
9337  "}\n"
9338  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_3;\n"
9339  #if RISCV64_DEBUG_CALL
9340  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9341  #endif
9342  "}\n"
9343 "}\n"
9344 
9345 
9346  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9347 
9348 ;
9349 return true;
9350 },
9351 0,
9352 nullptr
9353 );
9354 //-------------------------------------------------------------------------------------------------------------------
9355 static InstructionDefinition remu_rd_rs1_rs2(
9356  ISA32_RISCV64,
9357  "remu",
9358  (uint32_t)0x2007033,
9359  (uint32_t) 0xfe00707f,
9360  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9361  {
9362  etiss_uint64 rs2 = 0;
9363  static BitArrayRange R_rs2_0 (24,20);
9364  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9365  rs2 += rs2_0;
9366  etiss_uint64 rs1 = 0;
9367  static BitArrayRange R_rs1_0 (19,15);
9368  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9369  rs1 += rs1_0;
9370  etiss_uint64 rd = 0;
9371  static BitArrayRange R_rd_0 (11,7);
9372  etiss_uint64 rd_0 = R_rd_0.read(ba);
9373  rd += rd_0;
9374  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9375  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9376  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9377  partInit.getAffectedRegisters().add(reg_name[rd],64);
9378  partInit.getAffectedRegisters().add("instructionPointer",64);
9379  partInit.code() = std::string("//remu\n")+
9380  "etiss_uint32 temp = 0;\n"
9381  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9382  #if RISCV64_Pipeline1
9383  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9384  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9385  "etiss_uint32 num_stages = 4;\n"
9386  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9387  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9388  #endif
9389  #if RISCV64_Pipeline2
9390  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9391  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9392  "etiss_uint32 num_stages = 4;\n"
9393  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9394  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9395  #endif
9396 
9397 
9398 "if(" + toString(rd) + " != 0)\n"
9399 "{\n"
9400  "if(*((RISCV64*)cpu)->X[" + toString(rs2) + "] != 0)\n"
9401  "{\n"
9402  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] % *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
9403  #if RISCV64_DEBUG_CALL
9404  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9405  #endif
9406  "}\n"
9407 
9408  "else\n"
9409  "{\n"
9410  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
9411  #if RISCV64_DEBUG_CALL
9412  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9413  #endif
9414  "}\n"
9415 "}\n"
9416 
9417 
9418  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9419 
9420 ;
9421 return true;
9422 },
9423 0,
9424 nullptr
9425 );
9426 //-------------------------------------------------------------------------------------------------------------------
9427 static InstructionDefinition remuw_rd_rs1_rs2(
9428  ISA32_RISCV64,
9429  "remuw",
9430  (uint32_t)0x200703b,
9431  (uint32_t) 0xfe00707f,
9432  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9433  {
9434  etiss_uint64 rs2 = 0;
9435  static BitArrayRange R_rs2_0 (24,20);
9436  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9437  rs2 += rs2_0;
9438  etiss_uint64 rs1 = 0;
9439  static BitArrayRange R_rs1_0 (19,15);
9440  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9441  rs1 += rs1_0;
9442  etiss_uint64 rd = 0;
9443  static BitArrayRange R_rd_0 (11,7);
9444  etiss_uint64 rd_0 = R_rd_0.read(ba);
9445  rd += rd_0;
9446  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9447  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9448  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9449  partInit.getAffectedRegisters().add(reg_name[rd],64);
9450  partInit.getAffectedRegisters().add("instructionPointer",64);
9451  partInit.code() = std::string("//remuw\n")+
9452  "etiss_uint32 temp = 0;\n"
9453  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9454  #if RISCV64_Pipeline1
9455  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9456  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9457  "etiss_uint32 num_stages = 4;\n"
9458  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9459  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9460  #endif
9461  #if RISCV64_Pipeline2
9462  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9463  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9464  "etiss_uint32 num_stages = 4;\n"
9465  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9466  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9467  #endif
9468 
9469 
9470 "if(" + toString(rd) + " != 0)\n"
9471 "{\n"
9472  "if((*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff) != 0)\n"
9473  "{\n"
9474  "etiss_int64 cast_0 = ((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff) % (*((RISCV64*)cpu)->X[" + toString(rs2) + "] & 0xffffffff)); \n"
9475  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
9476  "{\n"
9477  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
9478  "}\n"
9479  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
9480  #if RISCV64_DEBUG_CALL
9481  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9482  #endif
9483  "}\n"
9484 
9485  "else\n"
9486  "{\n"
9487  "etiss_int64 cast_1 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
9488  "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
9489  "{\n"
9490  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
9491  "}\n"
9492  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
9493  #if RISCV64_DEBUG_CALL
9494  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9495  #endif
9496  "}\n"
9497 "}\n"
9498 
9499 
9500  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9501 
9502 ;
9503 return true;
9504 },
9505 0,
9506 nullptr
9507 );
9508 //-------------------------------------------------------------------------------------------------------------------
9509 static InstructionDefinition fadd_d_rd_frs1_frs2(
9510  ISA32_RISCV64,
9511  "fadd.d",
9512  (uint32_t)0x2000053,
9513  (uint32_t) 0xfe00007f,
9514  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9515  {
9516  etiss_uint64 rs2 = 0;
9517  static BitArrayRange R_rs2_0 (24,20);
9518  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9519  rs2 += rs2_0;
9520  etiss_uint64 rs1 = 0;
9521  static BitArrayRange R_rs1_0 (19,15);
9522  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9523  rs1 += rs1_0;
9524  etiss_uint64 rd = 0;
9525  static BitArrayRange R_rd_0 (11,7);
9526  etiss_uint64 rd_0 = R_rd_0.read(ba);
9527  rd += rd_0;
9528  etiss_uint64 rm = 0;
9529  static BitArrayRange R_rm_0 (14,12);
9530  etiss_uint64 rm_0 = R_rm_0.read(ba);
9531  rm += rm_0;
9532  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9533  partInit.getAffectedRegisters().add(reg_name[rd],64);
9534  partInit.getAffectedRegisters().add("instructionPointer",64);
9535  partInit.code() = std::string("//fadd.d\n")+
9536  "etiss_uint32 temp = 0;\n"
9537  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9538  #if RISCV64_Pipeline1
9539  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9540  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9541  "etiss_uint32 num_stages = 4;\n"
9542  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9543  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9544  #endif
9545  #if RISCV64_Pipeline2
9546  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9547  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9548  "etiss_uint32 num_stages = 4;\n"
9549  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9550  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9551  #endif
9552 
9553  "etiss_uint64 res = 0;\n"
9554  "etiss_int64 upper = 0;\n"
9555  "etiss_uint32 flags = 0;\n"
9556  "etiss_uint32 choose1 = 0;\n"
9557 
9558 "if(" + toString(rm) + " < 7)\n"
9559 "{\n"
9560  "choose1 = (" + toString(rm) + " & 0xff);\n"
9561  #if RISCV64_DEBUG_CALL
9562  "printf(\"choose1 = %#x\\n\",choose1); \n"
9563  #endif
9564 "}\n"
9565 
9566 "else\n"
9567 "{\n"
9568  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
9569  #if RISCV64_DEBUG_CALL
9570  "printf(\"choose1 = %#x\\n\",choose1); \n"
9571  #endif
9572 "}\n"
9573 "res = fadd_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), choose1);\n"
9574 #if RISCV64_DEBUG_CALL
9575 "printf(\"res = %#lx\\n\",res); \n"
9576 #endif
9577 "if(64 == 64)\n"
9578 "{\n"
9579  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
9580  #if RISCV64_DEBUG_CALL
9581  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
9582  #endif
9583 "}\n"
9584 
9585 "else\n"
9586 "{\n"
9587  "upper = - 1;\n"
9588  #if RISCV64_DEBUG_CALL
9589  "printf(\"upper = %#lx\\n\",upper); \n"
9590  #endif
9591  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
9592  #if RISCV64_DEBUG_CALL
9593  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
9594  #endif
9595 "}\n"
9596 "flags = fget_flags();\n"
9597 #if RISCV64_DEBUG_CALL
9598 "printf(\"flags = %#x\\n\",flags); \n"
9599 #endif
9600 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
9601 #if RISCV64_DEBUG_CALL
9602 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
9603 #endif
9604 
9605  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9606 
9607 ;
9608 return true;
9609 },
9610 0,
9611 nullptr
9612 );
9613 //-------------------------------------------------------------------------------------------------------------------
9614 static InstructionDefinition lr_w_rd_rs1(
9615  ISA32_RISCV64,
9616  "lr.w",
9617  (uint32_t)0x1000202f,
9618  (uint32_t) 0xf9f0707f,
9619  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9620  {
9621  etiss_uint64 aq = 0;
9622  static BitArrayRange R_aq_0 (26,26);
9623  etiss_uint64 aq_0 = R_aq_0.read(ba);
9624  aq += aq_0;
9625  etiss_uint64 rs1 = 0;
9626  static BitArrayRange R_rs1_0 (19,15);
9627  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9628  rs1 += rs1_0;
9629  etiss_uint64 rd = 0;
9630  static BitArrayRange R_rd_0 (11,7);
9631  etiss_uint64 rd_0 = R_rd_0.read(ba);
9632  rd += rd_0;
9633  etiss_uint64 rl = 0;
9634  static BitArrayRange R_rl_0 (25,25);
9635  etiss_uint64 rl_0 = R_rl_0.read(ba);
9636  rl += rl_0;
9637  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9638  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9639  partInit.getAffectedRegisters().add(reg_name[rd],64);
9640  partInit.getAffectedRegisters().add("instructionPointer",64);
9641  partInit.code() = std::string("//lr.w\n")+
9642  "etiss_uint32 exception = 0;\n"
9643  "etiss_uint32 temp = 0;\n"
9644  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9645  #if RISCV64_Pipeline1
9646  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9647  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9648  "etiss_uint32 num_stages = 4;\n"
9649  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9650  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9651  #endif
9652  #if RISCV64_Pipeline2
9653  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9654  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9655  "etiss_uint32 num_stages = 4;\n"
9656  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9657  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9658  #endif
9659 
9660  "etiss_uint64 offs = 0;\n"
9661 
9662 "if(" + toString(rd) + " != 0)\n"
9663 "{\n"
9664  "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
9665  #if RISCV64_DEBUG_CALL
9666  "printf(\"offs = %#lx\\n\",offs); \n"
9667  #endif
9668  "etiss_uint32 MEM_offs;\n"
9669  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
9670  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
9671  "etiss_int32 cast_0 = MEM_offs; \n"
9672  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
9673  "{\n"
9674  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
9675  "}\n"
9676  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
9677  #if RISCV64_DEBUG_CALL
9678  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9679  #endif
9680  "((RISCV64*)cpu)->RES = offs;\n"
9681  #if RISCV64_DEBUG_CALL
9682  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
9683  #endif
9684 "}\n"
9685 
9686 
9687  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9688 
9689  "return exception;\n"
9690 ;
9691 return true;
9692 },
9693 0,
9694 nullptr
9695 );
9696 //-------------------------------------------------------------------------------------------------------------------
9697 static InstructionDefinition lr_d_rd_rs1(
9698  ISA32_RISCV64,
9699  "lr.d",
9700  (uint32_t)0x1000302f,
9701  (uint32_t) 0xf9f0707f,
9702  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9703  {
9704  etiss_uint64 aq = 0;
9705  static BitArrayRange R_aq_0 (26,26);
9706  etiss_uint64 aq_0 = R_aq_0.read(ba);
9707  aq += aq_0;
9708  etiss_uint64 rs1 = 0;
9709  static BitArrayRange R_rs1_0 (19,15);
9710  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9711  rs1 += rs1_0;
9712  etiss_uint64 rd = 0;
9713  static BitArrayRange R_rd_0 (11,7);
9714  etiss_uint64 rd_0 = R_rd_0.read(ba);
9715  rd += rd_0;
9716  etiss_uint64 rl = 0;
9717  static BitArrayRange R_rl_0 (25,25);
9718  etiss_uint64 rl_0 = R_rl_0.read(ba);
9719  rl += rl_0;
9720  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9721  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9722  partInit.getAffectedRegisters().add(reg_name[rd],64);
9723  partInit.getAffectedRegisters().add("instructionPointer",64);
9724  partInit.code() = std::string("//lr.d\n")+
9725  "etiss_uint32 exception = 0;\n"
9726  "etiss_uint32 temp = 0;\n"
9727  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9728  #if RISCV64_Pipeline1
9729  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9730  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9731  "etiss_uint32 num_stages = 4;\n"
9732  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9733  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9734  #endif
9735  #if RISCV64_Pipeline2
9736  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9737  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9738  "etiss_uint32 num_stages = 4;\n"
9739  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9740  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9741  #endif
9742 
9743  "etiss_uint64 offs = 0;\n"
9744 
9745 "if(" + toString(rd) + " != 0)\n"
9746 "{\n"
9747  "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
9748  #if RISCV64_DEBUG_CALL
9749  "printf(\"offs = %#lx\\n\",offs); \n"
9750  #endif
9751  "etiss_uint64 MEM_offs;\n"
9752  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
9753  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
9754  "etiss_int64 cast_0 = MEM_offs; \n"
9755  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
9756  "{\n"
9757  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
9758  "}\n"
9759  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
9760  #if RISCV64_DEBUG_CALL
9761  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9762  #endif
9763  "((RISCV64*)cpu)->RES = offs;\n"
9764  #if RISCV64_DEBUG_CALL
9765  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
9766  #endif
9767 "}\n"
9768 
9769 
9770  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9771 
9772  "return exception;\n"
9773 ;
9774 return true;
9775 },
9776 0,
9777 nullptr
9778 );
9779 //-------------------------------------------------------------------------------------------------------------------
9780 static InstructionDefinition sc_w_rd_rs1_rs2(
9781  ISA32_RISCV64,
9782  "sc.w",
9783  (uint32_t)0x1800202f,
9784  (uint32_t) 0xf800707f,
9785  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9786  {
9787  etiss_uint64 aq = 0;
9788  static BitArrayRange R_aq_0 (26,26);
9789  etiss_uint64 aq_0 = R_aq_0.read(ba);
9790  aq += aq_0;
9791  etiss_uint64 rs2 = 0;
9792  static BitArrayRange R_rs2_0 (24,20);
9793  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9794  rs2 += rs2_0;
9795  etiss_uint64 rs1 = 0;
9796  static BitArrayRange R_rs1_0 (19,15);
9797  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9798  rs1 += rs1_0;
9799  etiss_uint64 rd = 0;
9800  static BitArrayRange R_rd_0 (11,7);
9801  etiss_uint64 rd_0 = R_rd_0.read(ba);
9802  rd += rd_0;
9803  etiss_uint64 rl = 0;
9804  static BitArrayRange R_rl_0 (25,25);
9805  etiss_uint64 rl_0 = R_rl_0.read(ba);
9806  rl += rl_0;
9807  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9808  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9809  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9810  partInit.getAffectedRegisters().add(reg_name[rd],64);
9811  partInit.getAffectedRegisters().add("instructionPointer",64);
9812  partInit.code() = std::string("//sc.w\n")+
9813  "etiss_uint32 exception = 0;\n"
9814  "etiss_uint32 temp = 0;\n"
9815  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9816  #if RISCV64_Pipeline1
9817  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9818  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9819  "etiss_uint32 num_stages = 4;\n"
9820  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9821  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9822  #endif
9823  #if RISCV64_Pipeline2
9824  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9825  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9826  "etiss_uint32 num_stages = 4;\n"
9827  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9828  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9829  #endif
9830 
9831  "etiss_uint64 offs = 0;\n"
9832 
9833 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
9834 #if RISCV64_DEBUG_CALL
9835 "printf(\"offs = %#lx\\n\",offs); \n"
9836 #endif
9837 "if(offs == ((RISCV64*)cpu)->RES)\n"
9838 "{\n"
9839  "etiss_uint32 MEM_offs;\n"
9840  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
9841  "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
9842  "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
9843  #if RISCV64_DEBUG_CALL
9844  "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
9845  #endif
9846  "if(" + toString(rd) + " != 0)\n"
9847  "{\n"
9848  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = 0;\n"
9849  #if RISCV64_DEBUG_CALL
9850  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9851  #endif
9852  "}\n"
9853 
9854  "((RISCV64*)cpu)->RES = 0;\n"
9855  #if RISCV64_DEBUG_CALL
9856  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
9857  #endif
9858 "}\n"
9859 
9860 "else\n"
9861 "{\n"
9862  "if(" + toString(rd) + " != 0)\n"
9863  "{\n"
9864  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = 1;\n"
9865  #if RISCV64_DEBUG_CALL
9866  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9867  #endif
9868  "}\n"
9869 
9870  "((RISCV64*)cpu)->RES = 0;\n"
9871  #if RISCV64_DEBUG_CALL
9872  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
9873  #endif
9874 "}\n"
9875 
9876  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9877 
9878  "return exception;\n"
9879 ;
9880 return true;
9881 },
9882 0,
9883 nullptr
9884 );
9885 //-------------------------------------------------------------------------------------------------------------------
9886 static InstructionDefinition sc_d_rd_rs1_rs2(
9887  ISA32_RISCV64,
9888  "sc.d",
9889  (uint32_t)0x1800302f,
9890  (uint32_t) 0xf800707f,
9891  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9892  {
9893  etiss_uint64 aq = 0;
9894  static BitArrayRange R_aq_0 (26,26);
9895  etiss_uint64 aq_0 = R_aq_0.read(ba);
9896  aq += aq_0;
9897  etiss_uint64 rs2 = 0;
9898  static BitArrayRange R_rs2_0 (24,20);
9899  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
9900  rs2 += rs2_0;
9901  etiss_uint64 rs1 = 0;
9902  static BitArrayRange R_rs1_0 (19,15);
9903  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
9904  rs1 += rs1_0;
9905  etiss_uint64 rd = 0;
9906  static BitArrayRange R_rd_0 (11,7);
9907  etiss_uint64 rd_0 = R_rd_0.read(ba);
9908  rd += rd_0;
9909  etiss_uint64 rl = 0;
9910  static BitArrayRange R_rl_0 (25,25);
9911  etiss_uint64 rl_0 = R_rl_0.read(ba);
9912  rl += rl_0;
9913  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
9914  partInit.getRegisterDependencies().add(reg_name[rs2],64);
9915  partInit.getRegisterDependencies().add(reg_name[rs1],64);
9916  partInit.getAffectedRegisters().add(reg_name[rd],64);
9917  partInit.getAffectedRegisters().add("instructionPointer",64);
9918  partInit.code() = std::string("//sc.d\n")+
9919  "etiss_uint32 exception = 0;\n"
9920  "etiss_uint32 temp = 0;\n"
9921  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
9922  #if RISCV64_Pipeline1
9923  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9924  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9925  "etiss_uint32 num_stages = 4;\n"
9926  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9927  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9928  #endif
9929  #if RISCV64_Pipeline2
9930  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
9931  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
9932  "etiss_uint32 num_stages = 4;\n"
9933  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
9934  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
9935  #endif
9936 
9937  "etiss_uint64 offs = 0;\n"
9938 
9939 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
9940 #if RISCV64_DEBUG_CALL
9941 "printf(\"offs = %#lx\\n\",offs); \n"
9942 #endif
9943 "if(offs == ((RISCV64*)cpu)->RES)\n"
9944 "{\n"
9945  "etiss_uint64 MEM_offs;\n"
9946  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
9947  "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
9948  "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
9949  #if RISCV64_DEBUG_CALL
9950  "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
9951  #endif
9952  "if(" + toString(rd) + " != 0)\n"
9953  "{\n"
9954  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = 0;\n"
9955  #if RISCV64_DEBUG_CALL
9956  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9957  #endif
9958  "}\n"
9959 
9960  "((RISCV64*)cpu)->RES = 0;\n"
9961  #if RISCV64_DEBUG_CALL
9962  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
9963  #endif
9964 "}\n"
9965 
9966 "else\n"
9967 "{\n"
9968  "if(" + toString(rd) + " != 0)\n"
9969  "{\n"
9970  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = 1;\n"
9971  #if RISCV64_DEBUG_CALL
9972  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
9973  #endif
9974  "}\n"
9975 
9976  "((RISCV64*)cpu)->RES = 0;\n"
9977  #if RISCV64_DEBUG_CALL
9978  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
9979  #endif
9980 "}\n"
9981 
9982  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
9983 
9984  "return exception;\n"
9985 ;
9986 return true;
9987 },
9988 0,
9989 nullptr
9990 );
9991 //-------------------------------------------------------------------------------------------------------------------
9992 static InstructionDefinition amoswap_w_rd_rs1_rs2_aqu_aq_rel_rl_(
9993  ISA32_RISCV64,
9994  "amoswap.w",
9995  (uint32_t)0x800202f,
9996  (uint32_t) 0xf800707f,
9997  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
9998  {
9999  etiss_uint64 aq = 0;
10000  static BitArrayRange R_aq_0 (26,26);
10001  etiss_uint64 aq_0 = R_aq_0.read(ba);
10002  aq += aq_0;
10003  etiss_uint64 rs2 = 0;
10004  static BitArrayRange R_rs2_0 (24,20);
10005  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10006  rs2 += rs2_0;
10007  etiss_uint64 rs1 = 0;
10008  static BitArrayRange R_rs1_0 (19,15);
10009  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10010  rs1 += rs1_0;
10011  etiss_uint64 rd = 0;
10012  static BitArrayRange R_rd_0 (11,7);
10013  etiss_uint64 rd_0 = R_rd_0.read(ba);
10014  rd += rd_0;
10015  etiss_uint64 rl = 0;
10016  static BitArrayRange R_rl_0 (25,25);
10017  etiss_uint64 rl_0 = R_rl_0.read(ba);
10018  rl += rl_0;
10019  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10020  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10021  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10022  partInit.getAffectedRegisters().add(reg_name[rd],64);
10023  partInit.getAffectedRegisters().add("instructionPointer",64);
10024  partInit.code() = std::string("//amoswap.w\n")+
10025  "etiss_uint32 exception = 0;\n"
10026  "etiss_uint32 temp = 0;\n"
10027  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10028  #if RISCV64_Pipeline1
10029  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10030  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10031  "etiss_uint32 num_stages = 4;\n"
10032  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10033  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10034  #endif
10035  #if RISCV64_Pipeline2
10036  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10037  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10038  "etiss_uint32 num_stages = 4;\n"
10039  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10040  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10041  #endif
10042 
10043  "etiss_uint64 offs = 0;\n"
10044 
10045 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10046 #if RISCV64_DEBUG_CALL
10047 "printf(\"offs = %#lx\\n\",offs); \n"
10048 #endif
10049 "if(" + toString(rd) + " != 0)\n"
10050 "{\n"
10051  "etiss_uint32 MEM_offs;\n"
10052  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10053  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
10054  "etiss_int32 cast_0 = MEM_offs; \n"
10055  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
10056  "{\n"
10057  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
10058  "}\n"
10059  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
10060  #if RISCV64_DEBUG_CALL
10061  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10062  #endif
10063 "}\n"
10064 
10065  "etiss_uint32 MEM_offs;\n"
10066 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10067 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
10068 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
10069 #if RISCV64_DEBUG_CALL
10070 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10071 #endif
10072 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10073 "{\n"
10074  "((RISCV64*)cpu)->RES = 0;\n"
10075  #if RISCV64_DEBUG_CALL
10076  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10077  #endif
10078 "}\n"
10079 
10080 
10081  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10082 
10083  "return exception;\n"
10084 ;
10085 return true;
10086 },
10087 0,
10088 nullptr
10089 );
10090 //-------------------------------------------------------------------------------------------------------------------
10091 static InstructionDefinition amoswap_d_rd_rs1_rs2_aqu_aq_rel_rl_(
10092  ISA32_RISCV64,
10093  "amoswap.d",
10094  (uint32_t)0x800302f,
10095  (uint32_t) 0xf800707f,
10096  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10097  {
10098  etiss_uint64 aq = 0;
10099  static BitArrayRange R_aq_0 (26,26);
10100  etiss_uint64 aq_0 = R_aq_0.read(ba);
10101  aq += aq_0;
10102  etiss_uint64 rs2 = 0;
10103  static BitArrayRange R_rs2_0 (24,20);
10104  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10105  rs2 += rs2_0;
10106  etiss_uint64 rs1 = 0;
10107  static BitArrayRange R_rs1_0 (19,15);
10108  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10109  rs1 += rs1_0;
10110  etiss_uint64 rd = 0;
10111  static BitArrayRange R_rd_0 (11,7);
10112  etiss_uint64 rd_0 = R_rd_0.read(ba);
10113  rd += rd_0;
10114  etiss_uint64 rl = 0;
10115  static BitArrayRange R_rl_0 (25,25);
10116  etiss_uint64 rl_0 = R_rl_0.read(ba);
10117  rl += rl_0;
10118  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10119  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10120  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10121  partInit.getAffectedRegisters().add(reg_name[rd],64);
10122  partInit.getAffectedRegisters().add("instructionPointer",64);
10123  partInit.code() = std::string("//amoswap.d\n")+
10124  "etiss_uint32 exception = 0;\n"
10125  "etiss_uint32 temp = 0;\n"
10126  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10127  #if RISCV64_Pipeline1
10128  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10129  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10130  "etiss_uint32 num_stages = 4;\n"
10131  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10132  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10133  #endif
10134  #if RISCV64_Pipeline2
10135  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10136  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10137  "etiss_uint32 num_stages = 4;\n"
10138  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10139  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10140  #endif
10141 
10142  "etiss_uint64 offs = 0;\n"
10143 
10144 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10145 #if RISCV64_DEBUG_CALL
10146 "printf(\"offs = %#lx\\n\",offs); \n"
10147 #endif
10148 "if(" + toString(rd) + " != 0)\n"
10149 "{\n"
10150  "etiss_uint64 MEM_offs;\n"
10151  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10152  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
10153  "etiss_int64 cast_0 = MEM_offs; \n"
10154  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
10155  "{\n"
10156  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
10157  "}\n"
10158  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
10159  #if RISCV64_DEBUG_CALL
10160  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10161  #endif
10162 "}\n"
10163 
10164  "etiss_uint64 MEM_offs;\n"
10165 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10166 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
10167 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
10168 #if RISCV64_DEBUG_CALL
10169 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10170 #endif
10171 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10172 "{\n"
10173  "((RISCV64*)cpu)->RES = 0;\n"
10174  #if RISCV64_DEBUG_CALL
10175  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10176  #endif
10177 "}\n"
10178 
10179 
10180  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10181 
10182  "return exception;\n"
10183 ;
10184 return true;
10185 },
10186 0,
10187 nullptr
10188 );
10189 //-------------------------------------------------------------------------------------------------------------------
10190 static InstructionDefinition amoadd_w_rd_rs1_rs2_aqu_aq_rel_rl_(
10191  ISA32_RISCV64,
10192  "amoadd.w",
10193  (uint32_t)0x202f,
10194  (uint32_t) 0xf800707f,
10195  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10196  {
10197  etiss_uint64 aq = 0;
10198  static BitArrayRange R_aq_0 (26,26);
10199  etiss_uint64 aq_0 = R_aq_0.read(ba);
10200  aq += aq_0;
10201  etiss_uint64 rs2 = 0;
10202  static BitArrayRange R_rs2_0 (24,20);
10203  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10204  rs2 += rs2_0;
10205  etiss_uint64 rs1 = 0;
10206  static BitArrayRange R_rs1_0 (19,15);
10207  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10208  rs1 += rs1_0;
10209  etiss_uint64 rd = 0;
10210  static BitArrayRange R_rd_0 (11,7);
10211  etiss_uint64 rd_0 = R_rd_0.read(ba);
10212  rd += rd_0;
10213  etiss_uint64 rl = 0;
10214  static BitArrayRange R_rl_0 (25,25);
10215  etiss_uint64 rl_0 = R_rl_0.read(ba);
10216  rl += rl_0;
10217  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10218  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10219  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10220  partInit.getAffectedRegisters().add(reg_name[rd],64);
10221  partInit.getAffectedRegisters().add("instructionPointer",64);
10222  partInit.code() = std::string("//amoadd.w\n")+
10223  "etiss_uint32 exception = 0;\n"
10224  "etiss_uint32 temp = 0;\n"
10225  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10226  #if RISCV64_Pipeline1
10227  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10228  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10229  "etiss_uint32 num_stages = 4;\n"
10230  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10231  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10232  #endif
10233  #if RISCV64_Pipeline2
10234  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10235  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10236  "etiss_uint32 num_stages = 4;\n"
10237  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10238  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10239  #endif
10240 
10241  "etiss_uint64 offs = 0;\n"
10242  "etiss_int64 res1 = 0;\n"
10243  "etiss_uint64 res2 = 0;\n"
10244 
10245 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10246 #if RISCV64_DEBUG_CALL
10247 "printf(\"offs = %#lx\\n\",offs); \n"
10248 #endif
10249  "etiss_uint32 MEM_offs;\n"
10250 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10251 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
10252 "etiss_int32 cast_0 = MEM_offs; \n"
10253 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
10254 "{\n"
10255  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
10256 "}\n"
10257 "res1 = (etiss_int64)cast_0;\n"
10258 #if RISCV64_DEBUG_CALL
10259 "printf(\"res1 = %#lx\\n\",res1); \n"
10260 #endif
10261 "if(" + toString(rd) + " != 0)\n"
10262 "{\n"
10263  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
10264  #if RISCV64_DEBUG_CALL
10265  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10266  #endif
10267 "}\n"
10268 
10269 "res2 = res1 + *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
10270 #if RISCV64_DEBUG_CALL
10271 "printf(\"res2 = %#lx\\n\",res2); \n"
10272 #endif
10273  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10274 "MEM_offs = res2;\n"
10275 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
10276 #if RISCV64_DEBUG_CALL
10277 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10278 #endif
10279 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10280 "{\n"
10281  "((RISCV64*)cpu)->RES = 0;\n"
10282  #if RISCV64_DEBUG_CALL
10283  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10284  #endif
10285 "}\n"
10286 
10287 
10288  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10289 
10290  "return exception;\n"
10291 ;
10292 return true;
10293 },
10294 0,
10295 nullptr
10296 );
10297 //-------------------------------------------------------------------------------------------------------------------
10298 static InstructionDefinition amoadd_d_rd_rs1_rs2_aqu_aq_rel_rl_(
10299  ISA32_RISCV64,
10300  "amoadd.d",
10301  (uint32_t)0x302f,
10302  (uint32_t) 0xf800707f,
10303  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10304  {
10305  etiss_uint64 aq = 0;
10306  static BitArrayRange R_aq_0 (26,26);
10307  etiss_uint64 aq_0 = R_aq_0.read(ba);
10308  aq += aq_0;
10309  etiss_uint64 rs2 = 0;
10310  static BitArrayRange R_rs2_0 (24,20);
10311  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10312  rs2 += rs2_0;
10313  etiss_uint64 rs1 = 0;
10314  static BitArrayRange R_rs1_0 (19,15);
10315  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10316  rs1 += rs1_0;
10317  etiss_uint64 rd = 0;
10318  static BitArrayRange R_rd_0 (11,7);
10319  etiss_uint64 rd_0 = R_rd_0.read(ba);
10320  rd += rd_0;
10321  etiss_uint64 rl = 0;
10322  static BitArrayRange R_rl_0 (25,25);
10323  etiss_uint64 rl_0 = R_rl_0.read(ba);
10324  rl += rl_0;
10325  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10326  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10327  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10328  partInit.getAffectedRegisters().add(reg_name[rd],64);
10329  partInit.getAffectedRegisters().add("instructionPointer",64);
10330  partInit.code() = std::string("//amoadd.d\n")+
10331  "etiss_uint32 exception = 0;\n"
10332  "etiss_uint32 temp = 0;\n"
10333  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10334  #if RISCV64_Pipeline1
10335  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10336  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10337  "etiss_uint32 num_stages = 4;\n"
10338  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10339  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10340  #endif
10341  #if RISCV64_Pipeline2
10342  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10343  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10344  "etiss_uint32 num_stages = 4;\n"
10345  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10346  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10347  #endif
10348 
10349  "etiss_uint64 offs = 0;\n"
10350  "etiss_int64 res = 0;\n"
10351  "etiss_uint64 res2 = 0;\n"
10352 
10353 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10354 #if RISCV64_DEBUG_CALL
10355 "printf(\"offs = %#lx\\n\",offs); \n"
10356 #endif
10357  "etiss_uint64 MEM_offs;\n"
10358 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10359 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
10360 "etiss_int64 cast_0 = MEM_offs; \n"
10361 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
10362 "{\n"
10363  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
10364 "}\n"
10365 "res = (etiss_int64)cast_0;\n"
10366 #if RISCV64_DEBUG_CALL
10367 "printf(\"res = %#lx\\n\",res); \n"
10368 #endif
10369 "if(" + toString(rd) + " != 0)\n"
10370 "{\n"
10371  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
10372  #if RISCV64_DEBUG_CALL
10373  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10374  #endif
10375 "}\n"
10376 
10377 "res2 = res + *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
10378 #if RISCV64_DEBUG_CALL
10379 "printf(\"res2 = %#lx\\n\",res2); \n"
10380 #endif
10381  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10382 "MEM_offs = res2;\n"
10383 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
10384 #if RISCV64_DEBUG_CALL
10385 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10386 #endif
10387 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10388 "{\n"
10389  "((RISCV64*)cpu)->RES = 0;\n"
10390  #if RISCV64_DEBUG_CALL
10391  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10392  #endif
10393 "}\n"
10394 
10395 
10396  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10397 
10398  "return exception;\n"
10399 ;
10400 return true;
10401 },
10402 0,
10403 nullptr
10404 );
10405 //-------------------------------------------------------------------------------------------------------------------
10406 static InstructionDefinition amoxor_w_rd_rs1_rs2_aqu_aq_rel_rl_(
10407  ISA32_RISCV64,
10408  "amoxor.w",
10409  (uint32_t)0x2000202f,
10410  (uint32_t) 0xf800707f,
10411  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10412  {
10413  etiss_uint64 aq = 0;
10414  static BitArrayRange R_aq_0 (26,26);
10415  etiss_uint64 aq_0 = R_aq_0.read(ba);
10416  aq += aq_0;
10417  etiss_uint64 rs2 = 0;
10418  static BitArrayRange R_rs2_0 (24,20);
10419  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10420  rs2 += rs2_0;
10421  etiss_uint64 rs1 = 0;
10422  static BitArrayRange R_rs1_0 (19,15);
10423  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10424  rs1 += rs1_0;
10425  etiss_uint64 rd = 0;
10426  static BitArrayRange R_rd_0 (11,7);
10427  etiss_uint64 rd_0 = R_rd_0.read(ba);
10428  rd += rd_0;
10429  etiss_uint64 rl = 0;
10430  static BitArrayRange R_rl_0 (25,25);
10431  etiss_uint64 rl_0 = R_rl_0.read(ba);
10432  rl += rl_0;
10433  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10434  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10435  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10436  partInit.getAffectedRegisters().add(reg_name[rd],64);
10437  partInit.getAffectedRegisters().add("instructionPointer",64);
10438  partInit.code() = std::string("//amoxor.w\n")+
10439  "etiss_uint32 exception = 0;\n"
10440  "etiss_uint32 temp = 0;\n"
10441  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10442  #if RISCV64_Pipeline1
10443  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10444  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10445  "etiss_uint32 num_stages = 4;\n"
10446  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10447  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10448  #endif
10449  #if RISCV64_Pipeline2
10450  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10451  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10452  "etiss_uint32 num_stages = 4;\n"
10453  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10454  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10455  #endif
10456 
10457  "etiss_uint64 offs = 0;\n"
10458  "etiss_int64 res1 = 0;\n"
10459  "etiss_uint64 res2 = 0;\n"
10460 
10461 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10462 #if RISCV64_DEBUG_CALL
10463 "printf(\"offs = %#lx\\n\",offs); \n"
10464 #endif
10465  "etiss_uint32 MEM_offs;\n"
10466 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10467 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
10468 "etiss_int32 cast_0 = MEM_offs; \n"
10469 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
10470 "{\n"
10471  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
10472 "}\n"
10473 "res1 = (etiss_int64)cast_0;\n"
10474 #if RISCV64_DEBUG_CALL
10475 "printf(\"res1 = %#lx\\n\",res1); \n"
10476 #endif
10477 "if(" + toString(rd) + " != 0)\n"
10478 "{\n"
10479  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
10480  #if RISCV64_DEBUG_CALL
10481  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10482  #endif
10483 "}\n"
10484 
10485 "res2 = (res1 ^ *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
10486 #if RISCV64_DEBUG_CALL
10487 "printf(\"res2 = %#lx\\n\",res2); \n"
10488 #endif
10489  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10490 "MEM_offs = res2;\n"
10491 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
10492 #if RISCV64_DEBUG_CALL
10493 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10494 #endif
10495 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10496 "{\n"
10497  "((RISCV64*)cpu)->RES = 0;\n"
10498  #if RISCV64_DEBUG_CALL
10499  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10500  #endif
10501 "}\n"
10502 
10503 
10504  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10505 
10506  "return exception;\n"
10507 ;
10508 return true;
10509 },
10510 0,
10511 nullptr
10512 );
10513 //-------------------------------------------------------------------------------------------------------------------
10514 static InstructionDefinition amoxor_d_rd_rs1_rs2_aqu_aq_rel_rl_(
10515  ISA32_RISCV64,
10516  "amoxor.d",
10517  (uint32_t)0x2000302f,
10518  (uint32_t) 0xf800707f,
10519  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10520  {
10521  etiss_uint64 aq = 0;
10522  static BitArrayRange R_aq_0 (26,26);
10523  etiss_uint64 aq_0 = R_aq_0.read(ba);
10524  aq += aq_0;
10525  etiss_uint64 rs2 = 0;
10526  static BitArrayRange R_rs2_0 (24,20);
10527  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10528  rs2 += rs2_0;
10529  etiss_uint64 rs1 = 0;
10530  static BitArrayRange R_rs1_0 (19,15);
10531  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10532  rs1 += rs1_0;
10533  etiss_uint64 rd = 0;
10534  static BitArrayRange R_rd_0 (11,7);
10535  etiss_uint64 rd_0 = R_rd_0.read(ba);
10536  rd += rd_0;
10537  etiss_uint64 rl = 0;
10538  static BitArrayRange R_rl_0 (25,25);
10539  etiss_uint64 rl_0 = R_rl_0.read(ba);
10540  rl += rl_0;
10541  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10542  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10543  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10544  partInit.getAffectedRegisters().add(reg_name[rd],64);
10545  partInit.getAffectedRegisters().add("instructionPointer",64);
10546  partInit.code() = std::string("//amoxor.d\n")+
10547  "etiss_uint32 exception = 0;\n"
10548  "etiss_uint32 temp = 0;\n"
10549  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10550  #if RISCV64_Pipeline1
10551  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10552  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10553  "etiss_uint32 num_stages = 4;\n"
10554  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10555  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10556  #endif
10557  #if RISCV64_Pipeline2
10558  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10559  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10560  "etiss_uint32 num_stages = 4;\n"
10561  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10562  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10563  #endif
10564 
10565  "etiss_uint64 offs = 0;\n"
10566  "etiss_int64 res = 0;\n"
10567  "etiss_uint64 res2 = 0;\n"
10568 
10569 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10570 #if RISCV64_DEBUG_CALL
10571 "printf(\"offs = %#lx\\n\",offs); \n"
10572 #endif
10573  "etiss_uint64 MEM_offs;\n"
10574 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10575 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
10576 "etiss_int64 cast_0 = MEM_offs; \n"
10577 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
10578 "{\n"
10579  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
10580 "}\n"
10581 "res = (etiss_int64)cast_0;\n"
10582 #if RISCV64_DEBUG_CALL
10583 "printf(\"res = %#lx\\n\",res); \n"
10584 #endif
10585 "if(" + toString(rd) + " != 0)\n"
10586 "{\n"
10587  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
10588  #if RISCV64_DEBUG_CALL
10589  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10590  #endif
10591 "}\n"
10592 
10593 "res2 = (res ^ *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
10594 #if RISCV64_DEBUG_CALL
10595 "printf(\"res2 = %#lx\\n\",res2); \n"
10596 #endif
10597  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10598 "MEM_offs = res2;\n"
10599 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
10600 #if RISCV64_DEBUG_CALL
10601 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10602 #endif
10603 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10604 "{\n"
10605  "((RISCV64*)cpu)->RES = 0;\n"
10606  #if RISCV64_DEBUG_CALL
10607  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10608  #endif
10609 "}\n"
10610 
10611 
10612  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10613 
10614  "return exception;\n"
10615 ;
10616 return true;
10617 },
10618 0,
10619 nullptr
10620 );
10621 //-------------------------------------------------------------------------------------------------------------------
10622 static InstructionDefinition amoand_w_rd_rs1_rs2_aqu_aq_rel_rl_(
10623  ISA32_RISCV64,
10624  "amoand.w",
10625  (uint32_t)0x6000202f,
10626  (uint32_t) 0xf800707f,
10627  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10628  {
10629  etiss_uint64 aq = 0;
10630  static BitArrayRange R_aq_0 (26,26);
10631  etiss_uint64 aq_0 = R_aq_0.read(ba);
10632  aq += aq_0;
10633  etiss_uint64 rs2 = 0;
10634  static BitArrayRange R_rs2_0 (24,20);
10635  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10636  rs2 += rs2_0;
10637  etiss_uint64 rs1 = 0;
10638  static BitArrayRange R_rs1_0 (19,15);
10639  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10640  rs1 += rs1_0;
10641  etiss_uint64 rd = 0;
10642  static BitArrayRange R_rd_0 (11,7);
10643  etiss_uint64 rd_0 = R_rd_0.read(ba);
10644  rd += rd_0;
10645  etiss_uint64 rl = 0;
10646  static BitArrayRange R_rl_0 (25,25);
10647  etiss_uint64 rl_0 = R_rl_0.read(ba);
10648  rl += rl_0;
10649  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10650  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10651  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10652  partInit.getAffectedRegisters().add(reg_name[rd],64);
10653  partInit.getAffectedRegisters().add("instructionPointer",64);
10654  partInit.code() = std::string("//amoand.w\n")+
10655  "etiss_uint32 exception = 0;\n"
10656  "etiss_uint32 temp = 0;\n"
10657  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10658  #if RISCV64_Pipeline1
10659  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10660  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10661  "etiss_uint32 num_stages = 4;\n"
10662  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10663  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10664  #endif
10665  #if RISCV64_Pipeline2
10666  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10667  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10668  "etiss_uint32 num_stages = 4;\n"
10669  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10670  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10671  #endif
10672 
10673  "etiss_uint64 offs = 0;\n"
10674  "etiss_int64 res1 = 0;\n"
10675  "etiss_uint64 res2 = 0;\n"
10676 
10677 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10678 #if RISCV64_DEBUG_CALL
10679 "printf(\"offs = %#lx\\n\",offs); \n"
10680 #endif
10681  "etiss_uint32 MEM_offs;\n"
10682 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10683 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
10684 "etiss_int32 cast_0 = MEM_offs; \n"
10685 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
10686 "{\n"
10687  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
10688 "}\n"
10689 "res1 = (etiss_int64)cast_0;\n"
10690 #if RISCV64_DEBUG_CALL
10691 "printf(\"res1 = %#lx\\n\",res1); \n"
10692 #endif
10693 "if(" + toString(rd) + " != 0)\n"
10694 "{\n"
10695  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
10696  #if RISCV64_DEBUG_CALL
10697  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10698  #endif
10699 "}\n"
10700 
10701 "res2 = (res1 & *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
10702 #if RISCV64_DEBUG_CALL
10703 "printf(\"res2 = %#lx\\n\",res2); \n"
10704 #endif
10705  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10706 "MEM_offs = res2;\n"
10707 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
10708 #if RISCV64_DEBUG_CALL
10709 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10710 #endif
10711 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10712 "{\n"
10713  "((RISCV64*)cpu)->RES = 0;\n"
10714  #if RISCV64_DEBUG_CALL
10715  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10716  #endif
10717 "}\n"
10718 
10719 
10720  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10721 
10722  "return exception;\n"
10723 ;
10724 return true;
10725 },
10726 0,
10727 nullptr
10728 );
10729 //-------------------------------------------------------------------------------------------------------------------
10730 static InstructionDefinition amoand_d_rd_rs1_rs2_aqu_aq_rel_rl_(
10731  ISA32_RISCV64,
10732  "amoand.d",
10733  (uint32_t)0x6000302f,
10734  (uint32_t) 0xf800707f,
10735  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10736  {
10737  etiss_uint64 aq = 0;
10738  static BitArrayRange R_aq_0 (26,26);
10739  etiss_uint64 aq_0 = R_aq_0.read(ba);
10740  aq += aq_0;
10741  etiss_uint64 rs2 = 0;
10742  static BitArrayRange R_rs2_0 (24,20);
10743  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10744  rs2 += rs2_0;
10745  etiss_uint64 rs1 = 0;
10746  static BitArrayRange R_rs1_0 (19,15);
10747  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10748  rs1 += rs1_0;
10749  etiss_uint64 rd = 0;
10750  static BitArrayRange R_rd_0 (11,7);
10751  etiss_uint64 rd_0 = R_rd_0.read(ba);
10752  rd += rd_0;
10753  etiss_uint64 rl = 0;
10754  static BitArrayRange R_rl_0 (25,25);
10755  etiss_uint64 rl_0 = R_rl_0.read(ba);
10756  rl += rl_0;
10757  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10758  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10759  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10760  partInit.getAffectedRegisters().add(reg_name[rd],64);
10761  partInit.getAffectedRegisters().add("instructionPointer",64);
10762  partInit.code() = std::string("//amoand.d\n")+
10763  "etiss_uint32 exception = 0;\n"
10764  "etiss_uint32 temp = 0;\n"
10765  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10766  #if RISCV64_Pipeline1
10767  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10768  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10769  "etiss_uint32 num_stages = 4;\n"
10770  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10771  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10772  #endif
10773  #if RISCV64_Pipeline2
10774  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10775  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10776  "etiss_uint32 num_stages = 4;\n"
10777  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10778  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10779  #endif
10780 
10781  "etiss_uint64 offs = 0;\n"
10782  "etiss_int64 res = 0;\n"
10783  "etiss_uint64 res2 = 0;\n"
10784 
10785 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10786 #if RISCV64_DEBUG_CALL
10787 "printf(\"offs = %#lx\\n\",offs); \n"
10788 #endif
10789  "etiss_uint64 MEM_offs;\n"
10790 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10791 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
10792 "etiss_int64 cast_0 = MEM_offs; \n"
10793 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
10794 "{\n"
10795  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
10796 "}\n"
10797 "res = (etiss_int64)cast_0;\n"
10798 #if RISCV64_DEBUG_CALL
10799 "printf(\"res = %#lx\\n\",res); \n"
10800 #endif
10801 "if(" + toString(rd) + " != 0)\n"
10802 "{\n"
10803  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
10804  #if RISCV64_DEBUG_CALL
10805  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10806  #endif
10807 "}\n"
10808 
10809 "res2 = (res & *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
10810 #if RISCV64_DEBUG_CALL
10811 "printf(\"res2 = %#lx\\n\",res2); \n"
10812 #endif
10813  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10814 "MEM_offs = res2;\n"
10815 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
10816 #if RISCV64_DEBUG_CALL
10817 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10818 #endif
10819 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10820 "{\n"
10821  "((RISCV64*)cpu)->RES = 0;\n"
10822  #if RISCV64_DEBUG_CALL
10823  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10824  #endif
10825 "}\n"
10826 
10827 
10828  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10829 
10830  "return exception;\n"
10831 ;
10832 return true;
10833 },
10834 0,
10835 nullptr
10836 );
10837 //-------------------------------------------------------------------------------------------------------------------
10838 static InstructionDefinition amoor_w_rd_rs1_rs2_aqu_aq_rel_rl_(
10839  ISA32_RISCV64,
10840  "amoor.w",
10841  (uint32_t)0x4000202f,
10842  (uint32_t) 0xf800707f,
10843  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10844  {
10845  etiss_uint64 aq = 0;
10846  static BitArrayRange R_aq_0 (26,26);
10847  etiss_uint64 aq_0 = R_aq_0.read(ba);
10848  aq += aq_0;
10849  etiss_uint64 rs2 = 0;
10850  static BitArrayRange R_rs2_0 (24,20);
10851  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10852  rs2 += rs2_0;
10853  etiss_uint64 rs1 = 0;
10854  static BitArrayRange R_rs1_0 (19,15);
10855  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10856  rs1 += rs1_0;
10857  etiss_uint64 rd = 0;
10858  static BitArrayRange R_rd_0 (11,7);
10859  etiss_uint64 rd_0 = R_rd_0.read(ba);
10860  rd += rd_0;
10861  etiss_uint64 rl = 0;
10862  static BitArrayRange R_rl_0 (25,25);
10863  etiss_uint64 rl_0 = R_rl_0.read(ba);
10864  rl += rl_0;
10865  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10866  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10867  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10868  partInit.getAffectedRegisters().add(reg_name[rd],64);
10869  partInit.getAffectedRegisters().add("instructionPointer",64);
10870  partInit.code() = std::string("//amoor.w\n")+
10871  "etiss_uint32 exception = 0;\n"
10872  "etiss_uint32 temp = 0;\n"
10873  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10874  #if RISCV64_Pipeline1
10875  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10876  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10877  "etiss_uint32 num_stages = 4;\n"
10878  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10879  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10880  #endif
10881  #if RISCV64_Pipeline2
10882  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10883  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10884  "etiss_uint32 num_stages = 4;\n"
10885  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10886  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10887  #endif
10888 
10889  "etiss_uint64 offs = 0;\n"
10890  "etiss_int64 res1 = 0;\n"
10891  "etiss_uint64 res2 = 0;\n"
10892 
10893 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
10894 #if RISCV64_DEBUG_CALL
10895 "printf(\"offs = %#lx\\n\",offs); \n"
10896 #endif
10897  "etiss_uint32 MEM_offs;\n"
10898 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10899 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
10900 "etiss_int32 cast_0 = MEM_offs; \n"
10901 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
10902 "{\n"
10903  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
10904 "}\n"
10905 "res1 = (etiss_int64)cast_0;\n"
10906 #if RISCV64_DEBUG_CALL
10907 "printf(\"res1 = %#lx\\n\",res1); \n"
10908 #endif
10909 "if(" + toString(rd) + " != 0)\n"
10910 "{\n"
10911  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
10912  #if RISCV64_DEBUG_CALL
10913  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
10914  #endif
10915 "}\n"
10916 
10917 "res2 = (res1 | *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
10918 #if RISCV64_DEBUG_CALL
10919 "printf(\"res2 = %#lx\\n\",res2); \n"
10920 #endif
10921  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
10922 "MEM_offs = res2;\n"
10923 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
10924 #if RISCV64_DEBUG_CALL
10925 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
10926 #endif
10927 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
10928 "{\n"
10929  "((RISCV64*)cpu)->RES = 0;\n"
10930  #if RISCV64_DEBUG_CALL
10931  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
10932  #endif
10933 "}\n"
10934 
10935 
10936  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
10937 
10938  "return exception;\n"
10939 ;
10940 return true;
10941 },
10942 0,
10943 nullptr
10944 );
10945 //-------------------------------------------------------------------------------------------------------------------
10946 static InstructionDefinition amoor_d_rd_rs1_rs2_aqu_aq_rel_rl_(
10947  ISA32_RISCV64,
10948  "amoor.d",
10949  (uint32_t)0x4000302f,
10950  (uint32_t) 0xf800707f,
10951  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
10952  {
10953  etiss_uint64 aq = 0;
10954  static BitArrayRange R_aq_0 (26,26);
10955  etiss_uint64 aq_0 = R_aq_0.read(ba);
10956  aq += aq_0;
10957  etiss_uint64 rs2 = 0;
10958  static BitArrayRange R_rs2_0 (24,20);
10959  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
10960  rs2 += rs2_0;
10961  etiss_uint64 rs1 = 0;
10962  static BitArrayRange R_rs1_0 (19,15);
10963  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
10964  rs1 += rs1_0;
10965  etiss_uint64 rd = 0;
10966  static BitArrayRange R_rd_0 (11,7);
10967  etiss_uint64 rd_0 = R_rd_0.read(ba);
10968  rd += rd_0;
10969  etiss_uint64 rl = 0;
10970  static BitArrayRange R_rl_0 (25,25);
10971  etiss_uint64 rl_0 = R_rl_0.read(ba);
10972  rl += rl_0;
10973  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
10974  partInit.getRegisterDependencies().add(reg_name[rs2],64);
10975  partInit.getRegisterDependencies().add(reg_name[rs1],64);
10976  partInit.getAffectedRegisters().add(reg_name[rd],64);
10977  partInit.getAffectedRegisters().add("instructionPointer",64);
10978  partInit.code() = std::string("//amoor.d\n")+
10979  "etiss_uint32 exception = 0;\n"
10980  "etiss_uint32 temp = 0;\n"
10981  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
10982  #if RISCV64_Pipeline1
10983  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10984  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10985  "etiss_uint32 num_stages = 4;\n"
10986  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10987  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10988  #endif
10989  #if RISCV64_Pipeline2
10990  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
10991  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
10992  "etiss_uint32 num_stages = 4;\n"
10993  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
10994  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
10995  #endif
10996 
10997  "etiss_uint64 offs = 0;\n"
10998  "etiss_int64 res = 0;\n"
10999  "etiss_uint64 res2 = 0;\n"
11000 
11001 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11002 #if RISCV64_DEBUG_CALL
11003 "printf(\"offs = %#lx\\n\",offs); \n"
11004 #endif
11005  "etiss_uint64 MEM_offs;\n"
11006 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11007 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
11008 "etiss_int64 cast_0 = MEM_offs; \n"
11009 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
11010 "{\n"
11011  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
11012 "}\n"
11013 "res = (etiss_int64)cast_0;\n"
11014 #if RISCV64_DEBUG_CALL
11015 "printf(\"res = %#lx\\n\",res); \n"
11016 #endif
11017 "if(" + toString(rd) + " != 0)\n"
11018 "{\n"
11019  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
11020  #if RISCV64_DEBUG_CALL
11021  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11022  #endif
11023 "}\n"
11024 
11025 "res2 = (res | *((RISCV64*)cpu)->X[" + toString(rs2) + "]);\n"
11026 #if RISCV64_DEBUG_CALL
11027 "printf(\"res2 = %#lx\\n\",res2); \n"
11028 #endif
11029  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11030 "MEM_offs = res2;\n"
11031 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
11032 #if RISCV64_DEBUG_CALL
11033 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11034 #endif
11035 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11036 "{\n"
11037  "((RISCV64*)cpu)->RES = 0;\n"
11038  #if RISCV64_DEBUG_CALL
11039  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11040  #endif
11041 "}\n"
11042 
11043 
11044  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11045 
11046  "return exception;\n"
11047 ;
11048 return true;
11049 },
11050 0,
11051 nullptr
11052 );
11053 //-------------------------------------------------------------------------------------------------------------------
11054 static InstructionDefinition amomin_w_rd_rs1_rs2_aqu_aq_rel_rl_(
11055  ISA32_RISCV64,
11056  "amomin.w",
11057  (uint32_t)0x8000202f,
11058  (uint32_t) 0xf800707f,
11059  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11060  {
11061  etiss_uint64 aq = 0;
11062  static BitArrayRange R_aq_0 (26,26);
11063  etiss_uint64 aq_0 = R_aq_0.read(ba);
11064  aq += aq_0;
11065  etiss_uint64 rs2 = 0;
11066  static BitArrayRange R_rs2_0 (24,20);
11067  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11068  rs2 += rs2_0;
11069  etiss_uint64 rs1 = 0;
11070  static BitArrayRange R_rs1_0 (19,15);
11071  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11072  rs1 += rs1_0;
11073  etiss_uint64 rd = 0;
11074  static BitArrayRange R_rd_0 (11,7);
11075  etiss_uint64 rd_0 = R_rd_0.read(ba);
11076  rd += rd_0;
11077  etiss_uint64 rl = 0;
11078  static BitArrayRange R_rl_0 (25,25);
11079  etiss_uint64 rl_0 = R_rl_0.read(ba);
11080  rl += rl_0;
11081  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11082  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11083  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11084  partInit.getAffectedRegisters().add(reg_name[rd],64);
11085  partInit.getAffectedRegisters().add("instructionPointer",64);
11086  partInit.code() = std::string("//amomin.w\n")+
11087  "etiss_uint32 exception = 0;\n"
11088  "etiss_uint32 temp = 0;\n"
11089  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11090  #if RISCV64_Pipeline1
11091  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11092  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11093  "etiss_uint32 num_stages = 4;\n"
11094  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11095  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11096  #endif
11097  #if RISCV64_Pipeline2
11098  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11099  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11100  "etiss_uint32 num_stages = 4;\n"
11101  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11102  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11103  #endif
11104 
11105  "etiss_uint64 offs = 0;\n"
11106  "etiss_int64 res1 = 0;\n"
11107  "etiss_uint64 res2 = 0;\n"
11108  "etiss_uint64 choose1 = 0;\n"
11109 
11110 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11111 #if RISCV64_DEBUG_CALL
11112 "printf(\"offs = %#lx\\n\",offs); \n"
11113 #endif
11114  "etiss_uint32 MEM_offs;\n"
11115 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11116 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
11117 "etiss_int32 cast_0 = MEM_offs; \n"
11118 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
11119 "{\n"
11120  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
11121 "}\n"
11122 "res1 = (etiss_int64)cast_0;\n"
11123 #if RISCV64_DEBUG_CALL
11124 "printf(\"res1 = %#lx\\n\",res1); \n"
11125 #endif
11126 "if(" + toString(rd) + " != 0)\n"
11127 "{\n"
11128  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
11129  #if RISCV64_DEBUG_CALL
11130  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11131  #endif
11132 "}\n"
11133 
11134 "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
11135 "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
11136 "{\n"
11137  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
11138 "}\n"
11139 "etiss_int64 cast_2 = res1; \n"
11140 "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
11141 "{\n"
11142  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
11143 "}\n"
11144 "if((etiss_int64)cast_2 > (etiss_int64)cast_1)\n"
11145 "{\n"
11146  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11147  #if RISCV64_DEBUG_CALL
11148  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11149  #endif
11150 "}\n"
11151 
11152 "else\n"
11153 "{\n"
11154  "choose1 = res1;\n"
11155  #if RISCV64_DEBUG_CALL
11156  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11157  #endif
11158 "}\n"
11159 "res2 = choose1;\n"
11160 #if RISCV64_DEBUG_CALL
11161 "printf(\"res2 = %#lx\\n\",res2); \n"
11162 #endif
11163  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11164 "MEM_offs = res2;\n"
11165 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
11166 #if RISCV64_DEBUG_CALL
11167 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11168 #endif
11169 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11170 "{\n"
11171  "((RISCV64*)cpu)->RES = 0;\n"
11172  #if RISCV64_DEBUG_CALL
11173  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11174  #endif
11175 "}\n"
11176 
11177 
11178  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11179 
11180  "return exception;\n"
11181 ;
11182 return true;
11183 },
11184 0,
11185 nullptr
11186 );
11187 //-------------------------------------------------------------------------------------------------------------------
11188 static InstructionDefinition amomin_d_rd_rs1_rs2_aqu_aq_rel_rl_(
11189  ISA32_RISCV64,
11190  "amomin.d",
11191  (uint32_t)0x8000302f,
11192  (uint32_t) 0xf800707f,
11193  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11194  {
11195  etiss_uint64 aq = 0;
11196  static BitArrayRange R_aq_0 (26,26);
11197  etiss_uint64 aq_0 = R_aq_0.read(ba);
11198  aq += aq_0;
11199  etiss_uint64 rs2 = 0;
11200  static BitArrayRange R_rs2_0 (24,20);
11201  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11202  rs2 += rs2_0;
11203  etiss_uint64 rs1 = 0;
11204  static BitArrayRange R_rs1_0 (19,15);
11205  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11206  rs1 += rs1_0;
11207  etiss_uint64 rd = 0;
11208  static BitArrayRange R_rd_0 (11,7);
11209  etiss_uint64 rd_0 = R_rd_0.read(ba);
11210  rd += rd_0;
11211  etiss_uint64 rl = 0;
11212  static BitArrayRange R_rl_0 (25,25);
11213  etiss_uint64 rl_0 = R_rl_0.read(ba);
11214  rl += rl_0;
11215  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11216  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11217  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11218  partInit.getAffectedRegisters().add(reg_name[rd],64);
11219  partInit.getAffectedRegisters().add("instructionPointer",64);
11220  partInit.code() = std::string("//amomin.d\n")+
11221  "etiss_uint32 exception = 0;\n"
11222  "etiss_uint32 temp = 0;\n"
11223  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11224  #if RISCV64_Pipeline1
11225  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11226  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11227  "etiss_uint32 num_stages = 4;\n"
11228  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11229  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11230  #endif
11231  #if RISCV64_Pipeline2
11232  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11233  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11234  "etiss_uint32 num_stages = 4;\n"
11235  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11236  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11237  #endif
11238 
11239  "etiss_uint64 offs = 0;\n"
11240  "etiss_int64 res1 = 0;\n"
11241  "etiss_uint64 res2 = 0;\n"
11242  "etiss_uint64 choose1 = 0;\n"
11243 
11244 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11245 #if RISCV64_DEBUG_CALL
11246 "printf(\"offs = %#lx\\n\",offs); \n"
11247 #endif
11248  "etiss_uint64 MEM_offs;\n"
11249 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11250 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
11251 "etiss_int64 cast_0 = MEM_offs; \n"
11252 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
11253 "{\n"
11254  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
11255 "}\n"
11256 "res1 = (etiss_int64)cast_0;\n"
11257 #if RISCV64_DEBUG_CALL
11258 "printf(\"res1 = %#lx\\n\",res1); \n"
11259 #endif
11260 "if(" + toString(rd) + " != 0)\n"
11261 "{\n"
11262  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
11263  #if RISCV64_DEBUG_CALL
11264  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11265  #endif
11266 "}\n"
11267 
11268 "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
11269 "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
11270 "{\n"
11271  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
11272 "}\n"
11273 "etiss_int64 cast_2 = res1; \n"
11274 "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
11275 "{\n"
11276  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
11277 "}\n"
11278 "if((etiss_int64)cast_2 > (etiss_int64)cast_1)\n"
11279 "{\n"
11280  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11281  #if RISCV64_DEBUG_CALL
11282  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11283  #endif
11284 "}\n"
11285 
11286 "else\n"
11287 "{\n"
11288  "choose1 = res1;\n"
11289  #if RISCV64_DEBUG_CALL
11290  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11291  #endif
11292 "}\n"
11293 "res2 = choose1;\n"
11294 #if RISCV64_DEBUG_CALL
11295 "printf(\"res2 = %#lx\\n\",res2); \n"
11296 #endif
11297  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11298 "MEM_offs = res2;\n"
11299 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
11300 #if RISCV64_DEBUG_CALL
11301 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11302 #endif
11303 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11304 "{\n"
11305  "((RISCV64*)cpu)->RES = 0;\n"
11306  #if RISCV64_DEBUG_CALL
11307  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11308  #endif
11309 "}\n"
11310 
11311 
11312  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11313 
11314  "return exception;\n"
11315 ;
11316 return true;
11317 },
11318 0,
11319 nullptr
11320 );
11321 //-------------------------------------------------------------------------------------------------------------------
11322 static InstructionDefinition amomax_w_rd_rs1_rs2_aqu_aq_rel_rl_(
11323  ISA32_RISCV64,
11324  "amomax.w",
11325  (uint32_t)0xa000202f,
11326  (uint32_t) 0xf800707f,
11327  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11328  {
11329  etiss_uint64 aq = 0;
11330  static BitArrayRange R_aq_0 (26,26);
11331  etiss_uint64 aq_0 = R_aq_0.read(ba);
11332  aq += aq_0;
11333  etiss_uint64 rs2 = 0;
11334  static BitArrayRange R_rs2_0 (24,20);
11335  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11336  rs2 += rs2_0;
11337  etiss_uint64 rs1 = 0;
11338  static BitArrayRange R_rs1_0 (19,15);
11339  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11340  rs1 += rs1_0;
11341  etiss_uint64 rd = 0;
11342  static BitArrayRange R_rd_0 (11,7);
11343  etiss_uint64 rd_0 = R_rd_0.read(ba);
11344  rd += rd_0;
11345  etiss_uint64 rl = 0;
11346  static BitArrayRange R_rl_0 (25,25);
11347  etiss_uint64 rl_0 = R_rl_0.read(ba);
11348  rl += rl_0;
11349  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11350  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11351  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11352  partInit.getAffectedRegisters().add(reg_name[rd],64);
11353  partInit.getAffectedRegisters().add("instructionPointer",64);
11354  partInit.code() = std::string("//amomax.w\n")+
11355  "etiss_uint32 exception = 0;\n"
11356  "etiss_uint32 temp = 0;\n"
11357  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11358  #if RISCV64_Pipeline1
11359  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11360  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11361  "etiss_uint32 num_stages = 4;\n"
11362  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11363  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11364  #endif
11365  #if RISCV64_Pipeline2
11366  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11367  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11368  "etiss_uint32 num_stages = 4;\n"
11369  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11370  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11371  #endif
11372 
11373  "etiss_uint64 offs = 0;\n"
11374  "etiss_int64 res1 = 0;\n"
11375  "etiss_uint64 res2 = 0;\n"
11376  "etiss_uint64 choose1 = 0;\n"
11377 
11378 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11379 #if RISCV64_DEBUG_CALL
11380 "printf(\"offs = %#lx\\n\",offs); \n"
11381 #endif
11382  "etiss_uint32 MEM_offs;\n"
11383 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11384 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
11385 "etiss_int32 cast_0 = MEM_offs; \n"
11386 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
11387 "{\n"
11388  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
11389 "}\n"
11390 "res1 = (etiss_int64)cast_0;\n"
11391 #if RISCV64_DEBUG_CALL
11392 "printf(\"res1 = %#lx\\n\",res1); \n"
11393 #endif
11394 "if(" + toString(rd) + " != 0)\n"
11395 "{\n"
11396  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
11397  #if RISCV64_DEBUG_CALL
11398  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11399  #endif
11400 "}\n"
11401 
11402 "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
11403 "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
11404 "{\n"
11405  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
11406 "}\n"
11407 "etiss_int64 cast_2 = res1; \n"
11408 "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
11409 "{\n"
11410  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
11411 "}\n"
11412 "if((etiss_int64)cast_2 < (etiss_int64)cast_1)\n"
11413 "{\n"
11414  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11415  #if RISCV64_DEBUG_CALL
11416  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11417  #endif
11418 "}\n"
11419 
11420 "else\n"
11421 "{\n"
11422  "choose1 = res1;\n"
11423  #if RISCV64_DEBUG_CALL
11424  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11425  #endif
11426 "}\n"
11427 "res2 = choose1;\n"
11428 #if RISCV64_DEBUG_CALL
11429 "printf(\"res2 = %#lx\\n\",res2); \n"
11430 #endif
11431  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11432 "MEM_offs = res2;\n"
11433 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
11434 #if RISCV64_DEBUG_CALL
11435 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11436 #endif
11437 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11438 "{\n"
11439  "((RISCV64*)cpu)->RES = 0;\n"
11440  #if RISCV64_DEBUG_CALL
11441  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11442  #endif
11443 "}\n"
11444 
11445 
11446  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11447 
11448  "return exception;\n"
11449 ;
11450 return true;
11451 },
11452 0,
11453 nullptr
11454 );
11455 //-------------------------------------------------------------------------------------------------------------------
11456 static InstructionDefinition amomax_d_rd_rs1_rs2_aqu_aq_rel_rl_(
11457  ISA32_RISCV64,
11458  "amomax.d",
11459  (uint32_t)0xa000302f,
11460  (uint32_t) 0xf800707f,
11461  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11462  {
11463  etiss_uint64 aq = 0;
11464  static BitArrayRange R_aq_0 (26,26);
11465  etiss_uint64 aq_0 = R_aq_0.read(ba);
11466  aq += aq_0;
11467  etiss_uint64 rs2 = 0;
11468  static BitArrayRange R_rs2_0 (24,20);
11469  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11470  rs2 += rs2_0;
11471  etiss_uint64 rs1 = 0;
11472  static BitArrayRange R_rs1_0 (19,15);
11473  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11474  rs1 += rs1_0;
11475  etiss_uint64 rd = 0;
11476  static BitArrayRange R_rd_0 (11,7);
11477  etiss_uint64 rd_0 = R_rd_0.read(ba);
11478  rd += rd_0;
11479  etiss_uint64 rl = 0;
11480  static BitArrayRange R_rl_0 (25,25);
11481  etiss_uint64 rl_0 = R_rl_0.read(ba);
11482  rl += rl_0;
11483  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11484  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11485  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11486  partInit.getAffectedRegisters().add(reg_name[rd],64);
11487  partInit.getAffectedRegisters().add("instructionPointer",64);
11488  partInit.code() = std::string("//amomax.d\n")+
11489  "etiss_uint32 exception = 0;\n"
11490  "etiss_uint32 temp = 0;\n"
11491  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11492  #if RISCV64_Pipeline1
11493  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11494  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11495  "etiss_uint32 num_stages = 4;\n"
11496  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11497  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11498  #endif
11499  #if RISCV64_Pipeline2
11500  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11501  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11502  "etiss_uint32 num_stages = 4;\n"
11503  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11504  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11505  #endif
11506 
11507  "etiss_uint64 offs = 0;\n"
11508  "etiss_int64 res = 0;\n"
11509  "etiss_uint64 res2 = 0;\n"
11510  "etiss_uint64 choose1 = 0;\n"
11511 
11512 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11513 #if RISCV64_DEBUG_CALL
11514 "printf(\"offs = %#lx\\n\",offs); \n"
11515 #endif
11516  "etiss_uint64 MEM_offs;\n"
11517 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11518 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
11519 "etiss_int64 cast_0 = MEM_offs; \n"
11520 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
11521 "{\n"
11522  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
11523 "}\n"
11524 "res = (etiss_int64)cast_0;\n"
11525 #if RISCV64_DEBUG_CALL
11526 "printf(\"res = %#lx\\n\",res); \n"
11527 #endif
11528 "if(" + toString(rd) + " != 0)\n"
11529 "{\n"
11530  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
11531  #if RISCV64_DEBUG_CALL
11532  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11533  #endif
11534 "}\n"
11535 
11536 "etiss_int64 cast_1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "]; \n"
11537 "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n"
11538 "{\n"
11539  "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n"
11540 "}\n"
11541 "etiss_int64 cast_2 = res; \n"
11542 "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n"
11543 "{\n"
11544  "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n"
11545 "}\n"
11546 "if((etiss_int64)cast_2 < (etiss_int64)cast_1)\n"
11547 "{\n"
11548  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11549  #if RISCV64_DEBUG_CALL
11550  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11551  #endif
11552 "}\n"
11553 
11554 "else\n"
11555 "{\n"
11556  "choose1 = res;\n"
11557  #if RISCV64_DEBUG_CALL
11558  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11559  #endif
11560 "}\n"
11561 "res2 = choose1;\n"
11562 #if RISCV64_DEBUG_CALL
11563 "printf(\"res2 = %#lx\\n\",res2); \n"
11564 #endif
11565  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11566 "MEM_offs = res2;\n"
11567 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
11568 #if RISCV64_DEBUG_CALL
11569 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11570 #endif
11571 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11572 "{\n"
11573  "((RISCV64*)cpu)->RES = 0;\n"
11574  #if RISCV64_DEBUG_CALL
11575  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11576  #endif
11577 "}\n"
11578 
11579 
11580  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11581 
11582  "return exception;\n"
11583 ;
11584 return true;
11585 },
11586 0,
11587 nullptr
11588 );
11589 //-------------------------------------------------------------------------------------------------------------------
11590 static InstructionDefinition amominu_w_rd_rs1_rs2_aqu_aq_rel_rl_(
11591  ISA32_RISCV64,
11592  "amominu.w",
11593  (uint32_t)0xc000202f,
11594  (uint32_t) 0xf800707f,
11595  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11596  {
11597  etiss_uint64 aq = 0;
11598  static BitArrayRange R_aq_0 (26,26);
11599  etiss_uint64 aq_0 = R_aq_0.read(ba);
11600  aq += aq_0;
11601  etiss_uint64 rs2 = 0;
11602  static BitArrayRange R_rs2_0 (24,20);
11603  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11604  rs2 += rs2_0;
11605  etiss_uint64 rs1 = 0;
11606  static BitArrayRange R_rs1_0 (19,15);
11607  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11608  rs1 += rs1_0;
11609  etiss_uint64 rd = 0;
11610  static BitArrayRange R_rd_0 (11,7);
11611  etiss_uint64 rd_0 = R_rd_0.read(ba);
11612  rd += rd_0;
11613  etiss_uint64 rl = 0;
11614  static BitArrayRange R_rl_0 (25,25);
11615  etiss_uint64 rl_0 = R_rl_0.read(ba);
11616  rl += rl_0;
11617  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11618  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11619  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11620  partInit.getAffectedRegisters().add(reg_name[rd],64);
11621  partInit.getAffectedRegisters().add("instructionPointer",64);
11622  partInit.code() = std::string("//amominu.w\n")+
11623  "etiss_uint32 exception = 0;\n"
11624  "etiss_uint32 temp = 0;\n"
11625  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11626  #if RISCV64_Pipeline1
11627  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11628  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11629  "etiss_uint32 num_stages = 4;\n"
11630  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11631  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11632  #endif
11633  #if RISCV64_Pipeline2
11634  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11635  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11636  "etiss_uint32 num_stages = 4;\n"
11637  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11638  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11639  #endif
11640 
11641  "etiss_uint64 offs = 0;\n"
11642  "etiss_int64 res1 = 0;\n"
11643  "etiss_uint64 res2 = 0;\n"
11644  "etiss_uint64 choose1 = 0;\n"
11645 
11646 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11647 #if RISCV64_DEBUG_CALL
11648 "printf(\"offs = %#lx\\n\",offs); \n"
11649 #endif
11650  "etiss_uint32 MEM_offs;\n"
11651 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11652 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
11653 "etiss_int32 cast_0 = MEM_offs; \n"
11654 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
11655 "{\n"
11656  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
11657 "}\n"
11658 "res1 = (etiss_int64)cast_0;\n"
11659 #if RISCV64_DEBUG_CALL
11660 "printf(\"res1 = %#lx\\n\",res1); \n"
11661 #endif
11662 "if(" + toString(rd) + " != 0)\n"
11663 "{\n"
11664  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
11665  #if RISCV64_DEBUG_CALL
11666  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11667  #endif
11668 "}\n"
11669 
11670 "if(res1 > *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
11671 "{\n"
11672  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11673  #if RISCV64_DEBUG_CALL
11674  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11675  #endif
11676 "}\n"
11677 
11678 "else\n"
11679 "{\n"
11680  "choose1 = res1;\n"
11681  #if RISCV64_DEBUG_CALL
11682  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11683  #endif
11684 "}\n"
11685 "res2 = choose1;\n"
11686 #if RISCV64_DEBUG_CALL
11687 "printf(\"res2 = %#lx\\n\",res2); \n"
11688 #endif
11689  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11690 "MEM_offs = res2;\n"
11691 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
11692 #if RISCV64_DEBUG_CALL
11693 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11694 #endif
11695 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11696 "{\n"
11697  "((RISCV64*)cpu)->RES = 0;\n"
11698  #if RISCV64_DEBUG_CALL
11699  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11700  #endif
11701 "}\n"
11702 
11703 
11704  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11705 
11706  "return exception;\n"
11707 ;
11708 return true;
11709 },
11710 0,
11711 nullptr
11712 );
11713 //-------------------------------------------------------------------------------------------------------------------
11714 static InstructionDefinition amominu_d_rd_rs1_rs2_aqu_aq_rel_rl_(
11715  ISA32_RISCV64,
11716  "amominu.d",
11717  (uint32_t)0xc000302f,
11718  (uint32_t) 0xf800707f,
11719  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11720  {
11721  etiss_uint64 aq = 0;
11722  static BitArrayRange R_aq_0 (26,26);
11723  etiss_uint64 aq_0 = R_aq_0.read(ba);
11724  aq += aq_0;
11725  etiss_uint64 rs2 = 0;
11726  static BitArrayRange R_rs2_0 (24,20);
11727  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11728  rs2 += rs2_0;
11729  etiss_uint64 rs1 = 0;
11730  static BitArrayRange R_rs1_0 (19,15);
11731  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11732  rs1 += rs1_0;
11733  etiss_uint64 rd = 0;
11734  static BitArrayRange R_rd_0 (11,7);
11735  etiss_uint64 rd_0 = R_rd_0.read(ba);
11736  rd += rd_0;
11737  etiss_uint64 rl = 0;
11738  static BitArrayRange R_rl_0 (25,25);
11739  etiss_uint64 rl_0 = R_rl_0.read(ba);
11740  rl += rl_0;
11741  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11742  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11743  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11744  partInit.getAffectedRegisters().add(reg_name[rd],64);
11745  partInit.getAffectedRegisters().add("instructionPointer",64);
11746  partInit.code() = std::string("//amominu.d\n")+
11747  "etiss_uint32 exception = 0;\n"
11748  "etiss_uint32 temp = 0;\n"
11749  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11750  #if RISCV64_Pipeline1
11751  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11752  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11753  "etiss_uint32 num_stages = 4;\n"
11754  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11755  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11756  #endif
11757  #if RISCV64_Pipeline2
11758  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11759  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11760  "etiss_uint32 num_stages = 4;\n"
11761  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11762  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11763  #endif
11764 
11765  "etiss_uint64 offs = 0;\n"
11766  "etiss_int64 res = 0;\n"
11767  "etiss_uint64 res2 = 0;\n"
11768  "etiss_uint64 choose1 = 0;\n"
11769 
11770 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11771 #if RISCV64_DEBUG_CALL
11772 "printf(\"offs = %#lx\\n\",offs); \n"
11773 #endif
11774  "etiss_uint64 MEM_offs;\n"
11775 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11776 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
11777 "etiss_int64 cast_0 = MEM_offs; \n"
11778 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
11779 "{\n"
11780  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
11781 "}\n"
11782 "res = (etiss_int64)cast_0;\n"
11783 #if RISCV64_DEBUG_CALL
11784 "printf(\"res = %#lx\\n\",res); \n"
11785 #endif
11786 "if(" + toString(rd) + " != 0)\n"
11787 "{\n"
11788  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res;\n"
11789  #if RISCV64_DEBUG_CALL
11790  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11791  #endif
11792 "}\n"
11793 
11794 "if(res > *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
11795 "{\n"
11796  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11797  #if RISCV64_DEBUG_CALL
11798  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11799  #endif
11800 "}\n"
11801 
11802 "else\n"
11803 "{\n"
11804  "choose1 = res;\n"
11805  #if RISCV64_DEBUG_CALL
11806  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11807  #endif
11808 "}\n"
11809 "res2 = choose1;\n"
11810 #if RISCV64_DEBUG_CALL
11811 "printf(\"res2 = %#lx\\n\",res2); \n"
11812 #endif
11813  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11814 "MEM_offs = res2;\n"
11815 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
11816 #if RISCV64_DEBUG_CALL
11817 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11818 #endif
11819 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11820 "{\n"
11821  "((RISCV64*)cpu)->RES = 0;\n"
11822  #if RISCV64_DEBUG_CALL
11823  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11824  #endif
11825 "}\n"
11826 
11827 
11828  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11829 
11830  "return exception;\n"
11831 ;
11832 return true;
11833 },
11834 0,
11835 nullptr
11836 );
11837 //-------------------------------------------------------------------------------------------------------------------
11838 static InstructionDefinition amomaxu_w_rd_rs1_rs2_aqu_aq_rel_rl_(
11839  ISA32_RISCV64,
11840  "amomaxu.w",
11841  (uint32_t)0xe000202f,
11842  (uint32_t) 0xf800707f,
11843  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11844  {
11845  etiss_uint64 aq = 0;
11846  static BitArrayRange R_aq_0 (26,26);
11847  etiss_uint64 aq_0 = R_aq_0.read(ba);
11848  aq += aq_0;
11849  etiss_uint64 rs2 = 0;
11850  static BitArrayRange R_rs2_0 (24,20);
11851  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11852  rs2 += rs2_0;
11853  etiss_uint64 rs1 = 0;
11854  static BitArrayRange R_rs1_0 (19,15);
11855  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11856  rs1 += rs1_0;
11857  etiss_uint64 rd = 0;
11858  static BitArrayRange R_rd_0 (11,7);
11859  etiss_uint64 rd_0 = R_rd_0.read(ba);
11860  rd += rd_0;
11861  etiss_uint64 rl = 0;
11862  static BitArrayRange R_rl_0 (25,25);
11863  etiss_uint64 rl_0 = R_rl_0.read(ba);
11864  rl += rl_0;
11865  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11866  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11867  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11868  partInit.getAffectedRegisters().add(reg_name[rd],64);
11869  partInit.getAffectedRegisters().add("instructionPointer",64);
11870  partInit.code() = std::string("//amomaxu.w\n")+
11871  "etiss_uint32 exception = 0;\n"
11872  "etiss_uint32 temp = 0;\n"
11873  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11874  #if RISCV64_Pipeline1
11875  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11876  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11877  "etiss_uint32 num_stages = 4;\n"
11878  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11879  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11880  #endif
11881  #if RISCV64_Pipeline2
11882  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
11883  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
11884  "etiss_uint32 num_stages = 4;\n"
11885  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
11886  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
11887  #endif
11888 
11889  "etiss_uint64 offs = 0;\n"
11890  "etiss_int64 res1 = 0;\n"
11891  "etiss_uint64 res2 = 0;\n"
11892  "etiss_uint64 choose1 = 0;\n"
11893 
11894 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
11895 #if RISCV64_DEBUG_CALL
11896 "printf(\"offs = %#lx\\n\",offs); \n"
11897 #endif
11898  "etiss_uint32 MEM_offs;\n"
11899 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11900 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
11901 "etiss_int32 cast_0 = MEM_offs; \n"
11902 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
11903 "{\n"
11904  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
11905 "}\n"
11906 "res1 = (etiss_int64)cast_0;\n"
11907 #if RISCV64_DEBUG_CALL
11908 "printf(\"res1 = %#lx\\n\",res1); \n"
11909 #endif
11910 "if(" + toString(rd) + " != 0)\n"
11911 "{\n"
11912  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
11913  #if RISCV64_DEBUG_CALL
11914  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
11915  #endif
11916 "}\n"
11917 
11918 "if(res1 < *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
11919 "{\n"
11920  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
11921  #if RISCV64_DEBUG_CALL
11922  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11923  #endif
11924 "}\n"
11925 
11926 "else\n"
11927 "{\n"
11928  "choose1 = res1;\n"
11929  #if RISCV64_DEBUG_CALL
11930  "printf(\"choose1 = %#lx\\n\",choose1); \n"
11931  #endif
11932 "}\n"
11933 "res2 = choose1;\n"
11934 #if RISCV64_DEBUG_CALL
11935 "printf(\"res2 = %#lx\\n\",res2); \n"
11936 #endif
11937  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
11938 "MEM_offs = res2;\n"
11939 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
11940 #if RISCV64_DEBUG_CALL
11941 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
11942 #endif
11943 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
11944 "{\n"
11945  "((RISCV64*)cpu)->RES = 0;\n"
11946  #if RISCV64_DEBUG_CALL
11947  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
11948  #endif
11949 "}\n"
11950 
11951 
11952  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
11953 
11954  "return exception;\n"
11955 ;
11956 return true;
11957 },
11958 0,
11959 nullptr
11960 );
11961 //-------------------------------------------------------------------------------------------------------------------
11962 static InstructionDefinition amomaxu_d_rd_rs1_rs2_aqu_aq_rel_rl_(
11963  ISA32_RISCV64,
11964  "amomaxu.d",
11965  (uint32_t)0xe000302f,
11966  (uint32_t) 0xf800707f,
11967  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
11968  {
11969  etiss_uint64 aq = 0;
11970  static BitArrayRange R_aq_0 (26,26);
11971  etiss_uint64 aq_0 = R_aq_0.read(ba);
11972  aq += aq_0;
11973  etiss_uint64 rs2 = 0;
11974  static BitArrayRange R_rs2_0 (24,20);
11975  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
11976  rs2 += rs2_0;
11977  etiss_uint64 rs1 = 0;
11978  static BitArrayRange R_rs1_0 (19,15);
11979  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
11980  rs1 += rs1_0;
11981  etiss_uint64 rd = 0;
11982  static BitArrayRange R_rd_0 (11,7);
11983  etiss_uint64 rd_0 = R_rd_0.read(ba);
11984  rd += rd_0;
11985  etiss_uint64 rl = 0;
11986  static BitArrayRange R_rl_0 (25,25);
11987  etiss_uint64 rl_0 = R_rl_0.read(ba);
11988  rl += rl_0;
11989  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
11990  partInit.getRegisterDependencies().add(reg_name[rs2],64);
11991  partInit.getRegisterDependencies().add(reg_name[rs1],64);
11992  partInit.getAffectedRegisters().add(reg_name[rd],64);
11993  partInit.getAffectedRegisters().add("instructionPointer",64);
11994  partInit.code() = std::string("//amomaxu.d\n")+
11995  "etiss_uint32 exception = 0;\n"
11996  "etiss_uint32 temp = 0;\n"
11997  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
11998  #if RISCV64_Pipeline1
11999  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12000  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12001  "etiss_uint32 num_stages = 4;\n"
12002  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12003  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12004  #endif
12005  #if RISCV64_Pipeline2
12006  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12007  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12008  "etiss_uint32 num_stages = 4;\n"
12009  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12010  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12011  #endif
12012 
12013  "etiss_uint64 offs = 0;\n"
12014  "etiss_int64 res1 = 0;\n"
12015  "etiss_uint64 res2 = 0;\n"
12016  "etiss_uint64 choose1 = 0;\n"
12017 
12018 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
12019 #if RISCV64_DEBUG_CALL
12020 "printf(\"offs = %#lx\\n\",offs); \n"
12021 #endif
12022  "etiss_uint64 MEM_offs;\n"
12023 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
12024 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
12025 "etiss_int64 cast_0 = MEM_offs; \n"
12026 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
12027 "{\n"
12028  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
12029 "}\n"
12030 "res1 = (etiss_int64)cast_0;\n"
12031 #if RISCV64_DEBUG_CALL
12032 "printf(\"res1 = %#lx\\n\",res1); \n"
12033 #endif
12034 "if(" + toString(rd) + " != 0)\n"
12035 "{\n"
12036  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = res1;\n"
12037  #if RISCV64_DEBUG_CALL
12038  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
12039  #endif
12040 "}\n"
12041 
12042 "if(res1 < *((RISCV64*)cpu)->X[" + toString(rs2) + "])\n"
12043 "{\n"
12044  "choose1 = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
12045  #if RISCV64_DEBUG_CALL
12046  "printf(\"choose1 = %#lx\\n\",choose1); \n"
12047  #endif
12048 "}\n"
12049 
12050 "else\n"
12051 "{\n"
12052  "choose1 = res1;\n"
12053  #if RISCV64_DEBUG_CALL
12054  "printf(\"choose1 = %#lx\\n\",choose1); \n"
12055  #endif
12056 "}\n"
12057 "res2 = choose1;\n"
12058 #if RISCV64_DEBUG_CALL
12059 "printf(\"res2 = %#lx\\n\",res2); \n"
12060 #endif
12061  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
12062 "MEM_offs = res2;\n"
12063 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
12064 #if RISCV64_DEBUG_CALL
12065 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
12066 #endif
12067 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
12068 "{\n"
12069  "((RISCV64*)cpu)->RES = 0;\n"
12070  #if RISCV64_DEBUG_CALL
12071  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
12072  #endif
12073 "}\n"
12074 
12075 
12076  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12077 
12078  "return exception;\n"
12079 ;
12080 return true;
12081 },
12082 0,
12083 nullptr
12084 );
12085 //-------------------------------------------------------------------------------------------------------------------
12086 static InstructionDefinition fsub_s_rd_frs1_frs2(
12087  ISA32_RISCV64,
12088  "fsub.s",
12089  (uint32_t)0x8000053,
12090  (uint32_t) 0xfe00007f,
12091  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12092  {
12093  etiss_uint64 rs2 = 0;
12094  static BitArrayRange R_rs2_0 (24,20);
12095  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12096  rs2 += rs2_0;
12097  etiss_uint64 rs1 = 0;
12098  static BitArrayRange R_rs1_0 (19,15);
12099  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12100  rs1 += rs1_0;
12101  etiss_uint64 rd = 0;
12102  static BitArrayRange R_rd_0 (11,7);
12103  etiss_uint64 rd_0 = R_rd_0.read(ba);
12104  rd += rd_0;
12105  etiss_uint64 rm = 0;
12106  static BitArrayRange R_rm_0 (14,12);
12107  etiss_uint64 rm_0 = R_rm_0.read(ba);
12108  rm += rm_0;
12109  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12110  partInit.getAffectedRegisters().add(reg_name[rd],64);
12111  partInit.getAffectedRegisters().add("instructionPointer",64);
12112  partInit.code() = std::string("//fsub.s\n")+
12113  "etiss_uint32 temp = 0;\n"
12114  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12115  #if RISCV64_Pipeline1
12116  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12117  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12118  "etiss_uint32 num_stages = 4;\n"
12119  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12120  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12121  #endif
12122  #if RISCV64_Pipeline2
12123  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12124  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12125  "etiss_uint32 num_stages = 4;\n"
12126  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12127  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12128  #endif
12129 
12130  "etiss_uint32 res = 0;\n"
12131  "etiss_int64 upper = 0;\n"
12132  "etiss_uint32 flags = 0;\n"
12133  "etiss_uint32 frs1 = 0;\n"
12134  "etiss_uint32 choose1 = 0;\n"
12135  "etiss_uint32 frs2 = 0;\n"
12136 
12137 "if(64 == 32)\n"
12138 "{\n"
12139  "if(" + toString(rm) + " < 7)\n"
12140  "{\n"
12141  "choose1 = (" + toString(rm) + " & 0xff);\n"
12142  #if RISCV64_DEBUG_CALL
12143  "printf(\"choose1 = %#x\\n\",choose1); \n"
12144  #endif
12145  "}\n"
12146 
12147  "else\n"
12148  "{\n"
12149  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
12150  #if RISCV64_DEBUG_CALL
12151  "printf(\"choose1 = %#x\\n\",choose1); \n"
12152  #endif
12153  "}\n"
12154  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fsub_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], choose1);\n"
12155  #if RISCV64_DEBUG_CALL
12156  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12157  #endif
12158 "}\n"
12159 
12160 "else\n"
12161 "{\n"
12162  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12163  #if RISCV64_DEBUG_CALL
12164  "printf(\"frs1 = %#x\\n\",frs1); \n"
12165  #endif
12166  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12167  #if RISCV64_DEBUG_CALL
12168  "printf(\"frs2 = %#x\\n\",frs2); \n"
12169  #endif
12170  "if(" + toString(rm) + " < 7)\n"
12171  "{\n"
12172  "choose1 = (" + toString(rm) + " & 0xff);\n"
12173  #if RISCV64_DEBUG_CALL
12174  "printf(\"choose1 = %#x\\n\",choose1); \n"
12175  #endif
12176  "}\n"
12177 
12178  "else\n"
12179  "{\n"
12180  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
12181  #if RISCV64_DEBUG_CALL
12182  "printf(\"choose1 = %#x\\n\",choose1); \n"
12183  #endif
12184  "}\n"
12185  "res = fsub_s(frs1, frs2, choose1);\n"
12186  #if RISCV64_DEBUG_CALL
12187  "printf(\"res = %#x\\n\",res); \n"
12188  #endif
12189  "upper = - 1;\n"
12190  #if RISCV64_DEBUG_CALL
12191  "printf(\"upper = %#lx\\n\",upper); \n"
12192  #endif
12193  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12194  #if RISCV64_DEBUG_CALL
12195  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12196  #endif
12197 "}\n"
12198 "flags = fget_flags();\n"
12199 #if RISCV64_DEBUG_CALL
12200 "printf(\"flags = %#x\\n\",flags); \n"
12201 #endif
12202 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
12203 #if RISCV64_DEBUG_CALL
12204 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
12205 #endif
12206 
12207  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12208 
12209 ;
12210 return true;
12211 },
12212 0,
12213 nullptr
12214 );
12215 //-------------------------------------------------------------------------------------------------------------------
12216 static InstructionDefinition fdiv_s_rd_frs1_frs2(
12217  ISA32_RISCV64,
12218  "fdiv.s",
12219  (uint32_t)0x18000053,
12220  (uint32_t) 0xfe00007f,
12221  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12222  {
12223  etiss_uint64 rs2 = 0;
12224  static BitArrayRange R_rs2_0 (24,20);
12225  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12226  rs2 += rs2_0;
12227  etiss_uint64 rs1 = 0;
12228  static BitArrayRange R_rs1_0 (19,15);
12229  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12230  rs1 += rs1_0;
12231  etiss_uint64 rd = 0;
12232  static BitArrayRange R_rd_0 (11,7);
12233  etiss_uint64 rd_0 = R_rd_0.read(ba);
12234  rd += rd_0;
12235  etiss_uint64 rm = 0;
12236  static BitArrayRange R_rm_0 (14,12);
12237  etiss_uint64 rm_0 = R_rm_0.read(ba);
12238  rm += rm_0;
12239  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12240  partInit.getAffectedRegisters().add(reg_name[rd],64);
12241  partInit.getAffectedRegisters().add("instructionPointer",64);
12242  partInit.code() = std::string("//fdiv.s\n")+
12243  "etiss_uint32 temp = 0;\n"
12244  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12245  #if RISCV64_Pipeline1
12246  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12247  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12248  "etiss_uint32 num_stages = 4;\n"
12249  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12250  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12251  #endif
12252  #if RISCV64_Pipeline2
12253  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12254  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12255  "etiss_uint32 num_stages = 4;\n"
12256  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12257  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12258  #endif
12259 
12260  "etiss_uint32 res = 0;\n"
12261  "etiss_int64 upper = 0;\n"
12262  "etiss_uint32 flags = 0;\n"
12263  "etiss_uint32 frs1 = 0;\n"
12264  "etiss_uint32 choose1 = 0;\n"
12265  "etiss_uint32 frs2 = 0;\n"
12266 
12267 "if(64 == 32)\n"
12268 "{\n"
12269  "if(" + toString(rm) + " < 7)\n"
12270  "{\n"
12271  "choose1 = (" + toString(rm) + " & 0xff);\n"
12272  #if RISCV64_DEBUG_CALL
12273  "printf(\"choose1 = %#x\\n\",choose1); \n"
12274  #endif
12275  "}\n"
12276 
12277  "else\n"
12278  "{\n"
12279  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
12280  #if RISCV64_DEBUG_CALL
12281  "printf(\"choose1 = %#x\\n\",choose1); \n"
12282  #endif
12283  "}\n"
12284  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fdiv_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], choose1);\n"
12285  #if RISCV64_DEBUG_CALL
12286  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12287  #endif
12288 "}\n"
12289 
12290 "else\n"
12291 "{\n"
12292  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12293  #if RISCV64_DEBUG_CALL
12294  "printf(\"frs1 = %#x\\n\",frs1); \n"
12295  #endif
12296  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12297  #if RISCV64_DEBUG_CALL
12298  "printf(\"frs2 = %#x\\n\",frs2); \n"
12299  #endif
12300  "if(" + toString(rm) + " < 7)\n"
12301  "{\n"
12302  "choose1 = (" + toString(rm) + " & 0xff);\n"
12303  #if RISCV64_DEBUG_CALL
12304  "printf(\"choose1 = %#x\\n\",choose1); \n"
12305  #endif
12306  "}\n"
12307 
12308  "else\n"
12309  "{\n"
12310  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
12311  #if RISCV64_DEBUG_CALL
12312  "printf(\"choose1 = %#x\\n\",choose1); \n"
12313  #endif
12314  "}\n"
12315  "res = fdiv_s(frs1, frs2, choose1);\n"
12316  #if RISCV64_DEBUG_CALL
12317  "printf(\"res = %#x\\n\",res); \n"
12318  #endif
12319  "upper = - 1;\n"
12320  #if RISCV64_DEBUG_CALL
12321  "printf(\"upper = %#lx\\n\",upper); \n"
12322  #endif
12323  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12324  #if RISCV64_DEBUG_CALL
12325  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12326  #endif
12327 "}\n"
12328 "flags = fget_flags();\n"
12329 #if RISCV64_DEBUG_CALL
12330 "printf(\"flags = %#x\\n\",flags); \n"
12331 #endif
12332 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
12333 #if RISCV64_DEBUG_CALL
12334 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
12335 #endif
12336 
12337  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12338 
12339 ;
12340 return true;
12341 },
12342 0,
12343 nullptr
12344 );
12345 //-------------------------------------------------------------------------------------------------------------------
12346 static InstructionDefinition fsqrt_s_rd_frs1(
12347  ISA32_RISCV64,
12348  "fsqrt.s",
12349  (uint32_t)0x58000053,
12350  (uint32_t) 0xfff0007f,
12351  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12352  {
12353  etiss_uint64 rs1 = 0;
12354  static BitArrayRange R_rs1_0 (19,15);
12355  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12356  rs1 += rs1_0;
12357  etiss_uint64 rd = 0;
12358  static BitArrayRange R_rd_0 (11,7);
12359  etiss_uint64 rd_0 = R_rd_0.read(ba);
12360  rd += rd_0;
12361  etiss_uint64 rm = 0;
12362  static BitArrayRange R_rm_0 (14,12);
12363  etiss_uint64 rm_0 = R_rm_0.read(ba);
12364  rm += rm_0;
12365  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12366  partInit.getAffectedRegisters().add(reg_name[rd],64);
12367  partInit.getAffectedRegisters().add("instructionPointer",64);
12368  partInit.code() = std::string("//fsqrt.s\n")+
12369  "etiss_uint32 temp = 0;\n"
12370  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12371  #if RISCV64_Pipeline1
12372  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12373  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12374  "etiss_uint32 num_stages = 4;\n"
12375  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12376  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12377  #endif
12378  #if RISCV64_Pipeline2
12379  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12380  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12381  "etiss_uint32 num_stages = 4;\n"
12382  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12383  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12384  #endif
12385 
12386  "etiss_uint32 res = 0;\n"
12387  "etiss_int64 upper = 0;\n"
12388  "etiss_uint32 flags = 0;\n"
12389  "etiss_uint32 frs1 = 0;\n"
12390  "etiss_uint32 choose1 = 0;\n"
12391 
12392 "if(64 == 32)\n"
12393 "{\n"
12394  "if(" + toString(rm) + " < 7)\n"
12395  "{\n"
12396  "choose1 = (" + toString(rm) + " & 0xff);\n"
12397  #if RISCV64_DEBUG_CALL
12398  "printf(\"choose1 = %#x\\n\",choose1); \n"
12399  #endif
12400  "}\n"
12401 
12402  "else\n"
12403  "{\n"
12404  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
12405  #if RISCV64_DEBUG_CALL
12406  "printf(\"choose1 = %#x\\n\",choose1); \n"
12407  #endif
12408  "}\n"
12409  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fsqrt_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], choose1);\n"
12410  #if RISCV64_DEBUG_CALL
12411  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12412  #endif
12413 "}\n"
12414 
12415 "else\n"
12416 "{\n"
12417  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12418  #if RISCV64_DEBUG_CALL
12419  "printf(\"frs1 = %#x\\n\",frs1); \n"
12420  #endif
12421  "if(" + toString(rm) + " < 7)\n"
12422  "{\n"
12423  "choose1 = (" + toString(rm) + " & 0xff);\n"
12424  #if RISCV64_DEBUG_CALL
12425  "printf(\"choose1 = %#x\\n\",choose1); \n"
12426  #endif
12427  "}\n"
12428 
12429  "else\n"
12430  "{\n"
12431  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
12432  #if RISCV64_DEBUG_CALL
12433  "printf(\"choose1 = %#x\\n\",choose1); \n"
12434  #endif
12435  "}\n"
12436  "res = fsqrt_s(frs1, choose1);\n"
12437  #if RISCV64_DEBUG_CALL
12438  "printf(\"res = %#x\\n\",res); \n"
12439  #endif
12440  "upper = - 1;\n"
12441  #if RISCV64_DEBUG_CALL
12442  "printf(\"upper = %#lx\\n\",upper); \n"
12443  #endif
12444  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12445  #if RISCV64_DEBUG_CALL
12446  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12447  #endif
12448 "}\n"
12449 "flags = fget_flags();\n"
12450 #if RISCV64_DEBUG_CALL
12451 "printf(\"flags = %#x\\n\",flags); \n"
12452 #endif
12453 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
12454 #if RISCV64_DEBUG_CALL
12455 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
12456 #endif
12457 
12458  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12459 
12460 ;
12461 return true;
12462 },
12463 0,
12464 nullptr
12465 );
12466 //-------------------------------------------------------------------------------------------------------------------
12467 static InstructionDefinition fsgnj_s_rd_frs1_frs2(
12468  ISA32_RISCV64,
12469  "fsgnj.s",
12470  (uint32_t)0x20000053,
12471  (uint32_t) 0xfe00707f,
12472  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12473  {
12474  etiss_uint64 rs2 = 0;
12475  static BitArrayRange R_rs2_0 (24,20);
12476  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12477  rs2 += rs2_0;
12478  etiss_uint64 rs1 = 0;
12479  static BitArrayRange R_rs1_0 (19,15);
12480  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12481  rs1 += rs1_0;
12482  etiss_uint64 rd = 0;
12483  static BitArrayRange R_rd_0 (11,7);
12484  etiss_uint64 rd_0 = R_rd_0.read(ba);
12485  rd += rd_0;
12486  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12487  partInit.getRegisterDependencies().add(reg_name[rs2],64);
12488  partInit.getRegisterDependencies().add(reg_name[rs1],64);
12489  partInit.getAffectedRegisters().add(reg_name[rd],64);
12490  partInit.getAffectedRegisters().add("instructionPointer",64);
12491  partInit.code() = std::string("//fsgnj.s\n")+
12492  "etiss_uint32 temp = 0;\n"
12493  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12494  #if RISCV64_Pipeline1
12495  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12496  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12497  "etiss_uint32 num_stages = 4;\n"
12498  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12499  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12500  #endif
12501  #if RISCV64_Pipeline2
12502  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12503  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12504  "etiss_uint32 num_stages = 4;\n"
12505  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12506  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12507  #endif
12508 
12509  "etiss_uint32 res = 0;\n"
12510  "etiss_int64 upper = 0;\n"
12511  "etiss_uint32 frs1 = 0;\n"
12512  "etiss_uint32 frs2 = 0;\n"
12513 
12514 "if(64 == 32)\n"
12515 "{\n"
12516  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 2147483647) | (((RISCV64*)cpu)->F[" + toString(rs2) + "] & -2147483648));\n"
12517  #if RISCV64_DEBUG_CALL
12518  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12519  #endif
12520 "}\n"
12521 
12522 "else\n"
12523 "{\n"
12524  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12525  #if RISCV64_DEBUG_CALL
12526  "printf(\"frs1 = %#x\\n\",frs1); \n"
12527  #endif
12528  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12529  #if RISCV64_DEBUG_CALL
12530  "printf(\"frs2 = %#x\\n\",frs2); \n"
12531  #endif
12532  "res = ((frs1 & 2147483647) | (frs2 & -2147483648));\n"
12533  #if RISCV64_DEBUG_CALL
12534  "printf(\"res = %#x\\n\",res); \n"
12535  #endif
12536  "upper = - 1;\n"
12537  #if RISCV64_DEBUG_CALL
12538  "printf(\"upper = %#lx\\n\",upper); \n"
12539  #endif
12540  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12541  #if RISCV64_DEBUG_CALL
12542  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12543  #endif
12544 "}\n"
12545 
12546  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12547 
12548 ;
12549 return true;
12550 },
12551 0,
12552 nullptr
12553 );
12554 //-------------------------------------------------------------------------------------------------------------------
12555 static InstructionDefinition fsgnjn_s_rd_frs1_frs2(
12556  ISA32_RISCV64,
12557  "fsgnjn.s",
12558  (uint32_t)0x20001053,
12559  (uint32_t) 0xfe00707f,
12560  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12561  {
12562  etiss_uint64 rs2 = 0;
12563  static BitArrayRange R_rs2_0 (24,20);
12564  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12565  rs2 += rs2_0;
12566  etiss_uint64 rs1 = 0;
12567  static BitArrayRange R_rs1_0 (19,15);
12568  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12569  rs1 += rs1_0;
12570  etiss_uint64 rd = 0;
12571  static BitArrayRange R_rd_0 (11,7);
12572  etiss_uint64 rd_0 = R_rd_0.read(ba);
12573  rd += rd_0;
12574  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12575  partInit.getRegisterDependencies().add(reg_name[rs2],64);
12576  partInit.getRegisterDependencies().add(reg_name[rs1],64);
12577  partInit.getAffectedRegisters().add(reg_name[rd],64);
12578  partInit.getAffectedRegisters().add("instructionPointer",64);
12579  partInit.code() = std::string("//fsgnjn.s\n")+
12580  "etiss_uint32 temp = 0;\n"
12581  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12582  #if RISCV64_Pipeline1
12583  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12584  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12585  "etiss_uint32 num_stages = 4;\n"
12586  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12587  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12588  #endif
12589  #if RISCV64_Pipeline2
12590  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12591  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12592  "etiss_uint32 num_stages = 4;\n"
12593  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12594  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12595  #endif
12596 
12597  "etiss_uint32 res = 0;\n"
12598  "etiss_int64 upper = 0;\n"
12599  "etiss_uint32 frs1 = 0;\n"
12600  "etiss_uint32 frs2 = 0;\n"
12601 
12602 "if(64 == 32)\n"
12603 "{\n"
12604  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 2147483647) | (~((RISCV64*)cpu)->F[" + toString(rs2) + "] & -2147483648))&0xffffffffffffffff;\n"
12605  #if RISCV64_DEBUG_CALL
12606  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12607  #endif
12608 "}\n"
12609 
12610 "else\n"
12611 "{\n"
12612  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12613  #if RISCV64_DEBUG_CALL
12614  "printf(\"frs1 = %#x\\n\",frs1); \n"
12615  #endif
12616  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12617  #if RISCV64_DEBUG_CALL
12618  "printf(\"frs2 = %#x\\n\",frs2); \n"
12619  #endif
12620  "res = ((frs1 & 2147483647) | (~frs2 & -2147483648))&0xffffffff;\n"
12621  #if RISCV64_DEBUG_CALL
12622  "printf(\"res = %#x\\n\",res); \n"
12623  #endif
12624  "upper = - 1;\n"
12625  #if RISCV64_DEBUG_CALL
12626  "printf(\"upper = %#lx\\n\",upper); \n"
12627  #endif
12628  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12629  #if RISCV64_DEBUG_CALL
12630  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12631  #endif
12632 "}\n"
12633 
12634  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12635 
12636 ;
12637 return true;
12638 },
12639 0,
12640 nullptr
12641 );
12642 //-------------------------------------------------------------------------------------------------------------------
12643 static InstructionDefinition fsgnjx_s_rd_frs1_frs2(
12644  ISA32_RISCV64,
12645  "fsgnjx.s",
12646  (uint32_t)0x20002053,
12647  (uint32_t) 0xfe00707f,
12648  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12649  {
12650  etiss_uint64 rs2 = 0;
12651  static BitArrayRange R_rs2_0 (24,20);
12652  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12653  rs2 += rs2_0;
12654  etiss_uint64 rs1 = 0;
12655  static BitArrayRange R_rs1_0 (19,15);
12656  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12657  rs1 += rs1_0;
12658  etiss_uint64 rd = 0;
12659  static BitArrayRange R_rd_0 (11,7);
12660  etiss_uint64 rd_0 = R_rd_0.read(ba);
12661  rd += rd_0;
12662  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12663  partInit.getRegisterDependencies().add(reg_name[rs2],64);
12664  partInit.getRegisterDependencies().add(reg_name[rs1],64);
12665  partInit.getAffectedRegisters().add(reg_name[rd],64);
12666  partInit.getAffectedRegisters().add("instructionPointer",64);
12667  partInit.code() = std::string("//fsgnjx.s\n")+
12668  "etiss_uint32 temp = 0;\n"
12669  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12670  #if RISCV64_Pipeline1
12671  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12672  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12673  "etiss_uint32 num_stages = 4;\n"
12674  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12675  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12676  #endif
12677  #if RISCV64_Pipeline2
12678  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12679  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12680  "etiss_uint32 num_stages = 4;\n"
12681  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12682  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12683  #endif
12684 
12685  "etiss_uint32 res = 0;\n"
12686  "etiss_int64 upper = 0;\n"
12687  "etiss_uint32 frs1 = 0;\n"
12688  "etiss_uint32 frs2 = 0;\n"
12689 
12690 "if(64 == 32)\n"
12691 "{\n"
12692  "((RISCV64*)cpu)->F[" + toString(rd) + "] = (((RISCV64*)cpu)->F[" + toString(rs1) + "] ^ (((RISCV64*)cpu)->F[" + toString(rs2) + "] & -2147483648));\n"
12693  #if RISCV64_DEBUG_CALL
12694  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12695  #endif
12696 "}\n"
12697 
12698 "else\n"
12699 "{\n"
12700  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12701  #if RISCV64_DEBUG_CALL
12702  "printf(\"frs1 = %#x\\n\",frs1); \n"
12703  #endif
12704  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12705  #if RISCV64_DEBUG_CALL
12706  "printf(\"frs2 = %#x\\n\",frs2); \n"
12707  #endif
12708  "res = (frs1 ^ (frs2 & -2147483648));\n"
12709  #if RISCV64_DEBUG_CALL
12710  "printf(\"res = %#x\\n\",res); \n"
12711  #endif
12712  "upper = - 1;\n"
12713  #if RISCV64_DEBUG_CALL
12714  "printf(\"upper = %#lx\\n\",upper); \n"
12715  #endif
12716  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12717  #if RISCV64_DEBUG_CALL
12718  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12719  #endif
12720 "}\n"
12721 
12722  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12723 
12724 ;
12725 return true;
12726 },
12727 0,
12728 nullptr
12729 );
12730 //-------------------------------------------------------------------------------------------------------------------
12731 static InstructionDefinition fmin_s_rd_frs1_frs2(
12732  ISA32_RISCV64,
12733  "fmin.s",
12734  (uint32_t)0x28000053,
12735  (uint32_t) 0xfe00707f,
12736  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12737  {
12738  etiss_uint64 rs2 = 0;
12739  static BitArrayRange R_rs2_0 (24,20);
12740  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12741  rs2 += rs2_0;
12742  etiss_uint64 rs1 = 0;
12743  static BitArrayRange R_rs1_0 (19,15);
12744  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12745  rs1 += rs1_0;
12746  etiss_uint64 rd = 0;
12747  static BitArrayRange R_rd_0 (11,7);
12748  etiss_uint64 rd_0 = R_rd_0.read(ba);
12749  rd += rd_0;
12750  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12751  partInit.getAffectedRegisters().add(reg_name[rd],64);
12752  partInit.getAffectedRegisters().add("instructionPointer",64);
12753  partInit.code() = std::string("//fmin.s\n")+
12754  "etiss_uint32 temp = 0;\n"
12755  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12756  #if RISCV64_Pipeline1
12757  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12758  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12759  "etiss_uint32 num_stages = 4;\n"
12760  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12761  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12762  #endif
12763  #if RISCV64_Pipeline2
12764  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12765  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12766  "etiss_uint32 num_stages = 4;\n"
12767  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12768  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12769  #endif
12770 
12771  "etiss_uint32 res = 0;\n"
12772  "etiss_int64 upper = 0;\n"
12773  "etiss_uint32 flags = 0;\n"
12774  "etiss_uint32 frs1 = 0;\n"
12775  "etiss_uint32 frs2 = 0;\n"
12776 
12777 "if(64 == 32)\n"
12778 "{\n"
12779  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fsel_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)0);\n"
12780  #if RISCV64_DEBUG_CALL
12781  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12782  #endif
12783 "}\n"
12784 
12785 "else\n"
12786 "{\n"
12787  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12788  #if RISCV64_DEBUG_CALL
12789  "printf(\"frs1 = %#x\\n\",frs1); \n"
12790  #endif
12791  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12792  #if RISCV64_DEBUG_CALL
12793  "printf(\"frs2 = %#x\\n\",frs2); \n"
12794  #endif
12795  "res = fsel_s(frs1, frs2, (etiss_uint32)0);\n"
12796  #if RISCV64_DEBUG_CALL
12797  "printf(\"res = %#x\\n\",res); \n"
12798  #endif
12799  "upper = - 1;\n"
12800  #if RISCV64_DEBUG_CALL
12801  "printf(\"upper = %#lx\\n\",upper); \n"
12802  #endif
12803  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12804  #if RISCV64_DEBUG_CALL
12805  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12806  #endif
12807 "}\n"
12808 "flags = fget_flags();\n"
12809 #if RISCV64_DEBUG_CALL
12810 "printf(\"flags = %#x\\n\",flags); \n"
12811 #endif
12812 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
12813 #if RISCV64_DEBUG_CALL
12814 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
12815 #endif
12816 
12817  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12818 
12819 ;
12820 return true;
12821 },
12822 0,
12823 nullptr
12824 );
12825 //-------------------------------------------------------------------------------------------------------------------
12826 static InstructionDefinition fmax_s_rd_frs1_frs2(
12827  ISA32_RISCV64,
12828  "fmax.s",
12829  (uint32_t)0x28001053,
12830  (uint32_t) 0xfe00707f,
12831  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12832  {
12833  etiss_uint64 rs2 = 0;
12834  static BitArrayRange R_rs2_0 (24,20);
12835  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
12836  rs2 += rs2_0;
12837  etiss_uint64 rs1 = 0;
12838  static BitArrayRange R_rs1_0 (19,15);
12839  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12840  rs1 += rs1_0;
12841  etiss_uint64 rd = 0;
12842  static BitArrayRange R_rd_0 (11,7);
12843  etiss_uint64 rd_0 = R_rd_0.read(ba);
12844  rd += rd_0;
12845  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12846  partInit.getAffectedRegisters().add(reg_name[rd],64);
12847  partInit.getAffectedRegisters().add("instructionPointer",64);
12848  partInit.code() = std::string("//fmax.s\n")+
12849  "etiss_uint32 temp = 0;\n"
12850  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12851  #if RISCV64_Pipeline1
12852  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12853  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12854  "etiss_uint32 num_stages = 4;\n"
12855  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12856  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12857  #endif
12858  #if RISCV64_Pipeline2
12859  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12860  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12861  "etiss_uint32 num_stages = 4;\n"
12862  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12863  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12864  #endif
12865 
12866  "etiss_uint32 res = 0;\n"
12867  "etiss_int64 upper = 0;\n"
12868  "etiss_uint32 flags = 0;\n"
12869  "etiss_uint32 frs1 = 0;\n"
12870  "etiss_uint32 frs2 = 0;\n"
12871 
12872 "if(64 == 32)\n"
12873 "{\n"
12874  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fsel_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)1);\n"
12875  #if RISCV64_DEBUG_CALL
12876  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12877  #endif
12878 "}\n"
12879 
12880 "else\n"
12881 "{\n"
12882  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12883  #if RISCV64_DEBUG_CALL
12884  "printf(\"frs1 = %#x\\n\",frs1); \n"
12885  #endif
12886  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
12887  #if RISCV64_DEBUG_CALL
12888  "printf(\"frs2 = %#x\\n\",frs2); \n"
12889  #endif
12890  "res = fsel_s(frs1, frs2, (etiss_uint32)1);\n"
12891  #if RISCV64_DEBUG_CALL
12892  "printf(\"res = %#x\\n\",res); \n"
12893  #endif
12894  "upper = - 1;\n"
12895  #if RISCV64_DEBUG_CALL
12896  "printf(\"upper = %#lx\\n\",upper); \n"
12897  #endif
12898  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
12899  #if RISCV64_DEBUG_CALL
12900  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
12901  #endif
12902 "}\n"
12903 "flags = fget_flags();\n"
12904 #if RISCV64_DEBUG_CALL
12905 "printf(\"flags = %#x\\n\",flags); \n"
12906 #endif
12907 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
12908 #if RISCV64_DEBUG_CALL
12909 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
12910 #endif
12911 
12912  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
12913 
12914 ;
12915 return true;
12916 },
12917 0,
12918 nullptr
12919 );
12920 //-------------------------------------------------------------------------------------------------------------------
12921 static InstructionDefinition fcvt_w_s_rd_frs1(
12922  ISA32_RISCV64,
12923  "fcvt.w.s",
12924  (uint32_t)0xc0000053,
12925  (uint32_t) 0xfff0007f,
12926  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
12927  {
12928  etiss_uint64 rs1 = 0;
12929  static BitArrayRange R_rs1_0 (19,15);
12930  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
12931  rs1 += rs1_0;
12932  etiss_uint64 rd = 0;
12933  static BitArrayRange R_rd_0 (11,7);
12934  etiss_uint64 rd_0 = R_rd_0.read(ba);
12935  rd += rd_0;
12936  etiss_uint64 rm = 0;
12937  static BitArrayRange R_rm_0 (14,12);
12938  etiss_uint64 rm_0 = R_rm_0.read(ba);
12939  rm += rm_0;
12940  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
12941  partInit.getAffectedRegisters().add(reg_name[rd],64);
12942  partInit.getAffectedRegisters().add("instructionPointer",64);
12943  partInit.code() = std::string("//fcvt.w.s\n")+
12944  "etiss_uint32 temp = 0;\n"
12945  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
12946  #if RISCV64_Pipeline1
12947  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12948  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12949  "etiss_uint32 num_stages = 4;\n"
12950  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12951  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12952  #endif
12953  #if RISCV64_Pipeline2
12954  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
12955  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
12956  "etiss_uint32 num_stages = 4;\n"
12957  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
12958  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
12959  #endif
12960 
12961  "etiss_uint32 flags = 0;\n"
12962  "etiss_uint32 frs1 = 0;\n"
12963 
12964 "if(64 == 32)\n"
12965 "{\n"
12966  "etiss_int32 cast_0 = fcvt_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], (etiss_uint32)0, (" + toString(rm) + " & 0xff)); \n"
12967  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
12968  "{\n"
12969  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
12970  "}\n"
12971  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
12972  #if RISCV64_DEBUG_CALL
12973  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
12974  #endif
12975 "}\n"
12976 
12977 "else\n"
12978 "{\n"
12979  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
12980  #if RISCV64_DEBUG_CALL
12981  "printf(\"frs1 = %#x\\n\",frs1); \n"
12982  #endif
12983  "etiss_int32 cast_1 = fcvt_s(frs1, (etiss_uint32)0, (" + toString(rm) + " & 0xff)); \n"
12984  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
12985  "{\n"
12986  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
12987  "}\n"
12988  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
12989  #if RISCV64_DEBUG_CALL
12990  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
12991  #endif
12992 "}\n"
12993 "flags = fget_flags();\n"
12994 #if RISCV64_DEBUG_CALL
12995 "printf(\"flags = %#x\\n\",flags); \n"
12996 #endif
12997 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
12998 #if RISCV64_DEBUG_CALL
12999 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13000 #endif
13001 
13002  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13003 
13004 ;
13005 return true;
13006 },
13007 0,
13008 nullptr
13009 );
13010 //-------------------------------------------------------------------------------------------------------------------
13011 static InstructionDefinition fcvt_wu_s_rd_frs1(
13012  ISA32_RISCV64,
13013  "fcvt.wu.s",
13014  (uint32_t)0xc0100053,
13015  (uint32_t) 0xfff0007f,
13016  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13017  {
13018  etiss_uint64 rs1 = 0;
13019  static BitArrayRange R_rs1_0 (19,15);
13020  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13021  rs1 += rs1_0;
13022  etiss_uint64 rd = 0;
13023  static BitArrayRange R_rd_0 (11,7);
13024  etiss_uint64 rd_0 = R_rd_0.read(ba);
13025  rd += rd_0;
13026  etiss_uint64 rm = 0;
13027  static BitArrayRange R_rm_0 (14,12);
13028  etiss_uint64 rm_0 = R_rm_0.read(ba);
13029  rm += rm_0;
13030  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13031  partInit.getAffectedRegisters().add(reg_name[rd],64);
13032  partInit.getAffectedRegisters().add("instructionPointer",64);
13033  partInit.code() = std::string("//fcvt.wu.s\n")+
13034  "etiss_uint32 temp = 0;\n"
13035  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13036  #if RISCV64_Pipeline1
13037  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13038  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13039  "etiss_uint32 num_stages = 4;\n"
13040  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13041  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13042  #endif
13043  #if RISCV64_Pipeline2
13044  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13045  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13046  "etiss_uint32 num_stages = 4;\n"
13047  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13048  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13049  #endif
13050 
13051  "etiss_uint32 flags = 0;\n"
13052  "etiss_uint32 frs1 = 0;\n"
13053 
13054 "if(64 == 32)\n"
13055 "{\n"
13056  "etiss_int32 cast_0 = fcvt_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], (etiss_uint32)1, (" + toString(rm) + " & 0xff)); \n"
13057  "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
13058  "{\n"
13059  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
13060  "}\n"
13061  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
13062  #if RISCV64_DEBUG_CALL
13063  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13064  #endif
13065 "}\n"
13066 
13067 "else\n"
13068 "{\n"
13069  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
13070  #if RISCV64_DEBUG_CALL
13071  "printf(\"frs1 = %#x\\n\",frs1); \n"
13072  #endif
13073  "etiss_int32 cast_1 = fcvt_s(frs1, (etiss_uint32)1, (" + toString(rm) + " & 0xff)); \n"
13074  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
13075  "{\n"
13076  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
13077  "}\n"
13078  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_1;\n"
13079  #if RISCV64_DEBUG_CALL
13080  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13081  #endif
13082 "}\n"
13083 "flags = fget_flags();\n"
13084 #if RISCV64_DEBUG_CALL
13085 "printf(\"flags = %#x\\n\",flags); \n"
13086 #endif
13087 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
13088 #if RISCV64_DEBUG_CALL
13089 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13090 #endif
13091 
13092  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13093 
13094 ;
13095 return true;
13096 },
13097 0,
13098 nullptr
13099 );
13100 //-------------------------------------------------------------------------------------------------------------------
13101 static InstructionDefinition fcvt_l_s_rd_frs1(
13102  ISA32_RISCV64,
13103  "fcvt.l.s",
13104  (uint32_t)0xc0200053,
13105  (uint32_t) 0xfff0007f,
13106  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13107  {
13108  etiss_uint64 rs1 = 0;
13109  static BitArrayRange R_rs1_0 (19,15);
13110  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13111  rs1 += rs1_0;
13112  etiss_uint64 rd = 0;
13113  static BitArrayRange R_rd_0 (11,7);
13114  etiss_uint64 rd_0 = R_rd_0.read(ba);
13115  rd += rd_0;
13116  etiss_uint64 rm = 0;
13117  static BitArrayRange R_rm_0 (14,12);
13118  etiss_uint64 rm_0 = R_rm_0.read(ba);
13119  rm += rm_0;
13120  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13121  partInit.getAffectedRegisters().add(reg_name[rd],64);
13122  partInit.getAffectedRegisters().add("instructionPointer",64);
13123  partInit.code() = std::string("//fcvt.l.s\n")+
13124  "etiss_uint32 temp = 0;\n"
13125  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13126  #if RISCV64_Pipeline1
13127  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13128  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13129  "etiss_uint32 num_stages = 4;\n"
13130  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13131  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13132  #endif
13133  #if RISCV64_Pipeline2
13134  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13135  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13136  "etiss_uint32 num_stages = 4;\n"
13137  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13138  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13139  #endif
13140 
13141  "etiss_uint64 res = 0;\n"
13142  "etiss_uint32 flags = 0;\n"
13143 
13144 "res = fcvt_32_64(unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]), (etiss_uint32)0, (" + toString(rm) + " & 0xff));\n"
13145 #if RISCV64_DEBUG_CALL
13146 "printf(\"res = %#lx\\n\",res); \n"
13147 #endif
13148 "etiss_int64 cast_0 = res; \n"
13149 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
13150 "{\n"
13151  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
13152 "}\n"
13153 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
13154 #if RISCV64_DEBUG_CALL
13155 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13156 #endif
13157 "flags = fget_flags();\n"
13158 #if RISCV64_DEBUG_CALL
13159 "printf(\"flags = %#x\\n\",flags); \n"
13160 #endif
13161 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
13162 #if RISCV64_DEBUG_CALL
13163 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13164 #endif
13165 
13166  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13167 
13168 ;
13169 return true;
13170 },
13171 0,
13172 nullptr
13173 );
13174 //-------------------------------------------------------------------------------------------------------------------
13175 static InstructionDefinition fcvt_lu_s_rd_frs1(
13176  ISA32_RISCV64,
13177  "fcvt.lu.s",
13178  (uint32_t)0xc0300053,
13179  (uint32_t) 0xfff0007f,
13180  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13181  {
13182  etiss_uint64 rs1 = 0;
13183  static BitArrayRange R_rs1_0 (19,15);
13184  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13185  rs1 += rs1_0;
13186  etiss_uint64 rd = 0;
13187  static BitArrayRange R_rd_0 (11,7);
13188  etiss_uint64 rd_0 = R_rd_0.read(ba);
13189  rd += rd_0;
13190  etiss_uint64 rm = 0;
13191  static BitArrayRange R_rm_0 (14,12);
13192  etiss_uint64 rm_0 = R_rm_0.read(ba);
13193  rm += rm_0;
13194  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13195  partInit.getAffectedRegisters().add(reg_name[rd],64);
13196  partInit.getAffectedRegisters().add("instructionPointer",64);
13197  partInit.code() = std::string("//fcvt.lu.s\n")+
13198  "etiss_uint32 temp = 0;\n"
13199  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13200  #if RISCV64_Pipeline1
13201  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13202  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13203  "etiss_uint32 num_stages = 4;\n"
13204  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13205  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13206  #endif
13207  #if RISCV64_Pipeline2
13208  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13209  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13210  "etiss_uint32 num_stages = 4;\n"
13211  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13212  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13213  #endif
13214 
13215  "etiss_uint64 res = 0;\n"
13216  "etiss_uint32 flags = 0;\n"
13217 
13218 "res = fcvt_32_64(unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]), (etiss_uint32)1, (" + toString(rm) + " & 0xff));\n"
13219 #if RISCV64_DEBUG_CALL
13220 "printf(\"res = %#lx\\n\",res); \n"
13221 #endif
13222 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)res;\n"
13223 #if RISCV64_DEBUG_CALL
13224 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13225 #endif
13226 "flags = fget_flags();\n"
13227 #if RISCV64_DEBUG_CALL
13228 "printf(\"flags = %#x\\n\",flags); \n"
13229 #endif
13230 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
13231 #if RISCV64_DEBUG_CALL
13232 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13233 #endif
13234 
13235  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13236 
13237 ;
13238 return true;
13239 },
13240 0,
13241 nullptr
13242 );
13243 //-------------------------------------------------------------------------------------------------------------------
13244 static InstructionDefinition feq_s_rd_frs1_frs2(
13245  ISA32_RISCV64,
13246  "feq.s",
13247  (uint32_t)0xa0002053,
13248  (uint32_t) 0xfe00707f,
13249  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13250  {
13251  etiss_uint64 rs2 = 0;
13252  static BitArrayRange R_rs2_0 (24,20);
13253  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
13254  rs2 += rs2_0;
13255  etiss_uint64 rs1 = 0;
13256  static BitArrayRange R_rs1_0 (19,15);
13257  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13258  rs1 += rs1_0;
13259  etiss_uint64 rd = 0;
13260  static BitArrayRange R_rd_0 (11,7);
13261  etiss_uint64 rd_0 = R_rd_0.read(ba);
13262  rd += rd_0;
13263  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13264  partInit.getAffectedRegisters().add(reg_name[rd],64);
13265  partInit.getAffectedRegisters().add("instructionPointer",64);
13266  partInit.code() = std::string("//feq.s\n")+
13267  "etiss_uint32 temp = 0;\n"
13268  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13269  #if RISCV64_Pipeline1
13270  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13271  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13272  "etiss_uint32 num_stages = 4;\n"
13273  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13274  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13275  #endif
13276  #if RISCV64_Pipeline2
13277  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13278  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13279  "etiss_uint32 num_stages = 4;\n"
13280  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13281  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13282  #endif
13283 
13284  "etiss_uint32 flags = 0;\n"
13285  "etiss_uint32 frs1 = 0;\n"
13286  "etiss_uint32 frs2 = 0;\n"
13287 
13288 "if(64 == 32)\n"
13289 "{\n"
13290  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)0);\n"
13291  #if RISCV64_DEBUG_CALL
13292  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13293  #endif
13294 "}\n"
13295 
13296 "else\n"
13297 "{\n"
13298  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
13299  #if RISCV64_DEBUG_CALL
13300  "printf(\"frs1 = %#x\\n\",frs1); \n"
13301  #endif
13302  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
13303  #if RISCV64_DEBUG_CALL
13304  "printf(\"frs2 = %#x\\n\",frs2); \n"
13305  #endif
13306  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_s(frs1, frs2, (etiss_uint32)0);\n"
13307  #if RISCV64_DEBUG_CALL
13308  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13309  #endif
13310 "}\n"
13311 "flags = fget_flags();\n"
13312 #if RISCV64_DEBUG_CALL
13313 "printf(\"flags = %#x\\n\",flags); \n"
13314 #endif
13315 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
13316 #if RISCV64_DEBUG_CALL
13317 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13318 #endif
13319 
13320  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13321 
13322 ;
13323 return true;
13324 },
13325 0,
13326 nullptr
13327 );
13328 //-------------------------------------------------------------------------------------------------------------------
13329 static InstructionDefinition flt_s_rd_frs1_frs2(
13330  ISA32_RISCV64,
13331  "flt.s",
13332  (uint32_t)0xa0001053,
13333  (uint32_t) 0xfe00707f,
13334  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13335  {
13336  etiss_uint64 rs2 = 0;
13337  static BitArrayRange R_rs2_0 (24,20);
13338  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
13339  rs2 += rs2_0;
13340  etiss_uint64 rs1 = 0;
13341  static BitArrayRange R_rs1_0 (19,15);
13342  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13343  rs1 += rs1_0;
13344  etiss_uint64 rd = 0;
13345  static BitArrayRange R_rd_0 (11,7);
13346  etiss_uint64 rd_0 = R_rd_0.read(ba);
13347  rd += rd_0;
13348  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13349  partInit.getAffectedRegisters().add(reg_name[rd],64);
13350  partInit.getAffectedRegisters().add("instructionPointer",64);
13351  partInit.code() = std::string("//flt.s\n")+
13352  "etiss_uint32 temp = 0;\n"
13353  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13354  #if RISCV64_Pipeline1
13355  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13356  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13357  "etiss_uint32 num_stages = 4;\n"
13358  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13359  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13360  #endif
13361  #if RISCV64_Pipeline2
13362  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13363  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13364  "etiss_uint32 num_stages = 4;\n"
13365  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13366  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13367  #endif
13368 
13369  "etiss_uint32 flags = 0;\n"
13370  "etiss_uint32 frs1 = 0;\n"
13371  "etiss_uint32 frs2 = 0;\n"
13372 
13373 "if(64 == 32)\n"
13374 "{\n"
13375  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)2);\n"
13376  #if RISCV64_DEBUG_CALL
13377  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13378  #endif
13379 "}\n"
13380 
13381 "else\n"
13382 "{\n"
13383  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
13384  #if RISCV64_DEBUG_CALL
13385  "printf(\"frs1 = %#x\\n\",frs1); \n"
13386  #endif
13387  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
13388  #if RISCV64_DEBUG_CALL
13389  "printf(\"frs2 = %#x\\n\",frs2); \n"
13390  #endif
13391  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_s(frs1, frs2, (etiss_uint32)2);\n"
13392  #if RISCV64_DEBUG_CALL
13393  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13394  #endif
13395 "}\n"
13396 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = fcmp_s((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffff), (etiss_uint32)2);\n"
13397 #if RISCV64_DEBUG_CALL
13398 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13399 #endif
13400 "flags = fget_flags();\n"
13401 #if RISCV64_DEBUG_CALL
13402 "printf(\"flags = %#x\\n\",flags); \n"
13403 #endif
13404 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
13405 #if RISCV64_DEBUG_CALL
13406 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13407 #endif
13408 
13409  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13410 
13411 ;
13412 return true;
13413 },
13414 0,
13415 nullptr
13416 );
13417 //-------------------------------------------------------------------------------------------------------------------
13418 static InstructionDefinition fle_s_rd_frs1_frs2(
13419  ISA32_RISCV64,
13420  "fle.s",
13421  (uint32_t)0xa0000053,
13422  (uint32_t) 0xfe00707f,
13423  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13424  {
13425  etiss_uint64 rs2 = 0;
13426  static BitArrayRange R_rs2_0 (24,20);
13427  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
13428  rs2 += rs2_0;
13429  etiss_uint64 rs1 = 0;
13430  static BitArrayRange R_rs1_0 (19,15);
13431  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13432  rs1 += rs1_0;
13433  etiss_uint64 rd = 0;
13434  static BitArrayRange R_rd_0 (11,7);
13435  etiss_uint64 rd_0 = R_rd_0.read(ba);
13436  rd += rd_0;
13437  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13438  partInit.getAffectedRegisters().add(reg_name[rd],64);
13439  partInit.getAffectedRegisters().add("instructionPointer",64);
13440  partInit.code() = std::string("//fle.s\n")+
13441  "etiss_uint32 temp = 0;\n"
13442  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13443  #if RISCV64_Pipeline1
13444  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13445  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13446  "etiss_uint32 num_stages = 4;\n"
13447  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13448  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13449  #endif
13450  #if RISCV64_Pipeline2
13451  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13452  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13453  "etiss_uint32 num_stages = 4;\n"
13454  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13455  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13456  #endif
13457 
13458  "etiss_uint32 flags = 0;\n"
13459  "etiss_uint32 frs1 = 0;\n"
13460  "etiss_uint32 frs2 = 0;\n"
13461 
13462 "if(64 == 32)\n"
13463 "{\n"
13464  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_s(((RISCV64*)cpu)->F[" + toString(rs1) + "], ((RISCV64*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)1);\n"
13465  #if RISCV64_DEBUG_CALL
13466  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13467  #endif
13468 "}\n"
13469 
13470 "else\n"
13471 "{\n"
13472  "frs1 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]);\n"
13473  #if RISCV64_DEBUG_CALL
13474  "printf(\"frs1 = %#x\\n\",frs1); \n"
13475  #endif
13476  "frs2 = unbox_s(((RISCV64*)cpu)->F[" + toString(rs2) + "]);\n"
13477  #if RISCV64_DEBUG_CALL
13478  "printf(\"frs2 = %#x\\n\",frs2); \n"
13479  #endif
13480  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_s(frs1, frs2, (etiss_uint32)1);\n"
13481  #if RISCV64_DEBUG_CALL
13482  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13483  #endif
13484 "}\n"
13485 "flags = fget_flags();\n"
13486 #if RISCV64_DEBUG_CALL
13487 "printf(\"flags = %#x\\n\",flags); \n"
13488 #endif
13489 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
13490 #if RISCV64_DEBUG_CALL
13491 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
13492 #endif
13493 
13494  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13495 
13496 ;
13497 return true;
13498 },
13499 0,
13500 nullptr
13501 );
13502 //-------------------------------------------------------------------------------------------------------------------
13503 static InstructionDefinition fclass_s_rd_frs1(
13504  ISA32_RISCV64,
13505  "fclass.s",
13506  (uint32_t)0xe0001053,
13507  (uint32_t) 0xfff0707f,
13508  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13509  {
13510  etiss_uint64 rs1 = 0;
13511  static BitArrayRange R_rs1_0 (19,15);
13512  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13513  rs1 += rs1_0;
13514  etiss_uint64 rd = 0;
13515  static BitArrayRange R_rd_0 (11,7);
13516  etiss_uint64 rd_0 = R_rd_0.read(ba);
13517  rd += rd_0;
13518  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13519  partInit.getAffectedRegisters().add(reg_name[rd],64);
13520  partInit.getAffectedRegisters().add("instructionPointer",64);
13521  partInit.code() = std::string("//fclass.s\n")+
13522  "etiss_uint32 temp = 0;\n"
13523  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13524  #if RISCV64_Pipeline1
13525  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13526  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13527  "etiss_uint32 num_stages = 4;\n"
13528  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13529  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13530  #endif
13531  #if RISCV64_Pipeline2
13532  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13533  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13534  "etiss_uint32 num_stages = 4;\n"
13535  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13536  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13537  #endif
13538 
13539 
13540 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = fclass_s(unbox_s(((RISCV64*)cpu)->F[" + toString(rs1) + "]));\n"
13541 #if RISCV64_DEBUG_CALL
13542 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13543 #endif
13544 
13545  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13546 
13547 ;
13548 return true;
13549 },
13550 0,
13551 nullptr
13552 );
13553 //-------------------------------------------------------------------------------------------------------------------
13554 static InstructionDefinition fmv_x_w_rd_frs1(
13555  ISA32_RISCV64,
13556  "fmv.x.w",
13557  (uint32_t)0xe0000053,
13558  (uint32_t) 0xfff0707f,
13559  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13560  {
13561  etiss_uint64 rs1 = 0;
13562  static BitArrayRange R_rs1_0 (19,15);
13563  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13564  rs1 += rs1_0;
13565  etiss_uint64 rd = 0;
13566  static BitArrayRange R_rd_0 (11,7);
13567  etiss_uint64 rd_0 = R_rd_0.read(ba);
13568  rd += rd_0;
13569  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13570  partInit.getRegisterDependencies().add(reg_name[rs1],64);
13571  partInit.getAffectedRegisters().add(reg_name[rd],64);
13572  partInit.getAffectedRegisters().add("instructionPointer",64);
13573  partInit.code() = std::string("//fmv.x.w\n")+
13574  "etiss_uint32 temp = 0;\n"
13575  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13576  #if RISCV64_Pipeline1
13577  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13578  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13579  "etiss_uint32 num_stages = 4;\n"
13580  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13581  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13582  #endif
13583  #if RISCV64_Pipeline2
13584  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13585  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13586  "etiss_uint32 num_stages = 4;\n"
13587  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13588  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13589  #endif
13590 
13591 
13592 "etiss_int64 cast_0 = (((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffff); \n"
13593 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
13594 "{\n"
13595  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
13596 "}\n"
13597 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
13598 #if RISCV64_DEBUG_CALL
13599 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
13600 #endif
13601 
13602  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13603 
13604 ;
13605 return true;
13606 },
13607 0,
13608 nullptr
13609 );
13610 //-------------------------------------------------------------------------------------------------------------------
13611 static InstructionDefinition fcvt_s_w_rd_rs1(
13612  ISA32_RISCV64,
13613  "fcvt.s.w",
13614  (uint32_t)0xd0000053,
13615  (uint32_t) 0xfff0007f,
13616  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13617  {
13618  etiss_uint64 rs1 = 0;
13619  static BitArrayRange R_rs1_0 (19,15);
13620  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13621  rs1 += rs1_0;
13622  etiss_uint64 rd = 0;
13623  static BitArrayRange R_rd_0 (11,7);
13624  etiss_uint64 rd_0 = R_rd_0.read(ba);
13625  rd += rd_0;
13626  etiss_uint64 rm = 0;
13627  static BitArrayRange R_rm_0 (14,12);
13628  etiss_uint64 rm_0 = R_rm_0.read(ba);
13629  rm += rm_0;
13630  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13631  partInit.getAffectedRegisters().add(reg_name[rd],64);
13632  partInit.getAffectedRegisters().add("instructionPointer",64);
13633  partInit.code() = std::string("//fcvt.s.w\n")+
13634  "etiss_uint32 temp = 0;\n"
13635  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13636  #if RISCV64_Pipeline1
13637  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13638  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13639  "etiss_uint32 num_stages = 4;\n"
13640  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13641  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13642  #endif
13643  #if RISCV64_Pipeline2
13644  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13645  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13646  "etiss_uint32 num_stages = 4;\n"
13647  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13648  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13649  #endif
13650 
13651  "etiss_uint32 res = 0;\n"
13652  "etiss_int64 upper = 0;\n"
13653 
13654 "if(64 == 32)\n"
13655 "{\n"
13656  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fcvt_s((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)2, (" + toString(rm) + " & 0xff));\n"
13657  #if RISCV64_DEBUG_CALL
13658  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13659  #endif
13660 "}\n"
13661 
13662 "else\n"
13663 "{\n"
13664  "res = fcvt_s((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)2, (" + toString(rm) + " & 0xff));\n"
13665  #if RISCV64_DEBUG_CALL
13666  "printf(\"res = %#x\\n\",res); \n"
13667  #endif
13668  "upper = - 1;\n"
13669  #if RISCV64_DEBUG_CALL
13670  "printf(\"upper = %#lx\\n\",upper); \n"
13671  #endif
13672  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
13673  #if RISCV64_DEBUG_CALL
13674  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13675  #endif
13676 "}\n"
13677 
13678  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13679 
13680 ;
13681 return true;
13682 },
13683 0,
13684 nullptr
13685 );
13686 //-------------------------------------------------------------------------------------------------------------------
13687 static InstructionDefinition fcvt_s_wu_rd_rs1(
13688  ISA32_RISCV64,
13689  "fcvt.s.wu",
13690  (uint32_t)0xd0100053,
13691  (uint32_t) 0xfff0007f,
13692  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13693  {
13694  etiss_uint64 rs1 = 0;
13695  static BitArrayRange R_rs1_0 (19,15);
13696  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13697  rs1 += rs1_0;
13698  etiss_uint64 rd = 0;
13699  static BitArrayRange R_rd_0 (11,7);
13700  etiss_uint64 rd_0 = R_rd_0.read(ba);
13701  rd += rd_0;
13702  etiss_uint64 rm = 0;
13703  static BitArrayRange R_rm_0 (14,12);
13704  etiss_uint64 rm_0 = R_rm_0.read(ba);
13705  rm += rm_0;
13706  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13707  partInit.getAffectedRegisters().add(reg_name[rd],64);
13708  partInit.getAffectedRegisters().add("instructionPointer",64);
13709  partInit.code() = std::string("//fcvt.s.wu\n")+
13710  "etiss_uint32 temp = 0;\n"
13711  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13712  #if RISCV64_Pipeline1
13713  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13714  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13715  "etiss_uint32 num_stages = 4;\n"
13716  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13717  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13718  #endif
13719  #if RISCV64_Pipeline2
13720  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13721  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13722  "etiss_uint32 num_stages = 4;\n"
13723  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13724  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13725  #endif
13726 
13727  "etiss_uint32 res = 0;\n"
13728  "etiss_int64 upper = 0;\n"
13729 
13730 "if(64 == 32)\n"
13731 "{\n"
13732  "((RISCV64*)cpu)->F[" + toString(rd) + "] = fcvt_s((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)3, (" + toString(rm) + " & 0xff));\n"
13733  #if RISCV64_DEBUG_CALL
13734  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13735  #endif
13736 "}\n"
13737 
13738 "else\n"
13739 "{\n"
13740  "res = fcvt_s((*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)3, (" + toString(rm) + " & 0xff));\n"
13741  #if RISCV64_DEBUG_CALL
13742  "printf(\"res = %#x\\n\",res); \n"
13743  #endif
13744  "upper = - 1;\n"
13745  #if RISCV64_DEBUG_CALL
13746  "printf(\"upper = %#lx\\n\",upper); \n"
13747  #endif
13748  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
13749  #if RISCV64_DEBUG_CALL
13750  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13751  #endif
13752 "}\n"
13753 
13754  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13755 
13756 ;
13757 return true;
13758 },
13759 0,
13760 nullptr
13761 );
13762 //-------------------------------------------------------------------------------------------------------------------
13763 static InstructionDefinition fcvt_s_l_rd_xrs1(
13764  ISA32_RISCV64,
13765  "fcvt.s.l",
13766  (uint32_t)0xd0200053,
13767  (uint32_t) 0xfff0007f,
13768  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13769  {
13770  etiss_uint64 rs1 = 0;
13771  static BitArrayRange R_rs1_0 (19,15);
13772  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13773  rs1 += rs1_0;
13774  etiss_uint64 rd = 0;
13775  static BitArrayRange R_rd_0 (11,7);
13776  etiss_uint64 rd_0 = R_rd_0.read(ba);
13777  rd += rd_0;
13778  etiss_uint64 rm = 0;
13779  static BitArrayRange R_rm_0 (14,12);
13780  etiss_uint64 rm_0 = R_rm_0.read(ba);
13781  rm += rm_0;
13782  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13783  partInit.getAffectedRegisters().add(reg_name[rd],64);
13784  partInit.getAffectedRegisters().add("instructionPointer",64);
13785  partInit.code() = std::string("//fcvt.s.l\n")+
13786  "etiss_uint32 temp = 0;\n"
13787  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13788  #if RISCV64_Pipeline1
13789  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13790  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13791  "etiss_uint32 num_stages = 4;\n"
13792  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13793  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13794  #endif
13795  #if RISCV64_Pipeline2
13796  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13797  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13798  "etiss_uint32 num_stages = 4;\n"
13799  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13800  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13801  #endif
13802 
13803  "etiss_uint32 res = 0;\n"
13804  "etiss_int64 upper = 0;\n"
13805 
13806 "res = fcvt_64_32(*((RISCV64*)cpu)->X[" + toString(rs1) + "], (etiss_uint32)2);\n"
13807 #if RISCV64_DEBUG_CALL
13808 "printf(\"res = %#x\\n\",res); \n"
13809 #endif
13810 "if(64 == 32)\n"
13811 "{\n"
13812  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
13813  #if RISCV64_DEBUG_CALL
13814  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13815  #endif
13816 "}\n"
13817 
13818 "else\n"
13819 "{\n"
13820  "upper = - 1;\n"
13821  #if RISCV64_DEBUG_CALL
13822  "printf(\"upper = %#lx\\n\",upper); \n"
13823  #endif
13824  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
13825  #if RISCV64_DEBUG_CALL
13826  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13827  #endif
13828 "}\n"
13829 
13830  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13831 
13832 ;
13833 return true;
13834 },
13835 0,
13836 nullptr
13837 );
13838 //-------------------------------------------------------------------------------------------------------------------
13839 static InstructionDefinition fcvt_s_lu_rd_xrs1(
13840  ISA32_RISCV64,
13841  "fcvt.s.lu",
13842  (uint32_t)0xd0300053,
13843  (uint32_t) 0xfff0007f,
13844  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13845  {
13846  etiss_uint64 rs1 = 0;
13847  static BitArrayRange R_rs1_0 (19,15);
13848  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13849  rs1 += rs1_0;
13850  etiss_uint64 rd = 0;
13851  static BitArrayRange R_rd_0 (11,7);
13852  etiss_uint64 rd_0 = R_rd_0.read(ba);
13853  rd += rd_0;
13854  etiss_uint64 rm = 0;
13855  static BitArrayRange R_rm_0 (14,12);
13856  etiss_uint64 rm_0 = R_rm_0.read(ba);
13857  rm += rm_0;
13858  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13859  partInit.getAffectedRegisters().add(reg_name[rd],64);
13860  partInit.getAffectedRegisters().add("instructionPointer",64);
13861  partInit.code() = std::string("//fcvt.s.lu\n")+
13862  "etiss_uint32 temp = 0;\n"
13863  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13864  #if RISCV64_Pipeline1
13865  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13866  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13867  "etiss_uint32 num_stages = 4;\n"
13868  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13869  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13870  #endif
13871  #if RISCV64_Pipeline2
13872  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13873  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13874  "etiss_uint32 num_stages = 4;\n"
13875  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13876  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13877  #endif
13878 
13879  "etiss_uint32 res = 0;\n"
13880  "etiss_int64 upper = 0;\n"
13881 
13882 "res = fcvt_64_32(*((RISCV64*)cpu)->X[" + toString(rs1) + "], (etiss_uint32)3);\n"
13883 #if RISCV64_DEBUG_CALL
13884 "printf(\"res = %#x\\n\",res); \n"
13885 #endif
13886 "if(64 == 32)\n"
13887 "{\n"
13888  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
13889  #if RISCV64_DEBUG_CALL
13890  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13891  #endif
13892 "}\n"
13893 
13894 "else\n"
13895 "{\n"
13896  "upper = - 1;\n"
13897  #if RISCV64_DEBUG_CALL
13898  "printf(\"upper = %#lx\\n\",upper); \n"
13899  #endif
13900  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n"
13901  #if RISCV64_DEBUG_CALL
13902  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13903  #endif
13904 "}\n"
13905 
13906  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13907 
13908 ;
13909 return true;
13910 },
13911 0,
13912 nullptr
13913 );
13914 //-------------------------------------------------------------------------------------------------------------------
13915 static InstructionDefinition fmv_w_x_rd_rs1(
13916  ISA32_RISCV64,
13917  "fmv.w.x",
13918  (uint32_t)0xf0000053,
13919  (uint32_t) 0xfff0707f,
13920  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13921  {
13922  etiss_uint64 rs1 = 0;
13923  static BitArrayRange R_rs1_0 (19,15);
13924  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13925  rs1 += rs1_0;
13926  etiss_uint64 rd = 0;
13927  static BitArrayRange R_rd_0 (11,7);
13928  etiss_uint64 rd_0 = R_rd_0.read(ba);
13929  rd += rd_0;
13930  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
13931  partInit.getRegisterDependencies().add(reg_name[rs1],64);
13932  partInit.getAffectedRegisters().add(reg_name[rd],64);
13933  partInit.getAffectedRegisters().add("instructionPointer",64);
13934  partInit.code() = std::string("//fmv.w.x\n")+
13935  "etiss_uint32 temp = 0;\n"
13936  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
13937  #if RISCV64_Pipeline1
13938  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13939  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13940  "etiss_uint32 num_stages = 4;\n"
13941  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13942  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13943  #endif
13944  #if RISCV64_Pipeline2
13945  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
13946  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
13947  "etiss_uint32 num_stages = 4;\n"
13948  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
13949  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
13950  #endif
13951 
13952  "etiss_int64 upper = 0;\n"
13953 
13954 "if(64 == 32)\n"
13955 "{\n"
13956  "((RISCV64*)cpu)->F[" + toString(rd) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff);\n"
13957  #if RISCV64_DEBUG_CALL
13958  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13959  #endif
13960 "}\n"
13961 
13962 "else\n"
13963 "{\n"
13964  "upper = - 1;\n"
13965  #if RISCV64_DEBUG_CALL
13966  "printf(\"upper = %#lx\\n\",upper); \n"
13967  #endif
13968  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)(*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff));\n"
13969  #if RISCV64_DEBUG_CALL
13970  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
13971  #endif
13972 "}\n"
13973 
13974  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
13975 
13976 ;
13977 return true;
13978 },
13979 0,
13980 nullptr
13981 );
13982 //-------------------------------------------------------------------------------------------------------------------
13983 static InstructionDefinition fsub_d_rd_frs1_frs2(
13984  ISA32_RISCV64,
13985  "fsub.d",
13986  (uint32_t)0xa000053,
13987  (uint32_t) 0xfe00007f,
13988  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
13989  {
13990  etiss_uint64 rs2 = 0;
13991  static BitArrayRange R_rs2_0 (24,20);
13992  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
13993  rs2 += rs2_0;
13994  etiss_uint64 rs1 = 0;
13995  static BitArrayRange R_rs1_0 (19,15);
13996  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
13997  rs1 += rs1_0;
13998  etiss_uint64 rd = 0;
13999  static BitArrayRange R_rd_0 (11,7);
14000  etiss_uint64 rd_0 = R_rd_0.read(ba);
14001  rd += rd_0;
14002  etiss_uint64 rm = 0;
14003  static BitArrayRange R_rm_0 (14,12);
14004  etiss_uint64 rm_0 = R_rm_0.read(ba);
14005  rm += rm_0;
14006  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14007  partInit.getAffectedRegisters().add(reg_name[rd],64);
14008  partInit.getAffectedRegisters().add("instructionPointer",64);
14009  partInit.code() = std::string("//fsub.d\n")+
14010  "etiss_uint32 temp = 0;\n"
14011  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14012  #if RISCV64_Pipeline1
14013  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14014  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14015  "etiss_uint32 num_stages = 4;\n"
14016  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14017  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14018  #endif
14019  #if RISCV64_Pipeline2
14020  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14021  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14022  "etiss_uint32 num_stages = 4;\n"
14023  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14024  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14025  #endif
14026 
14027  "etiss_uint64 res = 0;\n"
14028  "etiss_int64 upper = 0;\n"
14029  "etiss_uint32 flags = 0;\n"
14030  "etiss_uint32 choose1 = 0;\n"
14031 
14032 "if(" + toString(rm) + " < 7)\n"
14033 "{\n"
14034  "choose1 = (" + toString(rm) + " & 0xff);\n"
14035  #if RISCV64_DEBUG_CALL
14036  "printf(\"choose1 = %#x\\n\",choose1); \n"
14037  #endif
14038 "}\n"
14039 
14040 "else\n"
14041 "{\n"
14042  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
14043  #if RISCV64_DEBUG_CALL
14044  "printf(\"choose1 = %#x\\n\",choose1); \n"
14045  #endif
14046 "}\n"
14047 "res = fsub_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), choose1);\n"
14048 #if RISCV64_DEBUG_CALL
14049 "printf(\"res = %#lx\\n\",res); \n"
14050 #endif
14051 "if(64 == 64)\n"
14052 "{\n"
14053  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14054  #if RISCV64_DEBUG_CALL
14055  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14056  #endif
14057 "}\n"
14058 
14059 "else\n"
14060 "{\n"
14061  "upper = - 1;\n"
14062  #if RISCV64_DEBUG_CALL
14063  "printf(\"upper = %#lx\\n\",upper); \n"
14064  #endif
14065  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14066  #if RISCV64_DEBUG_CALL
14067  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14068  #endif
14069 "}\n"
14070 "flags = fget_flags();\n"
14071 #if RISCV64_DEBUG_CALL
14072 "printf(\"flags = %#x\\n\",flags); \n"
14073 #endif
14074 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14075 #if RISCV64_DEBUG_CALL
14076 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14077 #endif
14078 
14079  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14080 
14081 ;
14082 return true;
14083 },
14084 0,
14085 nullptr
14086 );
14087 //-------------------------------------------------------------------------------------------------------------------
14088 static InstructionDefinition fdiv_d_rd_frs1_frs2(
14089  ISA32_RISCV64,
14090  "fdiv.d",
14091  (uint32_t)0x1a000053,
14092  (uint32_t) 0xfe00007f,
14093  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14094  {
14095  etiss_uint64 rs2 = 0;
14096  static BitArrayRange R_rs2_0 (24,20);
14097  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14098  rs2 += rs2_0;
14099  etiss_uint64 rs1 = 0;
14100  static BitArrayRange R_rs1_0 (19,15);
14101  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14102  rs1 += rs1_0;
14103  etiss_uint64 rd = 0;
14104  static BitArrayRange R_rd_0 (11,7);
14105  etiss_uint64 rd_0 = R_rd_0.read(ba);
14106  rd += rd_0;
14107  etiss_uint64 rm = 0;
14108  static BitArrayRange R_rm_0 (14,12);
14109  etiss_uint64 rm_0 = R_rm_0.read(ba);
14110  rm += rm_0;
14111  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14112  partInit.getAffectedRegisters().add(reg_name[rd],64);
14113  partInit.getAffectedRegisters().add("instructionPointer",64);
14114  partInit.code() = std::string("//fdiv.d\n")+
14115  "etiss_uint32 temp = 0;\n"
14116  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14117  #if RISCV64_Pipeline1
14118  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14119  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14120  "etiss_uint32 num_stages = 4;\n"
14121  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14122  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14123  #endif
14124  #if RISCV64_Pipeline2
14125  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14126  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14127  "etiss_uint32 num_stages = 4;\n"
14128  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14129  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14130  #endif
14131 
14132  "etiss_uint64 res = 0;\n"
14133  "etiss_int64 upper = 0;\n"
14134  "etiss_uint32 flags = 0;\n"
14135  "etiss_uint32 choose1 = 0;\n"
14136 
14137 "if(" + toString(rm) + " < 7)\n"
14138 "{\n"
14139  "choose1 = (" + toString(rm) + " & 0xff);\n"
14140  #if RISCV64_DEBUG_CALL
14141  "printf(\"choose1 = %#x\\n\",choose1); \n"
14142  #endif
14143 "}\n"
14144 
14145 "else\n"
14146 "{\n"
14147  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
14148  #if RISCV64_DEBUG_CALL
14149  "printf(\"choose1 = %#x\\n\",choose1); \n"
14150  #endif
14151 "}\n"
14152 "res = fdiv_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), choose1);\n"
14153 #if RISCV64_DEBUG_CALL
14154 "printf(\"res = %#lx\\n\",res); \n"
14155 #endif
14156 "if(64 == 64)\n"
14157 "{\n"
14158  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14159  #if RISCV64_DEBUG_CALL
14160  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14161  #endif
14162 "}\n"
14163 
14164 "else\n"
14165 "{\n"
14166  "upper = - 1;\n"
14167  #if RISCV64_DEBUG_CALL
14168  "printf(\"upper = %#lx\\n\",upper); \n"
14169  #endif
14170  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14171  #if RISCV64_DEBUG_CALL
14172  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14173  #endif
14174 "}\n"
14175 "flags = fget_flags();\n"
14176 #if RISCV64_DEBUG_CALL
14177 "printf(\"flags = %#x\\n\",flags); \n"
14178 #endif
14179 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14180 #if RISCV64_DEBUG_CALL
14181 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14182 #endif
14183 
14184  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14185 
14186 ;
14187 return true;
14188 },
14189 0,
14190 nullptr
14191 );
14192 //-------------------------------------------------------------------------------------------------------------------
14193 static InstructionDefinition fsqrt_d_rd_frs1(
14194  ISA32_RISCV64,
14195  "fsqrt.d",
14196  (uint32_t)0x5a000053,
14197  (uint32_t) 0xfff0007f,
14198  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14199  {
14200  etiss_uint64 rs1 = 0;
14201  static BitArrayRange R_rs1_0 (19,15);
14202  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14203  rs1 += rs1_0;
14204  etiss_uint64 rd = 0;
14205  static BitArrayRange R_rd_0 (11,7);
14206  etiss_uint64 rd_0 = R_rd_0.read(ba);
14207  rd += rd_0;
14208  etiss_uint64 rm = 0;
14209  static BitArrayRange R_rm_0 (14,12);
14210  etiss_uint64 rm_0 = R_rm_0.read(ba);
14211  rm += rm_0;
14212  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14213  partInit.getAffectedRegisters().add(reg_name[rd],64);
14214  partInit.getAffectedRegisters().add("instructionPointer",64);
14215  partInit.code() = std::string("//fsqrt.d\n")+
14216  "etiss_uint32 temp = 0;\n"
14217  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14218  #if RISCV64_Pipeline1
14219  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14220  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14221  "etiss_uint32 num_stages = 4;\n"
14222  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14223  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14224  #endif
14225  #if RISCV64_Pipeline2
14226  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14227  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14228  "etiss_uint32 num_stages = 4;\n"
14229  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14230  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14231  #endif
14232 
14233  "etiss_uint64 res = 0;\n"
14234  "etiss_int64 upper = 0;\n"
14235  "etiss_uint32 flags = 0;\n"
14236  "etiss_uint32 choose1 = 0;\n"
14237 
14238 "if(" + toString(rm) + " < 7)\n"
14239 "{\n"
14240  "choose1 = (" + toString(rm) + " & 0xff);\n"
14241  #if RISCV64_DEBUG_CALL
14242  "printf(\"choose1 = %#x\\n\",choose1); \n"
14243  #endif
14244 "}\n"
14245 
14246 "else\n"
14247 "{\n"
14248  "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n"
14249  #if RISCV64_DEBUG_CALL
14250  "printf(\"choose1 = %#x\\n\",choose1); \n"
14251  #endif
14252 "}\n"
14253 "res = fsqrt_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), choose1);\n"
14254 #if RISCV64_DEBUG_CALL
14255 "printf(\"res = %#lx\\n\",res); \n"
14256 #endif
14257 "if(64 == 64)\n"
14258 "{\n"
14259  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14260  #if RISCV64_DEBUG_CALL
14261  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14262  #endif
14263 "}\n"
14264 
14265 "else\n"
14266 "{\n"
14267  "upper = - 1;\n"
14268  #if RISCV64_DEBUG_CALL
14269  "printf(\"upper = %#lx\\n\",upper); \n"
14270  #endif
14271  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14272  #if RISCV64_DEBUG_CALL
14273  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14274  #endif
14275 "}\n"
14276 "flags = fget_flags();\n"
14277 #if RISCV64_DEBUG_CALL
14278 "printf(\"flags = %#x\\n\",flags); \n"
14279 #endif
14280 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14281 #if RISCV64_DEBUG_CALL
14282 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14283 #endif
14284 
14285  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14286 
14287 ;
14288 return true;
14289 },
14290 0,
14291 nullptr
14292 );
14293 //-------------------------------------------------------------------------------------------------------------------
14294 static InstructionDefinition fsgnj_d_rd_frs1_frs2(
14295  ISA32_RISCV64,
14296  "fsgnj.d",
14297  (uint32_t)0x22000053,
14298  (uint32_t) 0xfe00707f,
14299  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14300  {
14301  etiss_uint64 rs2 = 0;
14302  static BitArrayRange R_rs2_0 (24,20);
14303  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14304  rs2 += rs2_0;
14305  etiss_uint64 rs1 = 0;
14306  static BitArrayRange R_rs1_0 (19,15);
14307  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14308  rs1 += rs1_0;
14309  etiss_uint64 rd = 0;
14310  static BitArrayRange R_rd_0 (11,7);
14311  etiss_uint64 rd_0 = R_rd_0.read(ba);
14312  rd += rd_0;
14313  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14314  partInit.getRegisterDependencies().add(reg_name[rs2],64);
14315  partInit.getRegisterDependencies().add(reg_name[rs1],64);
14316  partInit.getAffectedRegisters().add(reg_name[rd],64);
14317  partInit.getAffectedRegisters().add("instructionPointer",64);
14318  partInit.code() = std::string("//fsgnj.d\n")+
14319  "etiss_uint32 temp = 0;\n"
14320  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14321  #if RISCV64_Pipeline1
14322  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14323  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14324  "etiss_uint32 num_stages = 4;\n"
14325  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14326  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14327  #endif
14328  #if RISCV64_Pipeline2
14329  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14330  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14331  "etiss_uint32 num_stages = 4;\n"
14332  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14333  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14334  #endif
14335 
14336  "etiss_uint64 res = 0;\n"
14337  "etiss_int64 ONE = 0;\n"
14338  "etiss_int64 upper = 0;\n"
14339  "etiss_int64 MSK1 = 0;\n"
14340  "etiss_int64 MSK2 = 0;\n"
14341 
14342 "ONE = 1;\n"
14343 #if RISCV64_DEBUG_CALL
14344 "printf(\"ONE = %#lx\\n\",ONE); \n"
14345 #endif
14346 "MSK1 = (ONE << 63);\n"
14347 #if RISCV64_DEBUG_CALL
14348 "printf(\"MSK1 = %#lx\\n\",MSK1); \n"
14349 #endif
14350 "MSK2 = MSK1 - 1;\n"
14351 #if RISCV64_DEBUG_CALL
14352 "printf(\"MSK2 = %#lx\\n\",MSK2); \n"
14353 #endif
14354 "res = (((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff) & MSK2) | ((((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff) & MSK1));\n"
14355 #if RISCV64_DEBUG_CALL
14356 "printf(\"res = %#lx\\n\",res); \n"
14357 #endif
14358 "if(64 == 64)\n"
14359 "{\n"
14360  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14361  #if RISCV64_DEBUG_CALL
14362  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14363  #endif
14364 "}\n"
14365 
14366 "else\n"
14367 "{\n"
14368  "upper = - 1;\n"
14369  #if RISCV64_DEBUG_CALL
14370  "printf(\"upper = %#lx\\n\",upper); \n"
14371  #endif
14372  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14373  #if RISCV64_DEBUG_CALL
14374  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14375  #endif
14376 "}\n"
14377 
14378  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14379 
14380 ;
14381 return true;
14382 },
14383 0,
14384 nullptr
14385 );
14386 //-------------------------------------------------------------------------------------------------------------------
14387 static InstructionDefinition fsgnjn_d_rd_frs1_frs2(
14388  ISA32_RISCV64,
14389  "fsgnjn.d",
14390  (uint32_t)0x22001053,
14391  (uint32_t) 0xfe00707f,
14392  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14393  {
14394  etiss_uint64 rs2 = 0;
14395  static BitArrayRange R_rs2_0 (24,20);
14396  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14397  rs2 += rs2_0;
14398  etiss_uint64 rs1 = 0;
14399  static BitArrayRange R_rs1_0 (19,15);
14400  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14401  rs1 += rs1_0;
14402  etiss_uint64 rd = 0;
14403  static BitArrayRange R_rd_0 (11,7);
14404  etiss_uint64 rd_0 = R_rd_0.read(ba);
14405  rd += rd_0;
14406  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14407  partInit.getRegisterDependencies().add(reg_name[rs2],64);
14408  partInit.getRegisterDependencies().add(reg_name[rs1],64);
14409  partInit.getAffectedRegisters().add(reg_name[rd],64);
14410  partInit.getAffectedRegisters().add("instructionPointer",64);
14411  partInit.code() = std::string("//fsgnjn.d\n")+
14412  "etiss_uint32 temp = 0;\n"
14413  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14414  #if RISCV64_Pipeline1
14415  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14416  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14417  "etiss_uint32 num_stages = 4;\n"
14418  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14419  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14420  #endif
14421  #if RISCV64_Pipeline2
14422  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14423  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14424  "etiss_uint32 num_stages = 4;\n"
14425  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14426  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14427  #endif
14428 
14429  "etiss_uint64 res = 0;\n"
14430  "etiss_int64 ONE = 0;\n"
14431  "etiss_int64 upper = 0;\n"
14432  "etiss_int64 MSK1 = 0;\n"
14433  "etiss_int64 MSK2 = 0;\n"
14434 
14435 "ONE = 1;\n"
14436 #if RISCV64_DEBUG_CALL
14437 "printf(\"ONE = %#lx\\n\",ONE); \n"
14438 #endif
14439 "MSK1 = (ONE << 63);\n"
14440 #if RISCV64_DEBUG_CALL
14441 "printf(\"MSK1 = %#lx\\n\",MSK1); \n"
14442 #endif
14443 "MSK2 = MSK1 - 1;\n"
14444 #if RISCV64_DEBUG_CALL
14445 "printf(\"MSK2 = %#lx\\n\",MSK2); \n"
14446 #endif
14447 "res = (((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff) & MSK2) | (~(((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff) & MSK1))&0xffffffffffffffff;\n"
14448 #if RISCV64_DEBUG_CALL
14449 "printf(\"res = %#lx\\n\",res); \n"
14450 #endif
14451 "if(64 == 64)\n"
14452 "{\n"
14453  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14454  #if RISCV64_DEBUG_CALL
14455  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14456  #endif
14457 "}\n"
14458 
14459 "else\n"
14460 "{\n"
14461  "upper = - 1;\n"
14462  #if RISCV64_DEBUG_CALL
14463  "printf(\"upper = %#lx\\n\",upper); \n"
14464  #endif
14465  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14466  #if RISCV64_DEBUG_CALL
14467  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14468  #endif
14469 "}\n"
14470 
14471  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14472 
14473 ;
14474 return true;
14475 },
14476 0,
14477 nullptr
14478 );
14479 //-------------------------------------------------------------------------------------------------------------------
14480 static InstructionDefinition fsgnjx_d_rd_frs1_frs2(
14481  ISA32_RISCV64,
14482  "fsgnjx.d",
14483  (uint32_t)0x22002053,
14484  (uint32_t) 0xfe00707f,
14485  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14486  {
14487  etiss_uint64 rs2 = 0;
14488  static BitArrayRange R_rs2_0 (24,20);
14489  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14490  rs2 += rs2_0;
14491  etiss_uint64 rs1 = 0;
14492  static BitArrayRange R_rs1_0 (19,15);
14493  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14494  rs1 += rs1_0;
14495  etiss_uint64 rd = 0;
14496  static BitArrayRange R_rd_0 (11,7);
14497  etiss_uint64 rd_0 = R_rd_0.read(ba);
14498  rd += rd_0;
14499  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14500  partInit.getRegisterDependencies().add(reg_name[rs2],64);
14501  partInit.getRegisterDependencies().add(reg_name[rs1],64);
14502  partInit.getAffectedRegisters().add(reg_name[rd],64);
14503  partInit.getAffectedRegisters().add("instructionPointer",64);
14504  partInit.code() = std::string("//fsgnjx.d\n")+
14505  "etiss_uint32 temp = 0;\n"
14506  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14507  #if RISCV64_Pipeline1
14508  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14509  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14510  "etiss_uint32 num_stages = 4;\n"
14511  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14512  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14513  #endif
14514  #if RISCV64_Pipeline2
14515  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14516  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14517  "etiss_uint32 num_stages = 4;\n"
14518  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14519  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14520  #endif
14521 
14522  "etiss_uint64 res = 0;\n"
14523  "etiss_int64 ONE = 0;\n"
14524  "etiss_int64 upper = 0;\n"
14525  "etiss_int64 MSK1 = 0;\n"
14526 
14527 "ONE = 1;\n"
14528 #if RISCV64_DEBUG_CALL
14529 "printf(\"ONE = %#lx\\n\",ONE); \n"
14530 #endif
14531 "MSK1 = (ONE << 63);\n"
14532 #if RISCV64_DEBUG_CALL
14533 "printf(\"MSK1 = %#lx\\n\",MSK1); \n"
14534 #endif
14535 "res = ((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff) ^ ((((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff) & MSK1));\n"
14536 #if RISCV64_DEBUG_CALL
14537 "printf(\"res = %#lx\\n\",res); \n"
14538 #endif
14539 "if(64 == 64)\n"
14540 "{\n"
14541  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14542  #if RISCV64_DEBUG_CALL
14543  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14544  #endif
14545 "}\n"
14546 
14547 "else\n"
14548 "{\n"
14549  "upper = - 1;\n"
14550  #if RISCV64_DEBUG_CALL
14551  "printf(\"upper = %#lx\\n\",upper); \n"
14552  #endif
14553  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14554  #if RISCV64_DEBUG_CALL
14555  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14556  #endif
14557 "}\n"
14558 
14559  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14560 
14561 ;
14562 return true;
14563 },
14564 0,
14565 nullptr
14566 );
14567 //-------------------------------------------------------------------------------------------------------------------
14568 static InstructionDefinition fmin_d_rd_frs1_frs2(
14569  ISA32_RISCV64,
14570  "fmin.d",
14571  (uint32_t)0x2a000053,
14572  (uint32_t) 0xfe00707f,
14573  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14574  {
14575  etiss_uint64 rs2 = 0;
14576  static BitArrayRange R_rs2_0 (24,20);
14577  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14578  rs2 += rs2_0;
14579  etiss_uint64 rs1 = 0;
14580  static BitArrayRange R_rs1_0 (19,15);
14581  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14582  rs1 += rs1_0;
14583  etiss_uint64 rd = 0;
14584  static BitArrayRange R_rd_0 (11,7);
14585  etiss_uint64 rd_0 = R_rd_0.read(ba);
14586  rd += rd_0;
14587  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14588  partInit.getAffectedRegisters().add(reg_name[rd],64);
14589  partInit.getAffectedRegisters().add("instructionPointer",64);
14590  partInit.code() = std::string("//fmin.d\n")+
14591  "etiss_uint32 temp = 0;\n"
14592  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14593  #if RISCV64_Pipeline1
14594  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14595  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14596  "etiss_uint32 num_stages = 4;\n"
14597  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14598  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14599  #endif
14600  #if RISCV64_Pipeline2
14601  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14602  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14603  "etiss_uint32 num_stages = 4;\n"
14604  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14605  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14606  #endif
14607 
14608  "etiss_uint64 res = 0;\n"
14609  "etiss_int64 upper = 0;\n"
14610  "etiss_uint32 flags = 0;\n"
14611 
14612 "res = fsel_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)0);\n"
14613 #if RISCV64_DEBUG_CALL
14614 "printf(\"res = %#lx\\n\",res); \n"
14615 #endif
14616 "if(64 == 64)\n"
14617 "{\n"
14618  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14619  #if RISCV64_DEBUG_CALL
14620  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14621  #endif
14622 "}\n"
14623 
14624 "else\n"
14625 "{\n"
14626  "upper = - 1;\n"
14627  #if RISCV64_DEBUG_CALL
14628  "printf(\"upper = %#lx\\n\",upper); \n"
14629  #endif
14630  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14631  #if RISCV64_DEBUG_CALL
14632  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14633  #endif
14634 "}\n"
14635 "flags = fget_flags();\n"
14636 #if RISCV64_DEBUG_CALL
14637 "printf(\"flags = %#x\\n\",flags); \n"
14638 #endif
14639 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14640 #if RISCV64_DEBUG_CALL
14641 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14642 #endif
14643 
14644  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14645 
14646 ;
14647 return true;
14648 },
14649 0,
14650 nullptr
14651 );
14652 //-------------------------------------------------------------------------------------------------------------------
14653 static InstructionDefinition fmax_d_rd_frs1_frs2(
14654  ISA32_RISCV64,
14655  "fmax.d",
14656  (uint32_t)0x2a001053,
14657  (uint32_t) 0xfe00707f,
14658  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14659  {
14660  etiss_uint64 rs2 = 0;
14661  static BitArrayRange R_rs2_0 (24,20);
14662  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14663  rs2 += rs2_0;
14664  etiss_uint64 rs1 = 0;
14665  static BitArrayRange R_rs1_0 (19,15);
14666  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14667  rs1 += rs1_0;
14668  etiss_uint64 rd = 0;
14669  static BitArrayRange R_rd_0 (11,7);
14670  etiss_uint64 rd_0 = R_rd_0.read(ba);
14671  rd += rd_0;
14672  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14673  partInit.getAffectedRegisters().add(reg_name[rd],64);
14674  partInit.getAffectedRegisters().add("instructionPointer",64);
14675  partInit.code() = std::string("//fmax.d\n")+
14676  "etiss_uint32 temp = 0;\n"
14677  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14678  #if RISCV64_Pipeline1
14679  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14680  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14681  "etiss_uint32 num_stages = 4;\n"
14682  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14683  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14684  #endif
14685  #if RISCV64_Pipeline2
14686  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14687  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14688  "etiss_uint32 num_stages = 4;\n"
14689  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14690  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14691  #endif
14692 
14693  "etiss_uint64 res = 0;\n"
14694  "etiss_int64 upper = 0;\n"
14695  "etiss_uint32 flags = 0;\n"
14696 
14697 "res = fsel_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)1);\n"
14698 #if RISCV64_DEBUG_CALL
14699 "printf(\"res = %#lx\\n\",res); \n"
14700 #endif
14701 "if(64 == 64)\n"
14702 "{\n"
14703  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14704  #if RISCV64_DEBUG_CALL
14705  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14706  #endif
14707 "}\n"
14708 
14709 "else\n"
14710 "{\n"
14711  "upper = - 1;\n"
14712  #if RISCV64_DEBUG_CALL
14713  "printf(\"upper = %#lx\\n\",upper); \n"
14714  #endif
14715  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14716  #if RISCV64_DEBUG_CALL
14717  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14718  #endif
14719 "}\n"
14720 "flags = fget_flags();\n"
14721 #if RISCV64_DEBUG_CALL
14722 "printf(\"flags = %#x\\n\",flags); \n"
14723 #endif
14724 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14725 #if RISCV64_DEBUG_CALL
14726 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14727 #endif
14728 
14729  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14730 
14731 ;
14732 return true;
14733 },
14734 0,
14735 nullptr
14736 );
14737 //-------------------------------------------------------------------------------------------------------------------
14738 static InstructionDefinition fcvt_d_s_rd_frs1(
14739  ISA32_RISCV64,
14740  "fcvt.d.s",
14741  (uint32_t)0x42000053,
14742  (uint32_t) 0xfff0007f,
14743  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14744  {
14745  etiss_uint64 rs1 = 0;
14746  static BitArrayRange R_rs1_0 (19,15);
14747  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14748  rs1 += rs1_0;
14749  etiss_uint64 rd = 0;
14750  static BitArrayRange R_rd_0 (11,7);
14751  etiss_uint64 rd_0 = R_rd_0.read(ba);
14752  rd += rd_0;
14753  etiss_uint64 rm = 0;
14754  static BitArrayRange R_rm_0 (14,12);
14755  etiss_uint64 rm_0 = R_rm_0.read(ba);
14756  rm += rm_0;
14757  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14758  partInit.getAffectedRegisters().add(reg_name[rd],64);
14759  partInit.getAffectedRegisters().add("instructionPointer",64);
14760  partInit.code() = std::string("//fcvt.d.s\n")+
14761  "etiss_uint32 temp = 0;\n"
14762  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14763  #if RISCV64_Pipeline1
14764  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14765  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14766  "etiss_uint32 num_stages = 4;\n"
14767  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14768  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14769  #endif
14770  #if RISCV64_Pipeline2
14771  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14772  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14773  "etiss_uint32 num_stages = 4;\n"
14774  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14775  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14776  #endif
14777 
14778  "etiss_uint64 res = 0;\n"
14779  "etiss_int64 upper = 0;\n"
14780 
14781 "res = fconv_f2d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffff), (" + toString(rm) + " & 0xff));\n"
14782 #if RISCV64_DEBUG_CALL
14783 "printf(\"res = %#lx\\n\",res); \n"
14784 #endif
14785 "if(64 == 64)\n"
14786 "{\n"
14787  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
14788  #if RISCV64_DEBUG_CALL
14789  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14790  #endif
14791 "}\n"
14792 
14793 "else\n"
14794 "{\n"
14795  "upper = - 1;\n"
14796  #if RISCV64_DEBUG_CALL
14797  "printf(\"upper = %#lx\\n\",upper); \n"
14798  #endif
14799  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
14800  #if RISCV64_DEBUG_CALL
14801  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
14802  #endif
14803 "}\n"
14804 
14805  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14806 
14807 ;
14808 return true;
14809 },
14810 0,
14811 nullptr
14812 );
14813 //-------------------------------------------------------------------------------------------------------------------
14814 static InstructionDefinition feq_d_rd_frs1_frs2(
14815  ISA32_RISCV64,
14816  "feq.d",
14817  (uint32_t)0xa2002053,
14818  (uint32_t) 0xfe00707f,
14819  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14820  {
14821  etiss_uint64 rs2 = 0;
14822  static BitArrayRange R_rs2_0 (24,20);
14823  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14824  rs2 += rs2_0;
14825  etiss_uint64 rs1 = 0;
14826  static BitArrayRange R_rs1_0 (19,15);
14827  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14828  rs1 += rs1_0;
14829  etiss_uint64 rd = 0;
14830  static BitArrayRange R_rd_0 (11,7);
14831  etiss_uint64 rd_0 = R_rd_0.read(ba);
14832  rd += rd_0;
14833  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14834  partInit.getAffectedRegisters().add(reg_name[rd],64);
14835  partInit.getAffectedRegisters().add("instructionPointer",64);
14836  partInit.code() = std::string("//feq.d\n")+
14837  "etiss_uint32 temp = 0;\n"
14838  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14839  #if RISCV64_Pipeline1
14840  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14841  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14842  "etiss_uint32 num_stages = 4;\n"
14843  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14844  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14845  #endif
14846  #if RISCV64_Pipeline2
14847  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14848  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14849  "etiss_uint32 num_stages = 4;\n"
14850  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14851  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14852  #endif
14853 
14854  "etiss_uint32 flags = 0;\n"
14855 
14856 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)0);\n"
14857 #if RISCV64_DEBUG_CALL
14858 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
14859 #endif
14860 "flags = fget_flags();\n"
14861 #if RISCV64_DEBUG_CALL
14862 "printf(\"flags = %#x\\n\",flags); \n"
14863 #endif
14864 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14865 #if RISCV64_DEBUG_CALL
14866 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14867 #endif
14868 
14869  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14870 
14871 ;
14872 return true;
14873 },
14874 0,
14875 nullptr
14876 );
14877 //-------------------------------------------------------------------------------------------------------------------
14878 static InstructionDefinition flt_d_rd_frs1_frs2(
14879  ISA32_RISCV64,
14880  "flt.d",
14881  (uint32_t)0xa2001053,
14882  (uint32_t) 0xfe00707f,
14883  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14884  {
14885  etiss_uint64 rs2 = 0;
14886  static BitArrayRange R_rs2_0 (24,20);
14887  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14888  rs2 += rs2_0;
14889  etiss_uint64 rs1 = 0;
14890  static BitArrayRange R_rs1_0 (19,15);
14891  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14892  rs1 += rs1_0;
14893  etiss_uint64 rd = 0;
14894  static BitArrayRange R_rd_0 (11,7);
14895  etiss_uint64 rd_0 = R_rd_0.read(ba);
14896  rd += rd_0;
14897  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14898  partInit.getAffectedRegisters().add(reg_name[rd],64);
14899  partInit.getAffectedRegisters().add("instructionPointer",64);
14900  partInit.code() = std::string("//flt.d\n")+
14901  "etiss_uint32 temp = 0;\n"
14902  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14903  #if RISCV64_Pipeline1
14904  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14905  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14906  "etiss_uint32 num_stages = 4;\n"
14907  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14908  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14909  #endif
14910  #if RISCV64_Pipeline2
14911  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14912  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14913  "etiss_uint32 num_stages = 4;\n"
14914  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14915  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14916  #endif
14917 
14918  "etiss_uint32 flags = 0;\n"
14919 
14920 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)2);\n"
14921 #if RISCV64_DEBUG_CALL
14922 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
14923 #endif
14924 "flags = fget_flags();\n"
14925 #if RISCV64_DEBUG_CALL
14926 "printf(\"flags = %#x\\n\",flags); \n"
14927 #endif
14928 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14929 #if RISCV64_DEBUG_CALL
14930 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14931 #endif
14932 
14933  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14934 
14935 ;
14936 return true;
14937 },
14938 0,
14939 nullptr
14940 );
14941 //-------------------------------------------------------------------------------------------------------------------
14942 static InstructionDefinition fle_d_rd_frs1_frs2(
14943  ISA32_RISCV64,
14944  "fle.d",
14945  (uint32_t)0xa2000053,
14946  (uint32_t) 0xfe00707f,
14947  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
14948  {
14949  etiss_uint64 rs2 = 0;
14950  static BitArrayRange R_rs2_0 (24,20);
14951  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
14952  rs2 += rs2_0;
14953  etiss_uint64 rs1 = 0;
14954  static BitArrayRange R_rs1_0 (19,15);
14955  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
14956  rs1 += rs1_0;
14957  etiss_uint64 rd = 0;
14958  static BitArrayRange R_rd_0 (11,7);
14959  etiss_uint64 rd_0 = R_rd_0.read(ba);
14960  rd += rd_0;
14961  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
14962  partInit.getAffectedRegisters().add(reg_name[rd],64);
14963  partInit.getAffectedRegisters().add("instructionPointer",64);
14964  partInit.code() = std::string("//fle.d\n")+
14965  "etiss_uint32 temp = 0;\n"
14966  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
14967  #if RISCV64_Pipeline1
14968  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14969  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14970  "etiss_uint32 num_stages = 4;\n"
14971  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14972  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14973  #endif
14974  #if RISCV64_Pipeline2
14975  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
14976  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
14977  "etiss_uint32 num_stages = 4;\n"
14978  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
14979  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
14980  #endif
14981 
14982  "etiss_uint32 flags = 0;\n"
14983 
14984 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_uint64)fcmp_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)1);\n"
14985 #if RISCV64_DEBUG_CALL
14986 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
14987 #endif
14988 "flags = fget_flags();\n"
14989 #if RISCV64_DEBUG_CALL
14990 "printf(\"flags = %#x\\n\",flags); \n"
14991 #endif
14992 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
14993 #if RISCV64_DEBUG_CALL
14994 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
14995 #endif
14996 
14997  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
14998 
14999 ;
15000 return true;
15001 },
15002 0,
15003 nullptr
15004 );
15005 //-------------------------------------------------------------------------------------------------------------------
15006 static InstructionDefinition fclass_d_rd_frs1(
15007  ISA32_RISCV64,
15008  "fclass.d",
15009  (uint32_t)0xe2001053,
15010  (uint32_t) 0xfff0707f,
15011  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15012  {
15013  etiss_uint64 rs1 = 0;
15014  static BitArrayRange R_rs1_0 (19,15);
15015  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15016  rs1 += rs1_0;
15017  etiss_uint64 rd = 0;
15018  static BitArrayRange R_rd_0 (11,7);
15019  etiss_uint64 rd_0 = R_rd_0.read(ba);
15020  rd += rd_0;
15021  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15022  partInit.getAffectedRegisters().add(reg_name[rd],64);
15023  partInit.getAffectedRegisters().add("instructionPointer",64);
15024  partInit.code() = std::string("//fclass.d\n")+
15025  "etiss_uint32 temp = 0;\n"
15026  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15027  #if RISCV64_Pipeline1
15028  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15029  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15030  "etiss_uint32 num_stages = 4;\n"
15031  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15032  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15033  #endif
15034  #if RISCV64_Pipeline2
15035  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15036  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15037  "etiss_uint32 num_stages = 4;\n"
15038  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15039  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15040  #endif
15041 
15042 
15043 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = fclass_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff));\n"
15044 #if RISCV64_DEBUG_CALL
15045 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
15046 #endif
15047 
15048  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15049 
15050 ;
15051 return true;
15052 },
15053 0,
15054 nullptr
15055 );
15056 //-------------------------------------------------------------------------------------------------------------------
15057 static InstructionDefinition fmv_x_d_rd_frs1(
15058  ISA32_RISCV64,
15059  "fmv.x.d",
15060  (uint32_t)0xe2000053,
15061  (uint32_t) 0xfff0707f,
15062  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15063  {
15064  etiss_uint64 rs1 = 0;
15065  static BitArrayRange R_rs1_0 (19,15);
15066  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15067  rs1 += rs1_0;
15068  etiss_uint64 rd = 0;
15069  static BitArrayRange R_rd_0 (11,7);
15070  etiss_uint64 rd_0 = R_rd_0.read(ba);
15071  rd += rd_0;
15072  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15073  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15074  partInit.getAffectedRegisters().add(reg_name[rd],64);
15075  partInit.getAffectedRegisters().add("instructionPointer",64);
15076  partInit.code() = std::string("//fmv.x.d\n")+
15077  "etiss_uint32 temp = 0;\n"
15078  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15079  #if RISCV64_Pipeline1
15080  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15081  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15082  "etiss_uint32 num_stages = 4;\n"
15083  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15084  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15085  #endif
15086  #if RISCV64_Pipeline2
15087  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15088  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15089  "etiss_uint32 num_stages = 4;\n"
15090  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15091  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15092  #endif
15093 
15094 
15095 "etiss_int64 cast_0 = ((RISCV64*)cpu)->F[" + toString(rs1) + "]; \n"
15096 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
15097 "{\n"
15098  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
15099 "}\n"
15100 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
15101 #if RISCV64_DEBUG_CALL
15102 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
15103 #endif
15104 
15105  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15106 
15107 ;
15108 return true;
15109 },
15110 0,
15111 nullptr
15112 );
15113 //-------------------------------------------------------------------------------------------------------------------
15114 static InstructionDefinition fcvt_w_d_rd_frs1(
15115  ISA32_RISCV64,
15116  "fcvt.w.d",
15117  (uint32_t)0xc2000053,
15118  (uint32_t) 0xfff0007f,
15119  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15120  {
15121  etiss_uint64 rs1 = 0;
15122  static BitArrayRange R_rs1_0 (19,15);
15123  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15124  rs1 += rs1_0;
15125  etiss_uint64 rd = 0;
15126  static BitArrayRange R_rd_0 (11,7);
15127  etiss_uint64 rd_0 = R_rd_0.read(ba);
15128  rd += rd_0;
15129  etiss_uint64 rm = 0;
15130  static BitArrayRange R_rm_0 (14,12);
15131  etiss_uint64 rm_0 = R_rm_0.read(ba);
15132  rm += rm_0;
15133  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15134  partInit.getAffectedRegisters().add(reg_name[rd],64);
15135  partInit.getAffectedRegisters().add("instructionPointer",64);
15136  partInit.code() = std::string("//fcvt.w.d\n")+
15137  "etiss_uint32 temp = 0;\n"
15138  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15139  #if RISCV64_Pipeline1
15140  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15141  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15142  "etiss_uint32 num_stages = 4;\n"
15143  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15144  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15145  #endif
15146  #if RISCV64_Pipeline2
15147  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15148  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15149  "etiss_uint32 num_stages = 4;\n"
15150  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15151  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15152  #endif
15153 
15154  "etiss_uint32 flags = 0;\n"
15155 
15156 "etiss_int32 cast_0 = fcvt_64_32((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (etiss_uint32)0, (" + toString(rm) + " & 0xff)); \n"
15157 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
15158 "{\n"
15159  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
15160 "}\n"
15161 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
15162 #if RISCV64_DEBUG_CALL
15163 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
15164 #endif
15165 "flags = fget_flags();\n"
15166 #if RISCV64_DEBUG_CALL
15167 "printf(\"flags = %#x\\n\",flags); \n"
15168 #endif
15169 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
15170 #if RISCV64_DEBUG_CALL
15171 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
15172 #endif
15173 
15174  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15175 
15176 ;
15177 return true;
15178 },
15179 0,
15180 nullptr
15181 );
15182 //-------------------------------------------------------------------------------------------------------------------
15183 static InstructionDefinition fcvt_wu_d_rd_frs1(
15184  ISA32_RISCV64,
15185  "fcvt.wu.d",
15186  (uint32_t)0xc2100053,
15187  (uint32_t) 0xfff0007f,
15188  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15189  {
15190  etiss_uint64 rs1 = 0;
15191  static BitArrayRange R_rs1_0 (19,15);
15192  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15193  rs1 += rs1_0;
15194  etiss_uint64 rd = 0;
15195  static BitArrayRange R_rd_0 (11,7);
15196  etiss_uint64 rd_0 = R_rd_0.read(ba);
15197  rd += rd_0;
15198  etiss_uint64 rm = 0;
15199  static BitArrayRange R_rm_0 (14,12);
15200  etiss_uint64 rm_0 = R_rm_0.read(ba);
15201  rm += rm_0;
15202  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15203  partInit.getAffectedRegisters().add(reg_name[rd],64);
15204  partInit.getAffectedRegisters().add("instructionPointer",64);
15205  partInit.code() = std::string("//fcvt.wu.d\n")+
15206  "etiss_uint32 temp = 0;\n"
15207  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15208  #if RISCV64_Pipeline1
15209  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15210  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15211  "etiss_uint32 num_stages = 4;\n"
15212  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15213  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15214  #endif
15215  #if RISCV64_Pipeline2
15216  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15217  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15218  "etiss_uint32 num_stages = 4;\n"
15219  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15220  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15221  #endif
15222 
15223  "etiss_uint32 flags = 0;\n"
15224 
15225 "etiss_int32 cast_0 = fcvt_64_32((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (etiss_uint32)1, (" + toString(rm) + " & 0xff)); \n"
15226 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
15227 "{\n"
15228  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
15229 "}\n"
15230 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
15231 #if RISCV64_DEBUG_CALL
15232 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
15233 #endif
15234 "flags = fget_flags();\n"
15235 #if RISCV64_DEBUG_CALL
15236 "printf(\"flags = %#x\\n\",flags); \n"
15237 #endif
15238 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
15239 #if RISCV64_DEBUG_CALL
15240 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
15241 #endif
15242 
15243  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15244 
15245 ;
15246 return true;
15247 },
15248 0,
15249 nullptr
15250 );
15251 //-------------------------------------------------------------------------------------------------------------------
15252 static InstructionDefinition fcvt_l_d_rd_frs1(
15253  ISA32_RISCV64,
15254  "fcvt.l.d",
15255  (uint32_t)0xc2200053,
15256  (uint32_t) 0xfff0007f,
15257  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15258  {
15259  etiss_uint64 rs1 = 0;
15260  static BitArrayRange R_rs1_0 (19,15);
15261  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15262  rs1 += rs1_0;
15263  etiss_uint64 rd = 0;
15264  static BitArrayRange R_rd_0 (11,7);
15265  etiss_uint64 rd_0 = R_rd_0.read(ba);
15266  rd += rd_0;
15267  etiss_uint64 rm = 0;
15268  static BitArrayRange R_rm_0 (14,12);
15269  etiss_uint64 rm_0 = R_rm_0.read(ba);
15270  rm += rm_0;
15271  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15272  partInit.getAffectedRegisters().add(reg_name[rd],64);
15273  partInit.getAffectedRegisters().add("instructionPointer",64);
15274  partInit.code() = std::string("//fcvt.l.d\n")+
15275  "etiss_uint32 temp = 0;\n"
15276  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15277  #if RISCV64_Pipeline1
15278  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15279  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15280  "etiss_uint32 num_stages = 4;\n"
15281  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15282  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15283  #endif
15284  #if RISCV64_Pipeline2
15285  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15286  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15287  "etiss_uint32 num_stages = 4;\n"
15288  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15289  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15290  #endif
15291 
15292  "etiss_uint32 flags = 0;\n"
15293 
15294 "etiss_int64 cast_0 = fcvt_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (etiss_uint32)0, (" + toString(rm) + " & 0xff)); \n"
15295 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
15296 "{\n"
15297  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
15298 "}\n"
15299 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
15300 #if RISCV64_DEBUG_CALL
15301 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
15302 #endif
15303 "flags = fget_flags();\n"
15304 #if RISCV64_DEBUG_CALL
15305 "printf(\"flags = %#x\\n\",flags); \n"
15306 #endif
15307 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
15308 #if RISCV64_DEBUG_CALL
15309 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
15310 #endif
15311 
15312  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15313 
15314 ;
15315 return true;
15316 },
15317 0,
15318 nullptr
15319 );
15320 //-------------------------------------------------------------------------------------------------------------------
15321 static InstructionDefinition fcvt_lu_d_rd_frs1(
15322  ISA32_RISCV64,
15323  "fcvt.lu.d",
15324  (uint32_t)0xc2300053,
15325  (uint32_t) 0xfff0007f,
15326  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15327  {
15328  etiss_uint64 rs1 = 0;
15329  static BitArrayRange R_rs1_0 (19,15);
15330  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15331  rs1 += rs1_0;
15332  etiss_uint64 rd = 0;
15333  static BitArrayRange R_rd_0 (11,7);
15334  etiss_uint64 rd_0 = R_rd_0.read(ba);
15335  rd += rd_0;
15336  etiss_uint64 rm = 0;
15337  static BitArrayRange R_rm_0 (14,12);
15338  etiss_uint64 rm_0 = R_rm_0.read(ba);
15339  rm += rm_0;
15340  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15341  partInit.getAffectedRegisters().add(reg_name[rd],64);
15342  partInit.getAffectedRegisters().add("instructionPointer",64);
15343  partInit.code() = std::string("//fcvt.lu.d\n")+
15344  "etiss_uint32 temp = 0;\n"
15345  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15346  #if RISCV64_Pipeline1
15347  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15348  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15349  "etiss_uint32 num_stages = 4;\n"
15350  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15351  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15352  #endif
15353  #if RISCV64_Pipeline2
15354  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15355  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15356  "etiss_uint32 num_stages = 4;\n"
15357  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15358  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15359  #endif
15360 
15361  "etiss_uint32 flags = 0;\n"
15362 
15363 "etiss_int64 cast_0 = fcvt_d((((RISCV64*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (etiss_uint32)1, (" + toString(rm) + " & 0xff)); \n"
15364 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
15365 "{\n"
15366  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
15367 "}\n"
15368 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
15369 #if RISCV64_DEBUG_CALL
15370 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
15371 #endif
15372 "flags = fget_flags();\n"
15373 #if RISCV64_DEBUG_CALL
15374 "printf(\"flags = %#x\\n\",flags); \n"
15375 #endif
15376 "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n"
15377 #if RISCV64_DEBUG_CALL
15378 "printf(\"((RISCV64*)cpu)->FCSR = %#x\\n\",((RISCV64*)cpu)->FCSR); \n"
15379 #endif
15380 
15381  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15382 
15383 ;
15384 return true;
15385 },
15386 0,
15387 nullptr
15388 );
15389 //-------------------------------------------------------------------------------------------------------------------
15390 static InstructionDefinition fcvt_d_w_rd_rs1(
15391  ISA32_RISCV64,
15392  "fcvt.d.w",
15393  (uint32_t)0xd2000053,
15394  (uint32_t) 0xfff0007f,
15395  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15396  {
15397  etiss_uint64 rs1 = 0;
15398  static BitArrayRange R_rs1_0 (19,15);
15399  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15400  rs1 += rs1_0;
15401  etiss_uint64 rd = 0;
15402  static BitArrayRange R_rd_0 (11,7);
15403  etiss_uint64 rd_0 = R_rd_0.read(ba);
15404  rd += rd_0;
15405  etiss_uint64 rm = 0;
15406  static BitArrayRange R_rm_0 (14,12);
15407  etiss_uint64 rm_0 = R_rm_0.read(ba);
15408  rm += rm_0;
15409  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15410  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15411  partInit.getAffectedRegisters().add(reg_name[rd],64);
15412  partInit.getAffectedRegisters().add("instructionPointer",64);
15413  partInit.code() = std::string("//fcvt.d.w\n")+
15414  "etiss_uint32 temp = 0;\n"
15415  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15416  #if RISCV64_Pipeline1
15417  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15418  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15419  "etiss_uint32 num_stages = 4;\n"
15420  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15421  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15422  #endif
15423  #if RISCV64_Pipeline2
15424  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15425  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15426  "etiss_uint32 num_stages = 4;\n"
15427  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15428  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15429  #endif
15430 
15431  "etiss_uint64 res = 0;\n"
15432  "etiss_int64 upper = 0;\n"
15433 
15434 "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
15435 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
15436 "{\n"
15437  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
15438 "}\n"
15439 "res = fcvt_32_64((etiss_int64)cast_0, (etiss_uint32)2, (" + toString(rm) + " & 0xff));\n"
15440 #if RISCV64_DEBUG_CALL
15441 "printf(\"res = %#lx\\n\",res); \n"
15442 #endif
15443 "if(64 == 64)\n"
15444 "{\n"
15445  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
15446  #if RISCV64_DEBUG_CALL
15447  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15448  #endif
15449 "}\n"
15450 
15451 "else\n"
15452 "{\n"
15453  "upper = - 1;\n"
15454  #if RISCV64_DEBUG_CALL
15455  "printf(\"upper = %#lx\\n\",upper); \n"
15456  #endif
15457  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
15458  #if RISCV64_DEBUG_CALL
15459  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15460  #endif
15461 "}\n"
15462 
15463  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15464 
15465 ;
15466 return true;
15467 },
15468 0,
15469 nullptr
15470 );
15471 //-------------------------------------------------------------------------------------------------------------------
15472 static InstructionDefinition fcvt_d_wu_rd_rs1(
15473  ISA32_RISCV64,
15474  "fcvt.d.wu",
15475  (uint32_t)0xd2100053,
15476  (uint32_t) 0xfff0007f,
15477  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15478  {
15479  etiss_uint64 rs1 = 0;
15480  static BitArrayRange R_rs1_0 (19,15);
15481  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15482  rs1 += rs1_0;
15483  etiss_uint64 rd = 0;
15484  static BitArrayRange R_rd_0 (11,7);
15485  etiss_uint64 rd_0 = R_rd_0.read(ba);
15486  rd += rd_0;
15487  etiss_uint64 rm = 0;
15488  static BitArrayRange R_rm_0 (14,12);
15489  etiss_uint64 rm_0 = R_rm_0.read(ba);
15490  rm += rm_0;
15491  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15492  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15493  partInit.getAffectedRegisters().add(reg_name[rd],64);
15494  partInit.getAffectedRegisters().add("instructionPointer",64);
15495  partInit.code() = std::string("//fcvt.d.wu\n")+
15496  "etiss_uint32 temp = 0;\n"
15497  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15498  #if RISCV64_Pipeline1
15499  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15500  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15501  "etiss_uint32 num_stages = 4;\n"
15502  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15503  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15504  #endif
15505  #if RISCV64_Pipeline2
15506  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15507  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15508  "etiss_uint32 num_stages = 4;\n"
15509  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15510  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15511  #endif
15512 
15513  "etiss_uint64 res = 0;\n"
15514  "etiss_int64 upper = 0;\n"
15515 
15516 "res = fcvt_32_64((etiss_uint64)(*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)3, (" + toString(rm) + " & 0xff));\n"
15517 #if RISCV64_DEBUG_CALL
15518 "printf(\"res = %#lx\\n\",res); \n"
15519 #endif
15520 "if(64 == 64)\n"
15521 "{\n"
15522  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
15523  #if RISCV64_DEBUG_CALL
15524  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15525  #endif
15526 "}\n"
15527 
15528 "else\n"
15529 "{\n"
15530  "upper = - 1;\n"
15531  #if RISCV64_DEBUG_CALL
15532  "printf(\"upper = %#lx\\n\",upper); \n"
15533  #endif
15534  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
15535  #if RISCV64_DEBUG_CALL
15536  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15537  #endif
15538 "}\n"
15539 
15540  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15541 
15542 ;
15543 return true;
15544 },
15545 0,
15546 nullptr
15547 );
15548 //-------------------------------------------------------------------------------------------------------------------
15549 static InstructionDefinition fcvt_d_l_rd_rs1(
15550  ISA32_RISCV64,
15551  "fcvt.d.l",
15552  (uint32_t)0xd2200053,
15553  (uint32_t) 0xfff0007f,
15554  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15555  {
15556  etiss_uint64 rs1 = 0;
15557  static BitArrayRange R_rs1_0 (19,15);
15558  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15559  rs1 += rs1_0;
15560  etiss_uint64 rd = 0;
15561  static BitArrayRange R_rd_0 (11,7);
15562  etiss_uint64 rd_0 = R_rd_0.read(ba);
15563  rd += rd_0;
15564  etiss_uint64 rm = 0;
15565  static BitArrayRange R_rm_0 (14,12);
15566  etiss_uint64 rm_0 = R_rm_0.read(ba);
15567  rm += rm_0;
15568  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15569  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15570  partInit.getAffectedRegisters().add(reg_name[rd],64);
15571  partInit.getAffectedRegisters().add("instructionPointer",64);
15572  partInit.code() = std::string("//fcvt.d.l\n")+
15573  "etiss_uint32 temp = 0;\n"
15574  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15575  #if RISCV64_Pipeline1
15576  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15577  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15578  "etiss_uint32 num_stages = 4;\n"
15579  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15580  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15581  #endif
15582  #if RISCV64_Pipeline2
15583  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15584  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15585  "etiss_uint32 num_stages = 4;\n"
15586  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15587  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15588  #endif
15589 
15590  "etiss_uint64 res = 0;\n"
15591  "etiss_int64 upper = 0;\n"
15592 
15593 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
15594 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
15595 "{\n"
15596  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
15597 "}\n"
15598 "res = fcvt_d((etiss_int64)cast_0, (etiss_uint32)2, (" + toString(rm) + " & 0xff));\n"
15599 #if RISCV64_DEBUG_CALL
15600 "printf(\"res = %#lx\\n\",res); \n"
15601 #endif
15602 "if(64 == 64)\n"
15603 "{\n"
15604  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
15605  #if RISCV64_DEBUG_CALL
15606  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15607  #endif
15608 "}\n"
15609 
15610 "else\n"
15611 "{\n"
15612  "upper = - 1;\n"
15613  #if RISCV64_DEBUG_CALL
15614  "printf(\"upper = %#lx\\n\",upper); \n"
15615  #endif
15616  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
15617  #if RISCV64_DEBUG_CALL
15618  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15619  #endif
15620 "}\n"
15621 
15622  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15623 
15624 ;
15625 return true;
15626 },
15627 0,
15628 nullptr
15629 );
15630 //-------------------------------------------------------------------------------------------------------------------
15631 static InstructionDefinition fcvt_d_lu_rd_rs1(
15632  ISA32_RISCV64,
15633  "fcvt.d.lu",
15634  (uint32_t)0xd2300053,
15635  (uint32_t) 0xfff0007f,
15636  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15637  {
15638  etiss_uint64 rs1 = 0;
15639  static BitArrayRange R_rs1_0 (19,15);
15640  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15641  rs1 += rs1_0;
15642  etiss_uint64 rd = 0;
15643  static BitArrayRange R_rd_0 (11,7);
15644  etiss_uint64 rd_0 = R_rd_0.read(ba);
15645  rd += rd_0;
15646  etiss_uint64 rm = 0;
15647  static BitArrayRange R_rm_0 (14,12);
15648  etiss_uint64 rm_0 = R_rm_0.read(ba);
15649  rm += rm_0;
15650  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15651  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15652  partInit.getAffectedRegisters().add(reg_name[rd],64);
15653  partInit.getAffectedRegisters().add("instructionPointer",64);
15654  partInit.code() = std::string("//fcvt.d.lu\n")+
15655  "etiss_uint32 temp = 0;\n"
15656  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15657  #if RISCV64_Pipeline1
15658  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15659  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15660  "etiss_uint32 num_stages = 4;\n"
15661  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15662  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15663  #endif
15664  #if RISCV64_Pipeline2
15665  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15666  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15667  "etiss_uint32 num_stages = 4;\n"
15668  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15669  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15670  #endif
15671 
15672  "etiss_uint64 res = 0;\n"
15673  "etiss_int64 upper = 0;\n"
15674 
15675 "res = fcvt_d((etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs1) + "], (etiss_uint32)3, (" + toString(rm) + " & 0xff));\n"
15676 #if RISCV64_DEBUG_CALL
15677 "printf(\"res = %#lx\\n\",res); \n"
15678 #endif
15679 "if(64 == 64)\n"
15680 "{\n"
15681  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
15682  #if RISCV64_DEBUG_CALL
15683  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15684  #endif
15685 "}\n"
15686 
15687 "else\n"
15688 "{\n"
15689  "upper = - 1;\n"
15690  #if RISCV64_DEBUG_CALL
15691  "printf(\"upper = %#lx\\n\",upper); \n"
15692  #endif
15693  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n"
15694  #if RISCV64_DEBUG_CALL
15695  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15696  #endif
15697 "}\n"
15698 
15699  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15700 
15701 ;
15702 return true;
15703 },
15704 0,
15705 nullptr
15706 );
15707 //-------------------------------------------------------------------------------------------------------------------
15708 static InstructionDefinition fmv_d_x_rd_rs1(
15709  ISA32_RISCV64,
15710  "fmv.d.x",
15711  (uint32_t)0xf2000053,
15712  (uint32_t) 0xfff0707f,
15713  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15714  {
15715  etiss_uint64 rs1 = 0;
15716  static BitArrayRange R_rs1_0 (19,15);
15717  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15718  rs1 += rs1_0;
15719  etiss_uint64 rd = 0;
15720  static BitArrayRange R_rd_0 (11,7);
15721  etiss_uint64 rd_0 = R_rd_0.read(ba);
15722  rd += rd_0;
15723  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15724  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15725  partInit.getAffectedRegisters().add(reg_name[rd],64);
15726  partInit.getAffectedRegisters().add("instructionPointer",64);
15727  partInit.code() = std::string("//fmv.d.x\n")+
15728  "etiss_uint32 temp = 0;\n"
15729  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15730  #if RISCV64_Pipeline1
15731  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15732  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15733  "etiss_uint32 num_stages = 4;\n"
15734  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15735  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15736  #endif
15737  #if RISCV64_Pipeline2
15738  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15739  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15740  "etiss_uint32 num_stages = 4;\n"
15741  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15742  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15743  #endif
15744 
15745 
15746 "((RISCV64*)cpu)->F[" + toString(rd) + "] = (etiss_uint64)*((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
15747 #if RISCV64_DEBUG_CALL
15748 "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
15749 #endif
15750 
15751  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 4 ))+"ULL; \n"
15752 
15753 ;
15754 return true;
15755 },
15756 0,
15757 nullptr
15758 );
15759 //-------------------------------------------------------------------------------------------------------------------
15760 static InstructionDefinition c_addi4spn_rd_imm(
15761  ISA16_RISCV64,
15762  "c.addi4spn",
15763  (uint16_t)0x0,
15764  (uint16_t) 0xe003,
15765  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15766  {
15767  etiss_uint64 rd = 0;
15768  static BitArrayRange R_rd_0 (4,2);
15769  etiss_uint64 rd_0 = R_rd_0.read(ba);
15770  rd += rd_0;
15771  etiss_uint64 imm = 0;
15772  static BitArrayRange R_imm_4 (12,11);
15773  etiss_uint64 imm_4 = R_imm_4.read(ba);
15774  imm += imm_4<<4;
15775  static BitArrayRange R_imm_6 (10,7);
15776  etiss_uint64 imm_6 = R_imm_6.read(ba);
15777  imm += imm_6<<6;
15778  static BitArrayRange R_imm_2 (6,6);
15779  etiss_uint64 imm_2 = R_imm_2.read(ba);
15780  imm += imm_2<<2;
15781  static BitArrayRange R_imm_3 (5,5);
15782  etiss_uint64 imm_3 = R_imm_3.read(ba);
15783  imm += imm_3<<3;
15784  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15785  partInit.getRegisterDependencies().add(reg_name[2],64);
15786  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
15787  partInit.getAffectedRegisters().add("instructionPointer",64);
15788  partInit.code() = std::string("//c.addi4spn\n")+
15789  "etiss_uint32 exception = 0;\n"
15790  "etiss_uint32 temp = 0;\n"
15791  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15792  #if RISCV64_Pipeline1
15793  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15794  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15795  "etiss_uint32 num_stages = 4;\n"
15796  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15797  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15798  #endif
15799  #if RISCV64_Pipeline2
15800  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15801  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15802  "etiss_uint32 num_stages = 4;\n"
15803  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15804  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15805  #endif
15806 
15807 
15808 "if(" + toString(imm) + " == 0)\n"
15809 "{\n"
15810  "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n"
15811 "}\n"
15812 
15813 "*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = *((RISCV64*)cpu)->X[2] + " + toString(imm) + ";\n"
15814 #if RISCV64_DEBUG_CALL
15815 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + " + 8]); \n"
15816 #endif
15817 
15818  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
15819 
15820  "return exception;\n"
15821 ;
15822 return true;
15823 },
15824 0,
15825 nullptr
15826 );
15827 //-------------------------------------------------------------------------------------------------------------------
15828 static InstructionDefinition c_addi_rs1_imm(
15829  ISA16_RISCV64,
15830  "c.addi",
15831  (uint16_t)0x1,
15832  (uint16_t) 0xe003,
15833  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15834  {
15835  etiss_uint64 rs1 = 0;
15836  static BitArrayRange R_rs1_0 (11,7);
15837  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
15838  rs1 += rs1_0;
15839  etiss_int64 imm = 0;
15840  static BitArrayRange R_imm_5 (12,12);
15841  etiss_int64 imm_5 = R_imm_5.read(ba);
15842  imm += imm_5<<5;
15843  static BitArrayRange R_imm_0 (6,2);
15844  etiss_int64 imm_0 = R_imm_0.read(ba);
15845  imm += imm_0;
15846  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15847  partInit.getRegisterDependencies().add(reg_name[rs1],64);
15848  partInit.getAffectedRegisters().add(reg_name[rs1],64);
15849  partInit.getAffectedRegisters().add("instructionPointer",64);
15850  partInit.code() = std::string("//c.addi\n")+
15851  "etiss_uint32 temp = 0;\n"
15852  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15853  #if RISCV64_Pipeline1
15854  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15855  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15856  "etiss_uint32 num_stages = 4;\n"
15857  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15858  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15859  #endif
15860  #if RISCV64_Pipeline2
15861  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15862  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15863  "etiss_uint32 num_stages = 4;\n"
15864  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15865  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15866  #endif
15867 
15868  "etiss_int64 imm_extended = 0;\n"
15869 
15870 "if((" + toString(imm) + " & 0x20)>>5 == 0)\n"
15871 "{\n"
15872  "imm_extended = 0;\n"
15873  #if RISCV64_DEBUG_CALL
15874  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
15875  #endif
15876 "}\n"
15877 
15878 "else\n"
15879 "{\n"
15880  "imm_extended = 4294967295;\n"
15881  #if RISCV64_DEBUG_CALL
15882  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
15883  #endif
15884  "imm_extended = (imm_extended << 32);\n"
15885  #if RISCV64_DEBUG_CALL
15886  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
15887  #endif
15888  "imm_extended = imm_extended + 4294967232;\n"
15889  #if RISCV64_DEBUG_CALL
15890  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
15891  #endif
15892 "}\n"
15893 "imm_extended = imm_extended + " + toString(imm) + ";\n"
15894 #if RISCV64_DEBUG_CALL
15895 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
15896 #endif
15897 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[" + toString(rs1) + "]; \n"
15898 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
15899 "{\n"
15900  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
15901 "}\n"
15902 "*((RISCV64*)cpu)->X[" + toString(rs1) + "] = (etiss_int64)cast_0 + imm_extended;\n"
15903 #if RISCV64_DEBUG_CALL
15904 "printf(\"*((RISCV64*)cpu)->X[" + toString(rs1) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rs1) + "]); \n"
15905 #endif
15906 
15907  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
15908 
15909 ;
15910 return true;
15911 },
15912 0,
15913 nullptr
15914 );
15915 //-------------------------------------------------------------------------------------------------------------------
15916 static InstructionDefinition c_nop_(
15917  ISA16_RISCV64,
15918  "c.nop",
15919  (uint16_t)0x1,
15920  (uint16_t) 0xffff,
15921  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15922  {
15923  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15924  partInit.getAffectedRegisters().add("instructionPointer",64);
15925  partInit.code() = std::string("//c.nop\n")+
15926  "etiss_uint32 temp = 0;\n"
15927  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15928  #if RISCV64_Pipeline1
15929  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15930  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15931  "etiss_uint32 num_stages = 4;\n"
15932  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15933  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15934  #endif
15935  #if RISCV64_Pipeline2
15936  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15937  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15938  "etiss_uint32 num_stages = 4;\n"
15939  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15940  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15941  #endif
15942 
15943 
15944 
15945  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
15946 
15947 ;
15948 return true;
15949 },
15950 0,
15951 nullptr
15952 );
15953 //-------------------------------------------------------------------------------------------------------------------
15954 static InstructionDefinition dii_(
15955  ISA16_RISCV64,
15956  "dii",
15957  (uint16_t)0x0,
15958  (uint16_t) 0xffff,
15959  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
15960  {
15961  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
15962  partInit.getAffectedRegisters().add("instructionPointer",64);
15963  partInit.code() = std::string("//dii\n")+
15964  "etiss_uint32 exception = 0;\n"
15965  "etiss_uint32 temp = 0;\n"
15966  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
15967  #if RISCV64_Pipeline1
15968  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15969  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15970  "etiss_uint32 num_stages = 4;\n"
15971  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15972  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15973  #endif
15974  #if RISCV64_Pipeline2
15975  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
15976  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
15977  "etiss_uint32 num_stages = 4;\n"
15978  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
15979  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
15980  #endif
15981 
15982 
15983 "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n"
15984 
15985  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
15986 
15987  "return exception;\n"
15988 ;
15989 return true;
15990 },
15991 0,
15992 nullptr
15993 );
15994 //-------------------------------------------------------------------------------------------------------------------
15995 static InstructionDefinition c_slli_rs1_shamt(
15996  ISA16_RISCV64,
15997  "c.slli",
15998  (uint16_t)0x2,
15999  (uint16_t) 0xe003,
16000  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16001  {
16002  etiss_uint64 rs1 = 0;
16003  static BitArrayRange R_rs1_0 (11,7);
16004  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
16005  rs1 += rs1_0;
16006  etiss_uint64 shamt = 0;
16007  static BitArrayRange R_shamt_5 (12,12);
16008  etiss_uint64 shamt_5 = R_shamt_5.read(ba);
16009  shamt += shamt_5<<5;
16010  static BitArrayRange R_shamt_0 (6,2);
16011  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
16012  shamt += shamt_0;
16013  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16014  partInit.getRegisterDependencies().add(reg_name[rs1],64);
16015  partInit.getAffectedRegisters().add(reg_name[rs1],64);
16016  partInit.getAffectedRegisters().add("instructionPointer",64);
16017  partInit.code() = std::string("//c.slli\n")+
16018  "etiss_uint32 exception = 0;\n"
16019  "etiss_uint32 temp = 0;\n"
16020  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16021  #if RISCV64_Pipeline1
16022  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16023  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16024  "etiss_uint32 num_stages = 4;\n"
16025  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16026  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16027  #endif
16028  #if RISCV64_Pipeline2
16029  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16030  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16031  "etiss_uint32 num_stages = 4;\n"
16032  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16033  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16034  #endif
16035 
16036 
16037 "if(" + toString(rs1) + " == 0)\n"
16038 "{\n"
16039  "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n"
16040 "}\n"
16041 
16042 "*((RISCV64*)cpu)->X[" + toString(rs1) + "] = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] << " + toString(shamt) + ");\n"
16043 #if RISCV64_DEBUG_CALL
16044 "printf(\"*((RISCV64*)cpu)->X[" + toString(rs1) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rs1) + "]); \n"
16045 #endif
16046 
16047  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16048 
16049  "return exception;\n"
16050 ;
16051 return true;
16052 },
16053 0,
16054 nullptr
16055 );
16056 //-------------------------------------------------------------------------------------------------------------------
16057 static InstructionDefinition c_lw_8_rd_uimm_8_rs1_(
16058  ISA16_RISCV64,
16059  "c.lw",
16060  (uint16_t)0x4000,
16061  (uint16_t) 0xe003,
16062  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16063  {
16064  etiss_uint64 rs1 = 0;
16065  static BitArrayRange R_rs1_0 (9,7);
16066  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
16067  rs1 += rs1_0;
16068  etiss_uint64 uimm = 0;
16069  static BitArrayRange R_uimm_3 (12,10);
16070  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
16071  uimm += uimm_3<<3;
16072  static BitArrayRange R_uimm_2 (6,6);
16073  etiss_uint64 uimm_2 = R_uimm_2.read(ba);
16074  uimm += uimm_2<<2;
16075  static BitArrayRange R_uimm_6 (5,5);
16076  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
16077  uimm += uimm_6<<6;
16078  etiss_uint64 rd = 0;
16079  static BitArrayRange R_rd_0 (4,2);
16080  etiss_uint64 rd_0 = R_rd_0.read(ba);
16081  rd += rd_0;
16082  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16083  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
16084  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
16085  partInit.getAffectedRegisters().add("instructionPointer",64);
16086  partInit.code() = std::string("//c.lw\n")+
16087  "etiss_uint32 exception = 0;\n"
16088  "etiss_uint32 temp = 0;\n"
16089  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16090  #if RISCV64_Pipeline1
16091  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16092  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16093  "etiss_uint32 num_stages = 4;\n"
16094  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16095  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16096  #endif
16097  #if RISCV64_Pipeline2
16098  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16099  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16100  "etiss_uint32 num_stages = 4;\n"
16101  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16102  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16103  #endif
16104 
16105  "etiss_uint64 offs = 0;\n"
16106 
16107 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n"
16108 #if RISCV64_DEBUG_CALL
16109 "printf(\"offs = %#lx\\n\",offs); \n"
16110 #endif
16111  "etiss_uint32 MEM_offs;\n"
16112 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
16113 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
16114 "etiss_int32 cast_0 = MEM_offs; \n"
16115 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
16116 "{\n"
16117  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
16118 "}\n"
16119 "*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = (etiss_int64)cast_0;\n"
16120 #if RISCV64_DEBUG_CALL
16121 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + " + 8]); \n"
16122 #endif
16123 
16124  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16125 
16126  "return exception;\n"
16127 ;
16128 return true;
16129 },
16130 0,
16131 nullptr
16132 );
16133 //-------------------------------------------------------------------------------------------------------------------
16134 static InstructionDefinition c_li_rd_imm(
16135  ISA16_RISCV64,
16136  "c.li",
16137  (uint16_t)0x4001,
16138  (uint16_t) 0xe003,
16139  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16140  {
16141  etiss_uint64 rd = 0;
16142  static BitArrayRange R_rd_0 (11,7);
16143  etiss_uint64 rd_0 = R_rd_0.read(ba);
16144  rd += rd_0;
16145  etiss_int64 imm = 0;
16146  static BitArrayRange R_imm_5 (12,12);
16147  etiss_int64 imm_5 = R_imm_5.read(ba);
16148  imm += imm_5<<5;
16149  static BitArrayRange R_imm_0 (6,2);
16150  etiss_int64 imm_0 = R_imm_0.read(ba);
16151  imm += imm_0;
16152  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16153  partInit.getAffectedRegisters().add(reg_name[rd],64);
16154  partInit.getAffectedRegisters().add("instructionPointer",64);
16155  partInit.code() = std::string("//c.li\n")+
16156  "etiss_uint32 exception = 0;\n"
16157  "etiss_uint32 temp = 0;\n"
16158  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16159  #if RISCV64_Pipeline1
16160  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16161  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16162  "etiss_uint32 num_stages = 4;\n"
16163  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16164  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16165  #endif
16166  #if RISCV64_Pipeline2
16167  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16168  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16169  "etiss_uint32 num_stages = 4;\n"
16170  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16171  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16172  #endif
16173 
16174  "etiss_int64 imm_extended = 0;\n"
16175 
16176 "if((" + toString(imm) + " & 0x20)>>5 == 0)\n"
16177 "{\n"
16178  "imm_extended = 0;\n"
16179  #if RISCV64_DEBUG_CALL
16180  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16181  #endif
16182 "}\n"
16183 
16184 "else\n"
16185 "{\n"
16186  "imm_extended = 4294967295;\n"
16187  #if RISCV64_DEBUG_CALL
16188  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16189  #endif
16190  "imm_extended = (imm_extended << 32);\n"
16191  #if RISCV64_DEBUG_CALL
16192  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16193  #endif
16194  "imm_extended = imm_extended + 4294967232;\n"
16195  #if RISCV64_DEBUG_CALL
16196  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16197  #endif
16198 "}\n"
16199 "imm_extended = imm_extended + " + toString(imm) + ";\n"
16200 #if RISCV64_DEBUG_CALL
16201 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16202 #endif
16203 "if(" + toString(rd) + " == 0)\n"
16204 "{\n"
16205  "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n"
16206 "}\n"
16207 
16208 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = imm_extended;\n"
16209 #if RISCV64_DEBUG_CALL
16210 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
16211 #endif
16212 
16213  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16214 
16215  "return exception;\n"
16216 ;
16217 return true;
16218 },
16219 0,
16220 nullptr
16221 );
16222 //-------------------------------------------------------------------------------------------------------------------
16223 static InstructionDefinition c_lwsp_rd_sp_uimm(
16224  ISA16_RISCV64,
16225  "c.lwsp",
16226  (uint16_t)0x4002,
16227  (uint16_t) 0xe003,
16228  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16229  {
16230  etiss_uint64 uimm = 0;
16231  static BitArrayRange R_uimm_5 (12,12);
16232  etiss_uint64 uimm_5 = R_uimm_5.read(ba);
16233  uimm += uimm_5<<5;
16234  static BitArrayRange R_uimm_2 (6,4);
16235  etiss_uint64 uimm_2 = R_uimm_2.read(ba);
16236  uimm += uimm_2<<2;
16237  static BitArrayRange R_uimm_6 (3,2);
16238  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
16239  uimm += uimm_6<<6;
16240  etiss_uint64 rd = 0;
16241  static BitArrayRange R_rd_0 (11,7);
16242  etiss_uint64 rd_0 = R_rd_0.read(ba);
16243  rd += rd_0;
16244  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16245  partInit.getRegisterDependencies().add(reg_name[2],64);
16246  partInit.getAffectedRegisters().add(reg_name[rd],64);
16247  partInit.getAffectedRegisters().add("instructionPointer",64);
16248  partInit.code() = std::string("//c.lwsp\n")+
16249  "etiss_uint32 exception = 0;\n"
16250  "etiss_uint32 temp = 0;\n"
16251  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16252  #if RISCV64_Pipeline1
16253  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16254  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16255  "etiss_uint32 num_stages = 4;\n"
16256  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16257  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16258  #endif
16259  #if RISCV64_Pipeline2
16260  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16261  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16262  "etiss_uint32 num_stages = 4;\n"
16263  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16264  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16265  #endif
16266 
16267  "etiss_uint64 offs = 0;\n"
16268 
16269 "offs = *((RISCV64*)cpu)->X[2] + " + toString(uimm) + ";\n"
16270 #if RISCV64_DEBUG_CALL
16271 "printf(\"offs = %#lx\\n\",offs); \n"
16272 #endif
16273  "etiss_uint32 MEM_offs;\n"
16274 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
16275 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n"
16276 "etiss_int32 cast_0 = MEM_offs; \n"
16277 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
16278 "{\n"
16279  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
16280 "}\n"
16281 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
16282 #if RISCV64_DEBUG_CALL
16283 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
16284 #endif
16285 
16286  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16287 
16288  "return exception;\n"
16289 ;
16290 return true;
16291 },
16292 0,
16293 nullptr
16294 );
16295 //-------------------------------------------------------------------------------------------------------------------
16296 static InstructionDefinition c_sw_8_rs2_uimm_8_rs1_(
16297  ISA16_RISCV64,
16298  "c.sw",
16299  (uint16_t)0xc000,
16300  (uint16_t) 0xe003,
16301  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16302  {
16303  etiss_uint64 rs2 = 0;
16304  static BitArrayRange R_rs2_0 (4,2);
16305  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
16306  rs2 += rs2_0;
16307  etiss_uint64 rs1 = 0;
16308  static BitArrayRange R_rs1_0 (9,7);
16309  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
16310  rs1 += rs1_0;
16311  etiss_uint64 uimm = 0;
16312  static BitArrayRange R_uimm_3 (12,10);
16313  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
16314  uimm += uimm_3<<3;
16315  static BitArrayRange R_uimm_2 (6,6);
16316  etiss_uint64 uimm_2 = R_uimm_2.read(ba);
16317  uimm += uimm_2<<2;
16318  static BitArrayRange R_uimm_6 (5,5);
16319  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
16320  uimm += uimm_6<<6;
16321  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16322  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
16323  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
16324  partInit.getAffectedRegisters().add("instructionPointer",64);
16325  partInit.code() = std::string("//c.sw\n")+
16326  "etiss_uint32 exception = 0;\n"
16327  "etiss_uint32 temp = 0;\n"
16328  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16329  #if RISCV64_Pipeline1
16330  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16331  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16332  "etiss_uint32 num_stages = 4;\n"
16333  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16334  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16335  #endif
16336  #if RISCV64_Pipeline2
16337  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16338  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16339  "etiss_uint32 num_stages = 4;\n"
16340  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16341  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16342  #endif
16343 
16344  "etiss_uint64 offs = 0;\n"
16345 
16346 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n"
16347 #if RISCV64_DEBUG_CALL
16348 "printf(\"offs = %#lx\\n\",offs); \n"
16349 #endif
16350  "etiss_uint32 MEM_offs;\n"
16351 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
16352 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + " + 8];\n"
16353 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
16354 #if RISCV64_DEBUG_CALL
16355 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
16356 #endif
16357 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
16358 "{\n"
16359  "((RISCV64*)cpu)->RES = 0;\n"
16360  #if RISCV64_DEBUG_CALL
16361  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
16362  #endif
16363 "}\n"
16364 
16365 
16366  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16367 
16368  "return exception;\n"
16369 ;
16370 return true;
16371 },
16372 0,
16373 nullptr
16374 );
16375 //-------------------------------------------------------------------------------------------------------------------
16376 static InstructionDefinition c_beqz_8_rs1_imm(
16377  ISA16_RISCV64,
16378  "c.beqz",
16379  (uint16_t)0xc001,
16380  (uint16_t) 0xe003,
16381  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16382  {
16383  etiss_uint64 rs1 = 0;
16384  static BitArrayRange R_rs1_0 (9,7);
16385  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
16386  rs1 += rs1_0;
16387  etiss_int64 imm = 0;
16388  static BitArrayRange R_imm_8 (12,12);
16389  etiss_int64 imm_8 = R_imm_8.read(ba);
16390  imm += imm_8<<8;
16391  static BitArrayRange R_imm_3 (11,10);
16392  etiss_int64 imm_3 = R_imm_3.read(ba);
16393  imm += imm_3<<3;
16394  static BitArrayRange R_imm_6 (6,5);
16395  etiss_int64 imm_6 = R_imm_6.read(ba);
16396  imm += imm_6<<6;
16397  static BitArrayRange R_imm_1 (4,3);
16398  etiss_int64 imm_1 = R_imm_1.read(ba);
16399  imm += imm_1<<1;
16400  static BitArrayRange R_imm_5 (2,2);
16401  etiss_int64 imm_5 = R_imm_5.read(ba);
16402  imm += imm_5<<5;
16403  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16404  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
16405  partInit.getAffectedRegisters().add("instructionPointer",64);
16406  partInit.code() = std::string("//c.beqz\n")+
16407  "etiss_uint32 temp = 0;\n"
16408  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16409  #if RISCV64_Pipeline1
16410  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16411  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16412  "etiss_uint32 num_stages = 4;\n"
16413  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16414  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16415  #endif
16416  #if RISCV64_Pipeline2
16417  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16418  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16419  "etiss_uint32 num_stages = 4;\n"
16420  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16421  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16422  #endif
16423 
16424  "etiss_int64 imm_extended = 0;\n"
16425  "etiss_int64 choose1 = 0;\n"
16426 
16427 "if((" + toString(imm) + " & 0x100)>>8 == 0)\n"
16428 "{\n"
16429  "imm_extended = 0;\n"
16430  #if RISCV64_DEBUG_CALL
16431  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16432  #endif
16433 "}\n"
16434 
16435 "else\n"
16436 "{\n"
16437  "imm_extended = 4294967295;\n"
16438  #if RISCV64_DEBUG_CALL
16439  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16440  #endif
16441  "imm_extended = (imm_extended << 32);\n"
16442  #if RISCV64_DEBUG_CALL
16443  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16444  #endif
16445  "imm_extended = imm_extended + 4294966784;\n"
16446  #if RISCV64_DEBUG_CALL
16447  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16448  #endif
16449 "}\n"
16450 "imm_extended = imm_extended + " + toString(imm) + ";\n"
16451 #if RISCV64_DEBUG_CALL
16452 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16453 #endif
16454 "if(*((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] == 0)\n"
16455 "{\n"
16456  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
16457  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
16458  "{\n"
16459  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
16460  "}\n"
16461  "choose1 = (etiss_int64)cast_0 + imm_extended;\n"
16462  #if RISCV64_DEBUG_CALL
16463  "printf(\"choose1 = %#lx\\n\",choose1); \n"
16464  #endif
16465 // Explicit assignment to PC
16466 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16467 "}\n"
16468 
16469 "else\n"
16470 "{\n"
16471  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 2;\n"
16472  #if RISCV64_DEBUG_CALL
16473  "printf(\"choose1 = %#lx\\n\",choose1); \n"
16474  #endif
16475 "}\n"
16476 "cpu->instructionPointer = choose1;\n"
16477 #if RISCV64_DEBUG_CALL
16478 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
16479 #endif
16480 
16481  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
16482 
16483  "return 0;\n"
16484 ;
16485 return true;
16486 },
16487 0,
16488 nullptr
16489 );
16490 //-------------------------------------------------------------------------------------------------------------------
16491 static InstructionDefinition c_swsp_rs2_uimm_sp_(
16492  ISA16_RISCV64,
16493  "c.swsp",
16494  (uint16_t)0xc002,
16495  (uint16_t) 0xe003,
16496  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16497  {
16498  etiss_uint64 rs2 = 0;
16499  static BitArrayRange R_rs2_0 (6,2);
16500  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
16501  rs2 += rs2_0;
16502  etiss_uint64 uimm = 0;
16503  static BitArrayRange R_uimm_2 (12,9);
16504  etiss_uint64 uimm_2 = R_uimm_2.read(ba);
16505  uimm += uimm_2<<2;
16506  static BitArrayRange R_uimm_6 (8,7);
16507  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
16508  uimm += uimm_6<<6;
16509  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16510  partInit.getRegisterDependencies().add(reg_name[rs2],64);
16511  partInit.getRegisterDependencies().add(reg_name[2],64);
16512  partInit.getAffectedRegisters().add("instructionPointer",64);
16513  partInit.code() = std::string("//c.swsp\n")+
16514  "etiss_uint32 exception = 0;\n"
16515  "etiss_uint32 temp = 0;\n"
16516  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16517  #if RISCV64_Pipeline1
16518  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16519  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16520  "etiss_uint32 num_stages = 4;\n"
16521  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16522  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16523  #endif
16524  #if RISCV64_Pipeline2
16525  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16526  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16527  "etiss_uint32 num_stages = 4;\n"
16528  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16529  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16530  #endif
16531 
16532  "etiss_uint64 offs = 0;\n"
16533 
16534 "offs = *((RISCV64*)cpu)->X[2] + " + toString(uimm) + ";\n"
16535 #if RISCV64_DEBUG_CALL
16536 "printf(\"offs = %#lx\\n\",offs); \n"
16537 #endif
16538  "etiss_uint32 MEM_offs;\n"
16539 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
16540 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
16541 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n"
16542 #if RISCV64_DEBUG_CALL
16543 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
16544 #endif
16545 "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
16546 "{\n"
16547  "((RISCV64*)cpu)->RES = 0;\n"
16548  #if RISCV64_DEBUG_CALL
16549  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
16550  #endif
16551 "}\n"
16552 
16553 
16554  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16555 
16556  "return exception;\n"
16557 ;
16558 return true;
16559 },
16560 0,
16561 nullptr
16562 );
16563 //-------------------------------------------------------------------------------------------------------------------
16564 static InstructionDefinition c_addiw_rs1_imm(
16565  ISA16_RISCV64,
16566  "c.addiw",
16567  (uint16_t)0x2001,
16568  (uint16_t) 0xe003,
16569  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16570  {
16571  etiss_uint64 rs1 = 0;
16572  static BitArrayRange R_rs1_0 (11,7);
16573  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
16574  rs1 += rs1_0;
16575  etiss_int64 imm = 0;
16576  static BitArrayRange R_imm_5 (12,12);
16577  etiss_int64 imm_5 = R_imm_5.read(ba);
16578  imm += imm_5<<5;
16579  static BitArrayRange R_imm_0 (6,2);
16580  etiss_int64 imm_0 = R_imm_0.read(ba);
16581  imm += imm_0;
16582  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16583  partInit.getRegisterDependencies().add(reg_name[rs1],64);
16584  partInit.getAffectedRegisters().add(reg_name[rs1],64);
16585  partInit.getAffectedRegisters().add("instructionPointer",64);
16586  partInit.code() = std::string("//c.addiw\n")+
16587  "etiss_uint32 temp = 0;\n"
16588  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16589  #if RISCV64_Pipeline1
16590  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16591  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16592  "etiss_uint32 num_stages = 4;\n"
16593  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16594  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16595  #endif
16596  #if RISCV64_Pipeline2
16597  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16598  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16599  "etiss_uint32 num_stages = 4;\n"
16600  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16601  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16602  #endif
16603 
16604  "etiss_int64 imm_extended = 0;\n"
16605  "etiss_int32 res = 0;\n"
16606 
16607 "if((" + toString(imm) + " & 0x20)>>5 == 0)\n"
16608 "{\n"
16609  "imm_extended = 0;\n"
16610  #if RISCV64_DEBUG_CALL
16611  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16612  #endif
16613 "}\n"
16614 
16615 "else\n"
16616 "{\n"
16617  "imm_extended = 4294967295;\n"
16618  #if RISCV64_DEBUG_CALL
16619  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16620  #endif
16621  "imm_extended = (imm_extended << 32);\n"
16622  #if RISCV64_DEBUG_CALL
16623  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16624  #endif
16625  "imm_extended = imm_extended + 4294967232;\n"
16626  #if RISCV64_DEBUG_CALL
16627  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16628  #endif
16629 "}\n"
16630 "imm_extended = imm_extended + " + toString(imm) + ";\n"
16631 #if RISCV64_DEBUG_CALL
16632 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16633 #endif
16634 "if(" + toString(rs1) + " != 0)\n"
16635 "{\n"
16636  "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n"
16637  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
16638  "{\n"
16639  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
16640  "}\n"
16641  "res = (etiss_int32)cast_0 + imm_extended;\n"
16642  #if RISCV64_DEBUG_CALL
16643  "printf(\"res = %#x\\n\",res); \n"
16644  #endif
16645  "etiss_int32 cast_1 = res; \n"
16646  "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n"
16647  "{\n"
16648  "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n"
16649  "}\n"
16650  "*((RISCV64*)cpu)->X[" + toString(rs1) + "] = (etiss_int64)cast_1;\n"
16651  #if RISCV64_DEBUG_CALL
16652  "printf(\"*((RISCV64*)cpu)->X[" + toString(rs1) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rs1) + "]); \n"
16653  #endif
16654 "}\n"
16655 
16656 
16657  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16658 
16659 ;
16660 return true;
16661 },
16662 0,
16663 nullptr
16664 );
16665 //-------------------------------------------------------------------------------------------------------------------
16666 static InstructionDefinition c_fld_rd_uimm_8_rs1_(
16667  ISA16_RISCV64,
16668  "c.fld",
16669  (uint16_t)0x2000,
16670  (uint16_t) 0xe003,
16671  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16672  {
16673  etiss_uint64 rs1 = 0;
16674  static BitArrayRange R_rs1_0 (9,7);
16675  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
16676  rs1 += rs1_0;
16677  etiss_uint64 uimm = 0;
16678  static BitArrayRange R_uimm_3 (12,10);
16679  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
16680  uimm += uimm_3<<3;
16681  static BitArrayRange R_uimm_6 (6,5);
16682  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
16683  uimm += uimm_6<<6;
16684  etiss_uint64 rd = 0;
16685  static BitArrayRange R_rd_0 (4,2);
16686  etiss_uint64 rd_0 = R_rd_0.read(ba);
16687  rd += rd_0;
16688  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16689  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
16690  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
16691  partInit.getAffectedRegisters().add("instructionPointer",64);
16692  partInit.code() = std::string("//c.fld\n")+
16693  "etiss_uint32 exception = 0;\n"
16694  "etiss_uint32 temp = 0;\n"
16695  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16696  #if RISCV64_Pipeline1
16697  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16698  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16699  "etiss_uint32 num_stages = 4;\n"
16700  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16701  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16702  #endif
16703  #if RISCV64_Pipeline2
16704  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16705  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16706  "etiss_uint32 num_stages = 4;\n"
16707  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16708  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16709  #endif
16710 
16711  "etiss_uint64 offs = 0;\n"
16712  "etiss_uint64 res = 0;\n"
16713  "etiss_int64 upper = 0;\n"
16714 
16715 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n"
16716 #if RISCV64_DEBUG_CALL
16717 "printf(\"offs = %#lx\\n\",offs); \n"
16718 #endif
16719  "etiss_uint64 MEM_offs;\n"
16720 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
16721 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
16722 "res = MEM_offs;\n"
16723 #if RISCV64_DEBUG_CALL
16724 "printf(\"res = %#lx\\n\",res); \n"
16725 #endif
16726 "if(64 == 64)\n"
16727 "{\n"
16728  "((RISCV64*)cpu)->F[" + toString(rd) + " + 8] = res;\n"
16729  #if RISCV64_DEBUG_CALL
16730  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + " + 8] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + " + 8]); \n"
16731  #endif
16732 "}\n"
16733 
16734 "else\n"
16735 "{\n"
16736  "upper = - 1;\n"
16737  #if RISCV64_DEBUG_CALL
16738  "printf(\"upper = %#lx\\n\",upper); \n"
16739  #endif
16740  "((RISCV64*)cpu)->F[" + toString(rd) + " + 8] = ((upper << 64) | res);\n"
16741  #if RISCV64_DEBUG_CALL
16742  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + " + 8] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + " + 8]); \n"
16743  #endif
16744 "}\n"
16745 
16746  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16747 
16748  "return exception;\n"
16749 ;
16750 return true;
16751 },
16752 0,
16753 nullptr
16754 );
16755 //-------------------------------------------------------------------------------------------------------------------
16756 static InstructionDefinition c_fldsp_rd_uimm_x2_(
16757  ISA16_RISCV64,
16758  "c.fldsp",
16759  (uint16_t)0x2002,
16760  (uint16_t) 0xe003,
16761  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16762  {
16763  etiss_uint64 uimm = 0;
16764  static BitArrayRange R_uimm_5 (12,12);
16765  etiss_uint64 uimm_5 = R_uimm_5.read(ba);
16766  uimm += uimm_5<<5;
16767  static BitArrayRange R_uimm_3 (6,5);
16768  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
16769  uimm += uimm_3<<3;
16770  static BitArrayRange R_uimm_6 (4,2);
16771  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
16772  uimm += uimm_6<<6;
16773  etiss_uint64 rd = 0;
16774  static BitArrayRange R_rd_0 (11,7);
16775  etiss_uint64 rd_0 = R_rd_0.read(ba);
16776  rd += rd_0;
16777  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16778  partInit.getRegisterDependencies().add(reg_name[2],64);
16779  partInit.getAffectedRegisters().add(reg_name[rd],64);
16780  partInit.getAffectedRegisters().add("instructionPointer",64);
16781  partInit.code() = std::string("//c.fldsp\n")+
16782  "etiss_uint32 exception = 0;\n"
16783  "etiss_uint32 temp = 0;\n"
16784  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16785  #if RISCV64_Pipeline1
16786  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16787  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16788  "etiss_uint32 num_stages = 4;\n"
16789  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16790  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16791  #endif
16792  #if RISCV64_Pipeline2
16793  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16794  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16795  "etiss_uint32 num_stages = 4;\n"
16796  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16797  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16798  #endif
16799 
16800  "etiss_uint64 offs = 0;\n"
16801  "etiss_uint64 res = 0;\n"
16802  "etiss_int64 upper = 0;\n"
16803 
16804 "offs = *((RISCV64*)cpu)->X[2] + " + toString(uimm) + ";\n"
16805 #if RISCV64_DEBUG_CALL
16806 "printf(\"offs = %#lx\\n\",offs); \n"
16807 #endif
16808  "etiss_uint64 MEM_offs;\n"
16809 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
16810 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
16811 "res = MEM_offs;\n"
16812 #if RISCV64_DEBUG_CALL
16813 "printf(\"res = %#lx\\n\",res); \n"
16814 #endif
16815 "if(64 == 64)\n"
16816 "{\n"
16817  "((RISCV64*)cpu)->F[" + toString(rd) + "] = res;\n"
16818  #if RISCV64_DEBUG_CALL
16819  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
16820  #endif
16821 "}\n"
16822 
16823 "else\n"
16824 "{\n"
16825  "upper = - 1;\n"
16826  #if RISCV64_DEBUG_CALL
16827  "printf(\"upper = %#lx\\n\",upper); \n"
16828  #endif
16829  "((RISCV64*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | (etiss_uint64)res);\n"
16830  #if RISCV64_DEBUG_CALL
16831  "printf(\"((RISCV64*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV64*)cpu)->F[" + toString(rd) + "]); \n"
16832  #endif
16833 "}\n"
16834 
16835  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16836 
16837  "return exception;\n"
16838 ;
16839 return true;
16840 },
16841 0,
16842 nullptr
16843 );
16844 //-------------------------------------------------------------------------------------------------------------------
16845 static InstructionDefinition c_lui_rd_imm(
16846  ISA16_RISCV64,
16847  "c.lui",
16848  (uint16_t)0x6001,
16849  (uint16_t) 0xe003,
16850  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16851  {
16852  etiss_uint64 rd = 0;
16853  static BitArrayRange R_rd_0 (11,7);
16854  etiss_uint64 rd_0 = R_rd_0.read(ba);
16855  rd += rd_0;
16856  etiss_uint64 imm = 0;
16857  static BitArrayRange R_imm_17 (12,12);
16858  etiss_uint64 imm_17 = R_imm_17.read(ba);
16859  imm += imm_17<<17;
16860  static BitArrayRange R_imm_12 (6,2);
16861  etiss_int64 imm_12 = R_imm_12.read(ba);
16862  imm += imm_12<<12;
16863  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16864  partInit.getAffectedRegisters().add(reg_name[rd],64);
16865  partInit.getAffectedRegisters().add("instructionPointer",64);
16866  partInit.code() = std::string("//c.lui\n")+
16867  "etiss_uint32 exception = 0;\n"
16868  "etiss_uint32 temp = 0;\n"
16869  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16870  #if RISCV64_Pipeline1
16871  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16872  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16873  "etiss_uint32 num_stages = 4;\n"
16874  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16875  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16876  #endif
16877  #if RISCV64_Pipeline2
16878  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16879  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16880  "etiss_uint32 num_stages = 4;\n"
16881  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16882  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16883  #endif
16884 
16885  "etiss_int64 imm_extended = 0;\n"
16886 
16887 "if((" + toString(imm) + " & 0x20000)>>17 == 0)\n"
16888 "{\n"
16889  "imm_extended = 0;\n"
16890  #if RISCV64_DEBUG_CALL
16891  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16892  #endif
16893 "}\n"
16894 
16895 "else\n"
16896 "{\n"
16897  "imm_extended = 4294967295;\n"
16898  #if RISCV64_DEBUG_CALL
16899  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16900  #endif
16901  "imm_extended = (imm_extended << 32);\n"
16902  #if RISCV64_DEBUG_CALL
16903  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16904  #endif
16905  "imm_extended = imm_extended + 4294705152;\n"
16906  #if RISCV64_DEBUG_CALL
16907  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16908  #endif
16909 "}\n"
16910 "imm_extended = imm_extended + " + toString(imm) + ";\n"
16911 #if RISCV64_DEBUG_CALL
16912 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
16913 #endif
16914 "if(" + toString(rd) + " == 0)\n"
16915 "{\n"
16916  "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n"
16917 "}\n"
16918 
16919 "if(imm_extended == 0)\n"
16920 "{\n"
16921  "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n"
16922 "}\n"
16923 
16924 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = imm_extended;\n"
16925 #if RISCV64_DEBUG_CALL
16926 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
16927 #endif
16928 
16929  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
16930 
16931  "return exception;\n"
16932 ;
16933 return true;
16934 },
16935 0,
16936 nullptr
16937 );
16938 //-------------------------------------------------------------------------------------------------------------------
16939 static InstructionDefinition c_addi16sp_imm(
16940  ISA16_RISCV64,
16941  "c.addi16sp",
16942  (uint16_t)0x6101,
16943  (uint16_t) 0xef83,
16944  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
16945  {
16946  etiss_int64 imm = 0;
16947  static BitArrayRange R_imm_9 (12,12);
16948  etiss_int64 imm_9 = R_imm_9.read(ba);
16949  imm += imm_9<<9;
16950  static BitArrayRange R_imm_4 (6,6);
16951  etiss_int64 imm_4 = R_imm_4.read(ba);
16952  imm += imm_4<<4;
16953  static BitArrayRange R_imm_6 (5,5);
16954  etiss_int64 imm_6 = R_imm_6.read(ba);
16955  imm += imm_6<<6;
16956  static BitArrayRange R_imm_7 (4,3);
16957  etiss_int64 imm_7 = R_imm_7.read(ba);
16958  imm += imm_7<<7;
16959  static BitArrayRange R_imm_5 (2,2);
16960  etiss_int64 imm_5 = R_imm_5.read(ba);
16961  imm += imm_5<<5;
16962  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
16963  partInit.getRegisterDependencies().add(reg_name[2],64);
16964  partInit.getAffectedRegisters().add(reg_name[2],64);
16965  partInit.getAffectedRegisters().add("instructionPointer",64);
16966  partInit.code() = std::string("//c.addi16sp\n")+
16967  "etiss_uint32 temp = 0;\n"
16968  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
16969  #if RISCV64_Pipeline1
16970  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16971  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16972  "etiss_uint32 num_stages = 4;\n"
16973  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16974  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16975  #endif
16976  #if RISCV64_Pipeline2
16977  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
16978  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
16979  "etiss_uint32 num_stages = 4;\n"
16980  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
16981  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
16982  #endif
16983 
16984  "etiss_int64 imm_extended = 0;\n"
16985 
16986 "if((" + toString(imm) + " & 0x200)>>9 == 0)\n"
16987 "{\n"
16988  "imm_extended = 0;\n"
16989  #if RISCV64_DEBUG_CALL
16990  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16991  #endif
16992 "}\n"
16993 
16994 "else\n"
16995 "{\n"
16996  "imm_extended = 4294967295;\n"
16997  #if RISCV64_DEBUG_CALL
16998  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
16999  #endif
17000  "imm_extended = (imm_extended << 32);\n"
17001  #if RISCV64_DEBUG_CALL
17002  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
17003  #endif
17004  "imm_extended = imm_extended + 4294966272;\n"
17005  #if RISCV64_DEBUG_CALL
17006  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
17007  #endif
17008 "}\n"
17009 "imm_extended = imm_extended + " + toString(imm) + ";\n"
17010 #if RISCV64_DEBUG_CALL
17011 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
17012 #endif
17013 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[2]; \n"
17014 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
17015 "{\n"
17016  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
17017 "}\n"
17018 "*((RISCV64*)cpu)->X[2] = (etiss_int64)cast_0 + imm_extended;\n"
17019 #if RISCV64_DEBUG_CALL
17020 "printf(\"*((RISCV64*)cpu)->X[2] = %#lx\\n\",*((RISCV64*)cpu)->X[2]); \n"
17021 #endif
17022 
17023  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17024 
17025 ;
17026 return true;
17027 },
17028 0,
17029 nullptr
17030 );
17031 //-------------------------------------------------------------------------------------------------------------------
17032 static InstructionDefinition c_ld_8_rd_uimm_8_rs1_(
17033  ISA16_RISCV64,
17034  "c.ld",
17035  (uint16_t)0x6000,
17036  (uint16_t) 0xe003,
17037  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17038  {
17039  etiss_uint64 rs1 = 0;
17040  static BitArrayRange R_rs1_0 (9,7);
17041  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
17042  rs1 += rs1_0;
17043  etiss_uint64 uimm = 0;
17044  static BitArrayRange R_uimm_3 (12,10);
17045  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
17046  uimm += uimm_3<<3;
17047  static BitArrayRange R_uimm_6 (6,5);
17048  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
17049  uimm += uimm_6<<6;
17050  etiss_uint64 rd = 0;
17051  static BitArrayRange R_rd_0 (4,2);
17052  etiss_uint64 rd_0 = R_rd_0.read(ba);
17053  rd += rd_0;
17054  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17055  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
17056  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17057  partInit.getAffectedRegisters().add("instructionPointer",64);
17058  partInit.code() = std::string("//c.ld\n")+
17059  "etiss_uint32 exception = 0;\n"
17060  "etiss_uint32 temp = 0;\n"
17061  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17062  #if RISCV64_Pipeline1
17063  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17064  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17065  "etiss_uint32 num_stages = 4;\n"
17066  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17067  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17068  #endif
17069  #if RISCV64_Pipeline2
17070  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17071  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17072  "etiss_uint32 num_stages = 4;\n"
17073  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17074  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17075  #endif
17076 
17077  "etiss_uint64 offs = 0;\n"
17078 
17079 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n"
17080 #if RISCV64_DEBUG_CALL
17081 "printf(\"offs = %#lx\\n\",offs); \n"
17082 #endif
17083  "etiss_uint64 MEM_offs;\n"
17084 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
17085 "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
17086 "etiss_int64 cast_0 = MEM_offs; \n"
17087 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
17088 "{\n"
17089  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
17090 "}\n"
17091 "*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = (etiss_int64)cast_0;\n"
17092 #if RISCV64_DEBUG_CALL
17093 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + " + 8]); \n"
17094 #endif
17095 
17096  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17097 
17098  "return exception;\n"
17099 ;
17100 return true;
17101 },
17102 0,
17103 nullptr
17104 );
17105 //-------------------------------------------------------------------------------------------------------------------
17106 static InstructionDefinition c_ldsp_rd_uimm_sp_(
17107  ISA16_RISCV64,
17108  "c.ldsp",
17109  (uint16_t)0x6002,
17110  (uint16_t) 0xe003,
17111  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17112  {
17113  etiss_uint64 uimm = 0;
17114  static BitArrayRange R_uimm_5 (12,12);
17115  etiss_uint64 uimm_5 = R_uimm_5.read(ba);
17116  uimm += uimm_5<<5;
17117  static BitArrayRange R_uimm_3 (6,5);
17118  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
17119  uimm += uimm_3<<3;
17120  static BitArrayRange R_uimm_6 (4,2);
17121  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
17122  uimm += uimm_6<<6;
17123  etiss_uint64 rd = 0;
17124  static BitArrayRange R_rd_0 (11,7);
17125  etiss_uint64 rd_0 = R_rd_0.read(ba);
17126  rd += rd_0;
17127  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17128  partInit.getRegisterDependencies().add(reg_name[2],64);
17129  partInit.getAffectedRegisters().add(reg_name[rd],64);
17130  partInit.getAffectedRegisters().add("instructionPointer",64);
17131  partInit.code() = std::string("//c.ldsp\n")+
17132  "etiss_uint32 exception = 0;\n"
17133  "etiss_uint32 temp = 0;\n"
17134  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17135  #if RISCV64_Pipeline1
17136  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17137  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17138  "etiss_uint32 num_stages = 4;\n"
17139  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17140  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17141  #endif
17142  #if RISCV64_Pipeline2
17143  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17144  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17145  "etiss_uint32 num_stages = 4;\n"
17146  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17147  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17148  #endif
17149 
17150  "etiss_uint64 offs = 0;\n"
17151 
17152 "offs = *((RISCV64*)cpu)->X[2] + " + toString(uimm) + ";\n"
17153 #if RISCV64_DEBUG_CALL
17154 "printf(\"offs = %#lx\\n\",offs); \n"
17155 #endif
17156 "if(" + toString(rd) + " != 0)\n"
17157 "{\n"
17158  "etiss_uint64 MEM_offs;\n"
17159  "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
17160  "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n"
17161  "etiss_int64 cast_0 = MEM_offs; \n"
17162  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
17163  "{\n"
17164  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
17165  "}\n"
17166  "*((RISCV64*)cpu)->X[" + toString(rd) + "] = (etiss_int64)cast_0;\n"
17167  #if RISCV64_DEBUG_CALL
17168  "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
17169  #endif
17170 "}\n"
17171 
17172 
17173  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17174 
17175  "return exception;\n"
17176 ;
17177 return true;
17178 },
17179 0,
17180 nullptr
17181 );
17182 //-------------------------------------------------------------------------------------------------------------------
17183 static InstructionDefinition c_srli_8_rs1_shamt(
17184  ISA16_RISCV64,
17185  "c.srli",
17186  (uint16_t)0x8001,
17187  (uint16_t) 0xec03,
17188  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17189  {
17190  etiss_uint64 rs1 = 0;
17191  static BitArrayRange R_rs1_0 (9,7);
17192  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
17193  rs1 += rs1_0;
17194  etiss_uint64 shamt = 0;
17195  static BitArrayRange R_shamt_5 (12,12);
17196  etiss_uint64 shamt_5 = R_shamt_5.read(ba);
17197  shamt += shamt_5<<5;
17198  static BitArrayRange R_shamt_0 (6,2);
17199  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
17200  shamt += shamt_0;
17201  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17202  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
17203  partInit.getAffectedRegisters().add(reg_name[rs1+8],64);
17204  partInit.getAffectedRegisters().add("instructionPointer",64);
17205  partInit.code() = std::string("//c.srli\n")+
17206  "etiss_uint32 temp = 0;\n"
17207  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17208  #if RISCV64_Pipeline1
17209  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17210  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17211  "etiss_uint32 num_stages = 4;\n"
17212  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17213  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17214  #endif
17215  #if RISCV64_Pipeline2
17216  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17217  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17218  "etiss_uint32 num_stages = 4;\n"
17219  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17220  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17221  #endif
17222 
17223  "etiss_int8 rs1_idx = 0;\n"
17224 
17225 "rs1_idx = " + toString(rs1) + " + 8;\n"
17226 #if RISCV64_DEBUG_CALL
17227 "printf(\"rs1_idx = %#x\\n\",rs1_idx); \n"
17228 #endif
17229 "*((RISCV64*)cpu)->X[rs1_idx] = (*((RISCV64*)cpu)->X[rs1_idx] >> " + toString(shamt) + ");\n"
17230 #if RISCV64_DEBUG_CALL
17231 "printf(\"*((RISCV64*)cpu)->X[rs1_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rs1_idx]); \n"
17232 #endif
17233 
17234  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17235 
17236 ;
17237 return true;
17238 },
17239 0,
17240 nullptr
17241 );
17242 //-------------------------------------------------------------------------------------------------------------------
17243 static InstructionDefinition c_srai_8_rs1_shamt(
17244  ISA16_RISCV64,
17245  "c.srai",
17246  (uint16_t)0x8401,
17247  (uint16_t) 0xec03,
17248  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17249  {
17250  etiss_uint64 rs1 = 0;
17251  static BitArrayRange R_rs1_0 (9,7);
17252  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
17253  rs1 += rs1_0;
17254  etiss_uint64 shamt = 0;
17255  static BitArrayRange R_shamt_5 (12,12);
17256  etiss_uint64 shamt_5 = R_shamt_5.read(ba);
17257  shamt += shamt_5<<5;
17258  static BitArrayRange R_shamt_0 (6,2);
17259  etiss_uint64 shamt_0 = R_shamt_0.read(ba);
17260  shamt += shamt_0;
17261  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17262  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
17263  partInit.getAffectedRegisters().add(reg_name[rs1+8],64);
17264  partInit.getAffectedRegisters().add("instructionPointer",64);
17265  partInit.code() = std::string("//c.srai\n")+
17266  "etiss_uint32 temp = 0;\n"
17267  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17268  #if RISCV64_Pipeline1
17269  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17270  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17271  "etiss_uint32 num_stages = 4;\n"
17272  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17273  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17274  #endif
17275  #if RISCV64_Pipeline2
17276  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17277  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17278  "etiss_uint32 num_stages = 4;\n"
17279  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17280  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17281  #endif
17282 
17283  "etiss_int8 rs1_idx = 0;\n"
17284 
17285 "rs1_idx = " + toString(rs1) + " + 8;\n"
17286 #if RISCV64_DEBUG_CALL
17287 "printf(\"rs1_idx = %#x\\n\",rs1_idx); \n"
17288 #endif
17289 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[rs1_idx]; \n"
17290 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
17291 "{\n"
17292  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
17293 "}\n"
17294 "*((RISCV64*)cpu)->X[rs1_idx] = ((etiss_int64)cast_0 >> " + toString(shamt) + ");\n"
17295 #if RISCV64_DEBUG_CALL
17296 "printf(\"*((RISCV64*)cpu)->X[rs1_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rs1_idx]); \n"
17297 #endif
17298 
17299  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17300 
17301 ;
17302 return true;
17303 },
17304 0,
17305 nullptr
17306 );
17307 //-------------------------------------------------------------------------------------------------------------------
17308 static InstructionDefinition c_andi_8_rs1_imm(
17309  ISA16_RISCV64,
17310  "c.andi",
17311  (uint16_t)0x8801,
17312  (uint16_t) 0xec03,
17313  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17314  {
17315  etiss_uint64 rs1 = 0;
17316  static BitArrayRange R_rs1_0 (9,7);
17317  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
17318  rs1 += rs1_0;
17319  etiss_int64 imm = 0;
17320  static BitArrayRange R_imm_5 (12,12);
17321  etiss_int64 imm_5 = R_imm_5.read(ba);
17322  imm += imm_5<<5;
17323  static BitArrayRange R_imm_0 (6,2);
17324  etiss_int64 imm_0 = R_imm_0.read(ba);
17325  imm += imm_0;
17326  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17327  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
17328  partInit.getAffectedRegisters().add(reg_name[rs1+8],64);
17329  partInit.getAffectedRegisters().add("instructionPointer",64);
17330  partInit.code() = std::string("//c.andi\n")+
17331  "etiss_uint32 temp = 0;\n"
17332  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17333  #if RISCV64_Pipeline1
17334  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17335  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17336  "etiss_uint32 num_stages = 4;\n"
17337  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17338  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17339  #endif
17340  #if RISCV64_Pipeline2
17341  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17342  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17343  "etiss_uint32 num_stages = 4;\n"
17344  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17345  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17346  #endif
17347 
17348  "etiss_int64 imm_extended = 0;\n"
17349  "etiss_int8 rs1_idx = 0;\n"
17350 
17351 "if((" + toString(imm) + " & 0x20)>>5 == 0)\n"
17352 "{\n"
17353  "imm_extended = 0;\n"
17354  #if RISCV64_DEBUG_CALL
17355  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
17356  #endif
17357 "}\n"
17358 
17359 "else\n"
17360 "{\n"
17361  "imm_extended = 4294967295;\n"
17362  #if RISCV64_DEBUG_CALL
17363  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
17364  #endif
17365  "imm_extended = (imm_extended << 32);\n"
17366  #if RISCV64_DEBUG_CALL
17367  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
17368  #endif
17369  "imm_extended = imm_extended + 4294967232;\n"
17370  #if RISCV64_DEBUG_CALL
17371  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
17372  #endif
17373 "}\n"
17374 "imm_extended = imm_extended + " + toString(imm) + ";\n"
17375 #if RISCV64_DEBUG_CALL
17376 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
17377 #endif
17378 "rs1_idx = " + toString(rs1) + " + 8;\n"
17379 #if RISCV64_DEBUG_CALL
17380 "printf(\"rs1_idx = %#x\\n\",rs1_idx); \n"
17381 #endif
17382 "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[rs1_idx]; \n"
17383 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
17384 "{\n"
17385  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
17386 "}\n"
17387 "*((RISCV64*)cpu)->X[rs1_idx] = ((etiss_int64)cast_0 & imm_extended);\n"
17388 #if RISCV64_DEBUG_CALL
17389 "printf(\"*((RISCV64*)cpu)->X[rs1_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rs1_idx]); \n"
17390 #endif
17391 
17392  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17393 
17394 ;
17395 return true;
17396 },
17397 0,
17398 nullptr
17399 );
17400 //-------------------------------------------------------------------------------------------------------------------
17401 static InstructionDefinition c_sub_8_rd_8_rs2(
17402  ISA16_RISCV64,
17403  "c.sub",
17404  (uint16_t)0x8c01,
17405  (uint16_t) 0xfc63,
17406  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17407  {
17408  etiss_uint64 rs2 = 0;
17409  static BitArrayRange R_rs2_0 (4,2);
17410  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17411  rs2 += rs2_0;
17412  etiss_uint64 rd = 0;
17413  static BitArrayRange R_rd_0 (9,7);
17414  etiss_uint64 rd_0 = R_rd_0.read(ba);
17415  rd += rd_0;
17416  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17417  partInit.getRegisterDependencies().add(reg_name[rd+8],64);
17418  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
17419  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17420  partInit.getAffectedRegisters().add("instructionPointer",64);
17421  partInit.code() = std::string("//c.sub\n")+
17422  "etiss_uint32 temp = 0;\n"
17423  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17424  #if RISCV64_Pipeline1
17425  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17426  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17427  "etiss_uint32 num_stages = 4;\n"
17428  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17429  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17430  #endif
17431  #if RISCV64_Pipeline2
17432  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17433  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17434  "etiss_uint32 num_stages = 4;\n"
17435  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17436  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17437  #endif
17438 
17439  "etiss_int8 rd_idx = 0;\n"
17440 
17441 "rd_idx = " + toString(rd) + " + 8;\n"
17442 #if RISCV64_DEBUG_CALL
17443 "printf(\"rd_idx = %#x\\n\",rd_idx); \n"
17444 #endif
17445 "*((RISCV64*)cpu)->X[rd_idx] = *((RISCV64*)cpu)->X[rd_idx] - *((RISCV64*)cpu)->X[" + toString(rs2) + " + 8];\n"
17446 #if RISCV64_DEBUG_CALL
17447 "printf(\"*((RISCV64*)cpu)->X[rd_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rd_idx]); \n"
17448 #endif
17449 
17450  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17451 
17452 ;
17453 return true;
17454 },
17455 0,
17456 nullptr
17457 );
17458 //-------------------------------------------------------------------------------------------------------------------
17459 static InstructionDefinition c_xor_8_rd_8_rs2(
17460  ISA16_RISCV64,
17461  "c.xor",
17462  (uint16_t)0x8c21,
17463  (uint16_t) 0xfc63,
17464  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17465  {
17466  etiss_uint64 rs2 = 0;
17467  static BitArrayRange R_rs2_0 (4,2);
17468  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17469  rs2 += rs2_0;
17470  etiss_uint64 rd = 0;
17471  static BitArrayRange R_rd_0 (9,7);
17472  etiss_uint64 rd_0 = R_rd_0.read(ba);
17473  rd += rd_0;
17474  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17475  partInit.getRegisterDependencies().add(reg_name[rd+8],64);
17476  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
17477  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17478  partInit.getAffectedRegisters().add("instructionPointer",64);
17479  partInit.code() = std::string("//c.xor\n")+
17480  "etiss_uint32 temp = 0;\n"
17481  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17482  #if RISCV64_Pipeline1
17483  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17484  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17485  "etiss_uint32 num_stages = 4;\n"
17486  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17487  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17488  #endif
17489  #if RISCV64_Pipeline2
17490  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17491  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17492  "etiss_uint32 num_stages = 4;\n"
17493  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17494  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17495  #endif
17496 
17497  "etiss_int8 rd_idx = 0;\n"
17498 
17499 "rd_idx = " + toString(rd) + " + 8;\n"
17500 #if RISCV64_DEBUG_CALL
17501 "printf(\"rd_idx = %#x\\n\",rd_idx); \n"
17502 #endif
17503 "*((RISCV64*)cpu)->X[rd_idx] = (*((RISCV64*)cpu)->X[rd_idx] ^ *((RISCV64*)cpu)->X[" + toString(rs2) + " + 8]);\n"
17504 #if RISCV64_DEBUG_CALL
17505 "printf(\"*((RISCV64*)cpu)->X[rd_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rd_idx]); \n"
17506 #endif
17507 
17508  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17509 
17510 ;
17511 return true;
17512 },
17513 0,
17514 nullptr
17515 );
17516 //-------------------------------------------------------------------------------------------------------------------
17517 static InstructionDefinition c_or_8_rd_8_rs2(
17518  ISA16_RISCV64,
17519  "c.or",
17520  (uint16_t)0x8c41,
17521  (uint16_t) 0xfc63,
17522  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17523  {
17524  etiss_uint64 rs2 = 0;
17525  static BitArrayRange R_rs2_0 (4,2);
17526  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17527  rs2 += rs2_0;
17528  etiss_uint64 rd = 0;
17529  static BitArrayRange R_rd_0 (9,7);
17530  etiss_uint64 rd_0 = R_rd_0.read(ba);
17531  rd += rd_0;
17532  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17533  partInit.getRegisterDependencies().add(reg_name[rd+8],64);
17534  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
17535  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17536  partInit.getAffectedRegisters().add("instructionPointer",64);
17537  partInit.code() = std::string("//c.or\n")+
17538  "etiss_uint32 temp = 0;\n"
17539  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17540  #if RISCV64_Pipeline1
17541  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17542  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17543  "etiss_uint32 num_stages = 4;\n"
17544  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17545  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17546  #endif
17547  #if RISCV64_Pipeline2
17548  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17549  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17550  "etiss_uint32 num_stages = 4;\n"
17551  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17552  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17553  #endif
17554 
17555  "etiss_int8 rd_idx = 0;\n"
17556 
17557 "rd_idx = " + toString(rd) + " + 8;\n"
17558 #if RISCV64_DEBUG_CALL
17559 "printf(\"rd_idx = %#x\\n\",rd_idx); \n"
17560 #endif
17561 "*((RISCV64*)cpu)->X[rd_idx] = (*((RISCV64*)cpu)->X[rd_idx] | *((RISCV64*)cpu)->X[" + toString(rs2) + " + 8]);\n"
17562 #if RISCV64_DEBUG_CALL
17563 "printf(\"*((RISCV64*)cpu)->X[rd_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rd_idx]); \n"
17564 #endif
17565 
17566  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17567 
17568 ;
17569 return true;
17570 },
17571 0,
17572 nullptr
17573 );
17574 //-------------------------------------------------------------------------------------------------------------------
17575 static InstructionDefinition c_and_8_rd_8_rs2(
17576  ISA16_RISCV64,
17577  "c.and",
17578  (uint16_t)0x8c61,
17579  (uint16_t) 0xfc63,
17580  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17581  {
17582  etiss_uint64 rs2 = 0;
17583  static BitArrayRange R_rs2_0 (4,2);
17584  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17585  rs2 += rs2_0;
17586  etiss_uint64 rd = 0;
17587  static BitArrayRange R_rd_0 (9,7);
17588  etiss_uint64 rd_0 = R_rd_0.read(ba);
17589  rd += rd_0;
17590  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17591  partInit.getRegisterDependencies().add(reg_name[rd+8],64);
17592  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
17593  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17594  partInit.getAffectedRegisters().add("instructionPointer",64);
17595  partInit.code() = std::string("//c.and\n")+
17596  "etiss_uint32 temp = 0;\n"
17597  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17598  #if RISCV64_Pipeline1
17599  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17600  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17601  "etiss_uint32 num_stages = 4;\n"
17602  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17603  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17604  #endif
17605  #if RISCV64_Pipeline2
17606  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17607  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17608  "etiss_uint32 num_stages = 4;\n"
17609  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17610  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17611  #endif
17612 
17613  "etiss_int8 rd_idx = 0;\n"
17614 
17615 "rd_idx = " + toString(rd) + " + 8;\n"
17616 #if RISCV64_DEBUG_CALL
17617 "printf(\"rd_idx = %#x\\n\",rd_idx); \n"
17618 #endif
17619 "*((RISCV64*)cpu)->X[rd_idx] = (*((RISCV64*)cpu)->X[rd_idx] & *((RISCV64*)cpu)->X[" + toString(rs2) + " + 8]);\n"
17620 #if RISCV64_DEBUG_CALL
17621 "printf(\"*((RISCV64*)cpu)->X[rd_idx] = %#lx\\n\",*((RISCV64*)cpu)->X[rd_idx]); \n"
17622 #endif
17623 
17624  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17625 
17626 ;
17627 return true;
17628 },
17629 0,
17630 nullptr
17631 );
17632 //-------------------------------------------------------------------------------------------------------------------
17633 static InstructionDefinition c_mv_rd_rs2(
17634  ISA16_RISCV64,
17635  "c.mv",
17636  (uint16_t)0x8002,
17637  (uint16_t) 0xf003,
17638  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17639  {
17640  etiss_uint64 rs2 = 0;
17641  static BitArrayRange R_rs2_0 (6,2);
17642  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17643  rs2 += rs2_0;
17644  etiss_uint64 rd = 0;
17645  static BitArrayRange R_rd_0 (11,7);
17646  etiss_uint64 rd_0 = R_rd_0.read(ba);
17647  rd += rd_0;
17648  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17649  partInit.getRegisterDependencies().add(reg_name[rs2],64);
17650  partInit.getAffectedRegisters().add(reg_name[rd],64);
17651  partInit.getAffectedRegisters().add("instructionPointer",64);
17652  partInit.code() = std::string("//c.mv\n")+
17653  "etiss_uint32 temp = 0;\n"
17654  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17655  #if RISCV64_Pipeline1
17656  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17657  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17658  "etiss_uint32 num_stages = 4;\n"
17659  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17660  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17661  #endif
17662  #if RISCV64_Pipeline2
17663  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17664  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17665  "etiss_uint32 num_stages = 4;\n"
17666  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17667  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17668  #endif
17669 
17670 
17671 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
17672 #if RISCV64_DEBUG_CALL
17673 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
17674 #endif
17675 
17676  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17677 
17678 ;
17679 return true;
17680 },
17681 0,
17682 nullptr
17683 );
17684 //-------------------------------------------------------------------------------------------------------------------
17685 static InstructionDefinition c_jr_rs1(
17686  ISA16_RISCV64,
17687  "c.jr",
17688  (uint16_t)0x8002,
17689  (uint16_t) 0xf07f,
17690  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17691  {
17692  etiss_uint64 rs1 = 0;
17693  static BitArrayRange R_rs1_0 (11,7);
17694  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
17695  rs1 += rs1_0;
17696  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17697  partInit.getRegisterDependencies().add(reg_name[rs1],64);
17698  partInit.getAffectedRegisters().add("instructionPointer",64);
17699  partInit.code() = std::string("//c.jr\n")+
17700  "etiss_uint32 temp = 0;\n"
17701  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17702  #if RISCV64_Pipeline1
17703  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17704  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17705  "etiss_uint32 num_stages = 4;\n"
17706  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17707  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17708  #endif
17709  #if RISCV64_Pipeline2
17710  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17711  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17712  "etiss_uint32 num_stages = 4;\n"
17713  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17714  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17715  #endif
17716 
17717 
17718 "cpu->instructionPointer = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
17719 #if RISCV64_DEBUG_CALL
17720 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
17721 #endif
17722 
17723  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
17724 
17725  "return 0;\n"
17726 ;
17727 return true;
17728 },
17729 0,
17730 nullptr
17731 );
17732 //-------------------------------------------------------------------------------------------------------------------
17733 static InstructionDefinition c_add_rd_rs2(
17734  ISA16_RISCV64,
17735  "c.add",
17736  (uint16_t)0x9002,
17737  (uint16_t) 0xf003,
17738  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17739  {
17740  etiss_uint64 rs2 = 0;
17741  static BitArrayRange R_rs2_0 (6,2);
17742  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17743  rs2 += rs2_0;
17744  etiss_uint64 rd = 0;
17745  static BitArrayRange R_rd_0 (11,7);
17746  etiss_uint64 rd_0 = R_rd_0.read(ba);
17747  rd += rd_0;
17748  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17749  partInit.getRegisterDependencies().add(reg_name[rs2],64);
17750  partInit.getRegisterDependencies().add(reg_name[rd],64);
17751  partInit.getAffectedRegisters().add(reg_name[rd],64);
17752  partInit.getAffectedRegisters().add("instructionPointer",64);
17753  partInit.code() = std::string("//c.add\n")+
17754  "etiss_uint32 temp = 0;\n"
17755  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17756  #if RISCV64_Pipeline1
17757  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17758  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17759  "etiss_uint32 num_stages = 4;\n"
17760  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17761  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17762  #endif
17763  #if RISCV64_Pipeline2
17764  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17765  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17766  "etiss_uint32 num_stages = 4;\n"
17767  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17768  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17769  #endif
17770 
17771 
17772 "*((RISCV64*)cpu)->X[" + toString(rd) + "] = *((RISCV64*)cpu)->X[" + toString(rd) + "] + *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
17773 #if RISCV64_DEBUG_CALL
17774 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + "] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + "]); \n"
17775 #endif
17776 
17777  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17778 
17779 ;
17780 return true;
17781 },
17782 0,
17783 nullptr
17784 );
17785 //-------------------------------------------------------------------------------------------------------------------
17786 static InstructionDefinition c_jalr_rs1(
17787  ISA16_RISCV64,
17788  "c.jalr",
17789  (uint16_t)0x9002,
17790  (uint16_t) 0xf07f,
17791  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17792  {
17793  etiss_uint64 rs1 = 0;
17794  static BitArrayRange R_rs1_0 (11,7);
17795  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
17796  rs1 += rs1_0;
17797  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17798  partInit.getRegisterDependencies().add(reg_name[rs1],64);
17799  partInit.getAffectedRegisters().add(reg_name[1],64);
17800  partInit.getAffectedRegisters().add("instructionPointer",64);
17801  partInit.code() = std::string("//c.jalr\n")+
17802  "etiss_uint32 temp = 0;\n"
17803  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17804  #if RISCV64_Pipeline1
17805  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17806  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17807  "etiss_uint32 num_stages = 4;\n"
17808  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17809  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17810  #endif
17811  #if RISCV64_Pipeline2
17812  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17813  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17814  "etiss_uint32 num_stages = 4;\n"
17815  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17816  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17817  #endif
17818 
17819 
17820 "*((RISCV64*)cpu)->X[1] = " +toString((uint64_t)ic.current_address_)+"ULL + 2;\n"
17821 #if RISCV64_DEBUG_CALL
17822 "printf(\"*((RISCV64*)cpu)->X[1] = %#lx\\n\",*((RISCV64*)cpu)->X[1]); \n"
17823 #endif
17824 "cpu->instructionPointer = *((RISCV64*)cpu)->X[" + toString(rs1) + "];\n"
17825 #if RISCV64_DEBUG_CALL
17826 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
17827 #endif
17828 
17829  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
17830 
17831  "return 0;\n"
17832 ;
17833 return true;
17834 },
17835 0,
17836 nullptr
17837 );
17838 //-------------------------------------------------------------------------------------------------------------------
17839 static InstructionDefinition c_ebreak_(
17840  ISA16_RISCV64,
17841  "c.ebreak",
17842  (uint16_t)0x9002,
17843  (uint16_t) 0xffff,
17844  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17845  {
17846  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17847  partInit.getAffectedRegisters().add("instructionPointer",64);
17848  partInit.code() = std::string("//c.ebreak\n")+
17849  "etiss_uint32 exception = 0;\n"
17850  "etiss_uint32 temp = 0;\n"
17851  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17852  #if RISCV64_Pipeline1
17853  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17854  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17855  "etiss_uint32 num_stages = 4;\n"
17856  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17857  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17858  #endif
17859  #if RISCV64_Pipeline2
17860  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17861  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17862  "etiss_uint32 num_stages = 4;\n"
17863  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17864  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17865  #endif
17866 
17867 
17868 "return ETISS_RETURNCODE_CPUFINISHED; \n"
17869 
17870  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17871 
17872  "return exception;\n"
17873 ;
17874 return true;
17875 },
17876 0,
17877 nullptr
17878 );
17879 //-------------------------------------------------------------------------------------------------------------------
17880 static InstructionDefinition c_subw_8_rd_8_rd_8_rs2(
17881  ISA16_RISCV64,
17882  "c.subw",
17883  (uint16_t)0x9c01,
17884  (uint16_t) 0xfc63,
17885  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17886  {
17887  etiss_uint64 rs2 = 0;
17888  static BitArrayRange R_rs2_0 (4,2);
17889  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17890  rs2 += rs2_0;
17891  etiss_uint64 rd = 0;
17892  static BitArrayRange R_rd_0 (9,7);
17893  etiss_uint64 rd_0 = R_rd_0.read(ba);
17894  rd += rd_0;
17895  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17896  partInit.getRegisterDependencies().add(reg_name[rd+8],64);
17897  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
17898  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17899  partInit.getAffectedRegisters().add("instructionPointer",64);
17900  partInit.code() = std::string("//c.subw\n")+
17901  "etiss_uint32 temp = 0;\n"
17902  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17903  #if RISCV64_Pipeline1
17904  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17905  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17906  "etiss_uint32 num_stages = 4;\n"
17907  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17908  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17909  #endif
17910  #if RISCV64_Pipeline2
17911  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17912  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17913  "etiss_uint32 num_stages = 4;\n"
17914  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17915  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17916  #endif
17917 
17918  "etiss_uint32 res = 0;\n"
17919 
17920 "res = (*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] & 0xffffffff) - (*((RISCV64*)cpu)->X[" + toString(rs2) + " + 8] & 0xffffffff);\n"
17921 #if RISCV64_DEBUG_CALL
17922 "printf(\"res = %#x\\n\",res); \n"
17923 #endif
17924 "etiss_int32 cast_0 = res; \n"
17925 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
17926 "{\n"
17927  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
17928 "}\n"
17929 "*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = (etiss_int64)cast_0;\n"
17930 #if RISCV64_DEBUG_CALL
17931 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + " + 8]); \n"
17932 #endif
17933 
17934  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17935 
17936 ;
17937 return true;
17938 },
17939 0,
17940 nullptr
17941 );
17942 //-------------------------------------------------------------------------------------------------------------------
17943 static InstructionDefinition c_addw_8_rd_8_rd_8_rs2(
17944  ISA16_RISCV64,
17945  "c.addw",
17946  (uint16_t)0x9c21,
17947  (uint16_t) 0xfc63,
17948  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
17949  {
17950  etiss_uint64 rs2 = 0;
17951  static BitArrayRange R_rs2_0 (4,2);
17952  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
17953  rs2 += rs2_0;
17954  etiss_uint64 rd = 0;
17955  static BitArrayRange R_rd_0 (9,7);
17956  etiss_uint64 rd_0 = R_rd_0.read(ba);
17957  rd += rd_0;
17958  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
17959  partInit.getRegisterDependencies().add(reg_name[rd+8],64);
17960  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
17961  partInit.getAffectedRegisters().add(reg_name[rd+8],64);
17962  partInit.getAffectedRegisters().add("instructionPointer",64);
17963  partInit.code() = std::string("//c.addw\n")+
17964  "etiss_uint32 temp = 0;\n"
17965  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
17966  #if RISCV64_Pipeline1
17967  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17968  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17969  "etiss_uint32 num_stages = 4;\n"
17970  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17971  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17972  #endif
17973  #if RISCV64_Pipeline2
17974  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
17975  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
17976  "etiss_uint32 num_stages = 4;\n"
17977  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
17978  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
17979  #endif
17980 
17981  "etiss_uint32 res = 0;\n"
17982 
17983 "res = (*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] & 0xffffffff) + (*((RISCV64*)cpu)->X[" + toString(rs2) + " + 8] & 0xffffffff);\n"
17984 #if RISCV64_DEBUG_CALL
17985 "printf(\"res = %#x\\n\",res); \n"
17986 #endif
17987 "etiss_int32 cast_0 = res; \n"
17988 "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n"
17989 "{\n"
17990  "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n"
17991 "}\n"
17992 "*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = (etiss_int64)cast_0;\n"
17993 #if RISCV64_DEBUG_CALL
17994 "printf(\"*((RISCV64*)cpu)->X[" + toString(rd) + " + 8] = %#lx\\n\",*((RISCV64*)cpu)->X[" + toString(rd) + " + 8]); \n"
17995 #endif
17996 
17997  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
17998 
17999 ;
18000 return true;
18001 },
18002 0,
18003 nullptr
18004 );
18005 //-------------------------------------------------------------------------------------------------------------------
18006 static InstructionDefinition c_j_imm(
18007  ISA16_RISCV64,
18008  "c.j",
18009  (uint16_t)0xa001,
18010  (uint16_t) 0xe003,
18011  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
18012  {
18013  etiss_int64 imm = 0;
18014  static BitArrayRange R_imm_11 (12,12);
18015  etiss_int64 imm_11 = R_imm_11.read(ba);
18016  imm += imm_11<<11;
18017  static BitArrayRange R_imm_4 (11,11);
18018  etiss_int64 imm_4 = R_imm_4.read(ba);
18019  imm += imm_4<<4;
18020  static BitArrayRange R_imm_8 (10,9);
18021  etiss_int64 imm_8 = R_imm_8.read(ba);
18022  imm += imm_8<<8;
18023  static BitArrayRange R_imm_10 (8,8);
18024  etiss_int64 imm_10 = R_imm_10.read(ba);
18025  imm += imm_10<<10;
18026  static BitArrayRange R_imm_6 (7,7);
18027  etiss_int64 imm_6 = R_imm_6.read(ba);
18028  imm += imm_6<<6;
18029  static BitArrayRange R_imm_7 (6,6);
18030  etiss_int64 imm_7 = R_imm_7.read(ba);
18031  imm += imm_7<<7;
18032  static BitArrayRange R_imm_1 (5,3);
18033  etiss_int64 imm_1 = R_imm_1.read(ba);
18034  imm += imm_1<<1;
18035  static BitArrayRange R_imm_5 (2,2);
18036  etiss_int64 imm_5 = R_imm_5.read(ba);
18037  imm += imm_5<<5;
18038  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
18039  partInit.getAffectedRegisters().add("instructionPointer",64);
18040  partInit.code() = std::string("//c.j\n")+
18041  "etiss_uint32 temp = 0;\n"
18042  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
18043  #if RISCV64_Pipeline1
18044  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18045  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18046  "etiss_uint32 num_stages = 4;\n"
18047  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18048  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18049  #endif
18050  #if RISCV64_Pipeline2
18051  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18052  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18053  "etiss_uint32 num_stages = 4;\n"
18054  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18055  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18056  #endif
18057 
18058  "etiss_int64 imm_extended = 0;\n"
18059 
18060 "if((" + toString(imm) + " & 0x800)>>11 == 0)\n"
18061 "{\n"
18062  "imm_extended = 0;\n"
18063  #if RISCV64_DEBUG_CALL
18064  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
18065  #endif
18066 "}\n"
18067 
18068 "else\n"
18069 "{\n"
18070  "imm_extended = 4294967295;\n"
18071  #if RISCV64_DEBUG_CALL
18072  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
18073  #endif
18074  "imm_extended = (imm_extended << 32);\n"
18075  #if RISCV64_DEBUG_CALL
18076  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
18077  #endif
18078  "imm_extended = imm_extended + 4294963200;\n"
18079  #if RISCV64_DEBUG_CALL
18080  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
18081  #endif
18082 "}\n"
18083 "imm_extended = imm_extended + " + toString(imm) + ";\n"
18084 #if RISCV64_DEBUG_CALL
18085 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
18086 #endif
18087 "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
18088 "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
18089 "{\n"
18090  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
18091 "}\n"
18092 "cpu->instructionPointer = (etiss_int64)cast_0 + imm_extended;\n"
18093 #if RISCV64_DEBUG_CALL
18094 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
18095 #endif
18096 
18097  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
18098 
18099  "return 0;\n"
18100 ;
18101 return true;
18102 },
18103 0,
18104 nullptr
18105 );
18106 //-------------------------------------------------------------------------------------------------------------------
18107 static InstructionDefinition c_fsd_rs2_uimm_8_rs1_(
18108  ISA16_RISCV64,
18109  "c.fsd",
18110  (uint16_t)0xa000,
18111  (uint16_t) 0xe003,
18112  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
18113  {
18114  etiss_uint64 rs2 = 0;
18115  static BitArrayRange R_rs2_0 (4,2);
18116  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
18117  rs2 += rs2_0;
18118  etiss_uint64 rs1 = 0;
18119  static BitArrayRange R_rs1_0 (9,7);
18120  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
18121  rs1 += rs1_0;
18122  etiss_uint64 uimm = 0;
18123  static BitArrayRange R_uimm_3 (12,10);
18124  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
18125  uimm += uimm_3<<3;
18126  static BitArrayRange R_uimm_6 (6,5);
18127  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
18128  uimm += uimm_6<<6;
18129  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
18130  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
18131  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
18132  partInit.getAffectedRegisters().add("instructionPointer",64);
18133  partInit.code() = std::string("//c.fsd\n")+
18134  "etiss_uint32 exception = 0;\n"
18135  "etiss_uint32 temp = 0;\n"
18136  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
18137  #if RISCV64_Pipeline1
18138  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18139  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18140  "etiss_uint32 num_stages = 4;\n"
18141  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18142  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18143  #endif
18144  #if RISCV64_Pipeline2
18145  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18146  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18147  "etiss_uint32 num_stages = 4;\n"
18148  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18149  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18150  #endif
18151 
18152  "etiss_uint64 offs = 0;\n"
18153 
18154 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n"
18155 #if RISCV64_DEBUG_CALL
18156 "printf(\"offs = %#lx\\n\",offs); \n"
18157 #endif
18158  "etiss_uint64 MEM_offs;\n"
18159 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
18160 "MEM_offs = (((RISCV64*)cpu)->F[" + toString(rs2) + " + 8] & 0xffffffffffffffff);\n"
18161 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
18162 #if RISCV64_DEBUG_CALL
18163 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
18164 #endif
18165 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
18166 "{\n"
18167  "((RISCV64*)cpu)->RES = 0;\n"
18168  #if RISCV64_DEBUG_CALL
18169  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
18170  #endif
18171 "}\n"
18172 
18173 
18174  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
18175 
18176  "return exception;\n"
18177 ;
18178 return true;
18179 },
18180 0,
18181 nullptr
18182 );
18183 //-------------------------------------------------------------------------------------------------------------------
18184 static InstructionDefinition c_fsdsp_rs2_uimm_x2_(
18185  ISA16_RISCV64,
18186  "c.fsdsp",
18187  (uint16_t)0xa002,
18188  (uint16_t) 0xe003,
18189  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
18190  {
18191  etiss_uint64 rs2 = 0;
18192  static BitArrayRange R_rs2_0 (6,2);
18193  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
18194  rs2 += rs2_0;
18195  etiss_uint64 uimm = 0;
18196  static BitArrayRange R_uimm_3 (12,10);
18197  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
18198  uimm += uimm_3<<3;
18199  static BitArrayRange R_uimm_6 (9,7);
18200  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
18201  uimm += uimm_6<<6;
18202  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
18203  partInit.getRegisterDependencies().add(reg_name[2],64);
18204  partInit.getRegisterDependencies().add(reg_name[rs2],64);
18205  partInit.getAffectedRegisters().add("instructionPointer",64);
18206  partInit.code() = std::string("//c.fsdsp\n")+
18207  "etiss_uint32 exception = 0;\n"
18208  "etiss_uint32 temp = 0;\n"
18209  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
18210  #if RISCV64_Pipeline1
18211  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18212  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18213  "etiss_uint32 num_stages = 4;\n"
18214  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18215  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18216  #endif
18217  #if RISCV64_Pipeline2
18218  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18219  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18220  "etiss_uint32 num_stages = 4;\n"
18221  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18222  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18223  #endif
18224 
18225  "etiss_uint64 offs = 0;\n"
18226 
18227 "offs = *((RISCV64*)cpu)->X[2] + " + toString(uimm) + ";\n"
18228 #if RISCV64_DEBUG_CALL
18229 "printf(\"offs = %#lx\\n\",offs); \n"
18230 #endif
18231  "etiss_uint64 MEM_offs;\n"
18232 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
18233 "MEM_offs = (((RISCV64*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff);\n"
18234 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
18235 #if RISCV64_DEBUG_CALL
18236 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
18237 #endif
18238 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
18239 "{\n"
18240  "((RISCV64*)cpu)->RES = 0;\n"
18241  #if RISCV64_DEBUG_CALL
18242  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
18243  #endif
18244 "}\n"
18245 
18246 
18247  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
18248 
18249  "return exception;\n"
18250 ;
18251 return true;
18252 },
18253 0,
18254 nullptr
18255 );
18256 //-------------------------------------------------------------------------------------------------------------------
18257 static InstructionDefinition c_bnez_8_rs1_imm(
18258  ISA16_RISCV64,
18259  "c.bnez",
18260  (uint16_t)0xe001,
18261  (uint16_t) 0xe003,
18262  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
18263  {
18264  etiss_uint64 rs1 = 0;
18265  static BitArrayRange R_rs1_0 (9,7);
18266  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
18267  rs1 += rs1_0;
18268  etiss_int64 imm = 0;
18269  static BitArrayRange R_imm_8 (12,12);
18270  etiss_int64 imm_8 = R_imm_8.read(ba);
18271  imm += imm_8<<8;
18272  static BitArrayRange R_imm_3 (11,10);
18273  etiss_int64 imm_3 = R_imm_3.read(ba);
18274  imm += imm_3<<3;
18275  static BitArrayRange R_imm_6 (6,5);
18276  etiss_int64 imm_6 = R_imm_6.read(ba);
18277  imm += imm_6<<6;
18278  static BitArrayRange R_imm_1 (4,3);
18279  etiss_int64 imm_1 = R_imm_1.read(ba);
18280  imm += imm_1<<1;
18281  static BitArrayRange R_imm_5 (2,2);
18282  etiss_int64 imm_5 = R_imm_5.read(ba);
18283  imm += imm_5<<5;
18284  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
18285  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
18286  partInit.getAffectedRegisters().add("instructionPointer",64);
18287  partInit.code() = std::string("//c.bnez\n")+
18288  "etiss_uint32 temp = 0;\n"
18289  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
18290  #if RISCV64_Pipeline1
18291  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18292  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18293  "etiss_uint32 num_stages = 4;\n"
18294  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18295  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18296  #endif
18297  #if RISCV64_Pipeline2
18298  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18299  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18300  "etiss_uint32 num_stages = 4;\n"
18301  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18302  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18303  #endif
18304 
18305  "etiss_int64 imm_extended = 0;\n"
18306  "etiss_int64 choose1 = 0;\n"
18307 
18308 "if((" + toString(imm) + " & 0x100)>>8 == 0)\n"
18309 "{\n"
18310  "imm_extended = 0;\n"
18311  #if RISCV64_DEBUG_CALL
18312  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
18313  #endif
18314 "}\n"
18315 
18316 "else\n"
18317 "{\n"
18318  "imm_extended = 4294967295;\n"
18319  #if RISCV64_DEBUG_CALL
18320  "printf(\"imm_extended = %#x\\n\",imm_extended); \n"
18321  #endif
18322  "imm_extended = (imm_extended << 32);\n"
18323  #if RISCV64_DEBUG_CALL
18324  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
18325  #endif
18326  "imm_extended = imm_extended + 4294966784;\n"
18327  #if RISCV64_DEBUG_CALL
18328  "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
18329  #endif
18330 "}\n"
18331 "imm_extended = imm_extended + " + toString(imm) + ";\n"
18332 #if RISCV64_DEBUG_CALL
18333 "printf(\"imm_extended = %#lx\\n\",imm_extended); \n"
18334 #endif
18335 "if(*((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] != 0)\n"
18336 "{\n"
18337  "etiss_int64 cast_0 = " +toString((uint64_t)ic.current_address_)+"ULL ; \n"
18338  "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n"
18339  "{\n"
18340  "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n"
18341  "}\n"
18342  "choose1 = (etiss_int64)cast_0 + imm_extended;\n"
18343  #if RISCV64_DEBUG_CALL
18344  "printf(\"choose1 = %#lx\\n\",choose1); \n"
18345  #endif
18346 // Explicit assignment to PC
18347 "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
18348 "}\n"
18349 
18350 "else\n"
18351 "{\n"
18352  "choose1 = " +toString((uint64_t)ic.current_address_)+"ULL + 2;\n"
18353  #if RISCV64_DEBUG_CALL
18354  "printf(\"choose1 = %#lx\\n\",choose1); \n"
18355  #endif
18356 "}\n"
18357 "cpu->instructionPointer = choose1;\n"
18358 #if RISCV64_DEBUG_CALL
18359 "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n"
18360 #endif
18361 
18362  "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n"
18363 
18364  "return 0;\n"
18365 ;
18366 return true;
18367 },
18368 0,
18369 nullptr
18370 );
18371 //-------------------------------------------------------------------------------------------------------------------
18372 static InstructionDefinition c_sd_8_rs2_uimm_8_rs1_(
18373  ISA16_RISCV64,
18374  "c.sd",
18375  (uint16_t)0xe000,
18376  (uint16_t) 0xe003,
18377  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
18378  {
18379  etiss_uint64 rs2 = 0;
18380  static BitArrayRange R_rs2_0 (4,2);
18381  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
18382  rs2 += rs2_0;
18383  etiss_uint64 rs1 = 0;
18384  static BitArrayRange R_rs1_0 (9,7);
18385  etiss_uint64 rs1_0 = R_rs1_0.read(ba);
18386  rs1 += rs1_0;
18387  etiss_uint64 uimm = 0;
18388  static BitArrayRange R_uimm_3 (12,10);
18389  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
18390  uimm += uimm_3<<3;
18391  static BitArrayRange R_uimm_6 (6,5);
18392  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
18393  uimm += uimm_6<<6;
18394  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
18395  partInit.getRegisterDependencies().add(reg_name[rs1+8],64);
18396  partInit.getRegisterDependencies().add(reg_name[rs2+8],64);
18397  partInit.getAffectedRegisters().add("instructionPointer",64);
18398  partInit.code() = std::string("//c.sd\n")+
18399  "etiss_uint32 exception = 0;\n"
18400  "etiss_uint32 temp = 0;\n"
18401  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
18402  #if RISCV64_Pipeline1
18403  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18404  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18405  "etiss_uint32 num_stages = 4;\n"
18406  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18407  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18408  #endif
18409  #if RISCV64_Pipeline2
18410  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18411  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18412  "etiss_uint32 num_stages = 4;\n"
18413  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18414  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18415  #endif
18416 
18417  "etiss_uint64 offs = 0;\n"
18418 
18419 "offs = *((RISCV64*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n"
18420 #if RISCV64_DEBUG_CALL
18421 "printf(\"offs = %#lx\\n\",offs); \n"
18422 #endif
18423  "etiss_uint64 MEM_offs;\n"
18424 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
18425 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + " + 8];\n"
18426 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
18427 #if RISCV64_DEBUG_CALL
18428 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
18429 #endif
18430 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
18431 "{\n"
18432  "((RISCV64*)cpu)->RES = 0;\n"
18433  #if RISCV64_DEBUG_CALL
18434  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
18435  #endif
18436 "}\n"
18437 
18438 
18439  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
18440 
18441  "return exception;\n"
18442 ;
18443 return true;
18444 },
18445 0,
18446 nullptr
18447 );
18448 //-------------------------------------------------------------------------------------------------------------------
18449 static InstructionDefinition c_sdsp_rs2_uimm_sp_(
18450  ISA16_RISCV64,
18451  "c.sdsp",
18452  (uint16_t)0xe002,
18453  (uint16_t) 0xe003,
18454  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
18455  {
18456  etiss_uint64 rs2 = 0;
18457  static BitArrayRange R_rs2_0 (6,2);
18458  etiss_uint64 rs2_0 = R_rs2_0.read(ba);
18459  rs2 += rs2_0;
18460  etiss_uint64 uimm = 0;
18461  static BitArrayRange R_uimm_3 (12,10);
18462  etiss_uint64 uimm_3 = R_uimm_3.read(ba);
18463  uimm += uimm_3<<3;
18464  static BitArrayRange R_uimm_6 (9,7);
18465  etiss_uint64 uimm_6 = R_uimm_6.read(ba);
18466  uimm += uimm_6<<6;
18467  CodePart & partInit = cs.append(CodePart::INITIALREQUIRED);
18468  partInit.getRegisterDependencies().add(reg_name[rs2],64);
18469  partInit.getRegisterDependencies().add(reg_name[2],64);
18470  partInit.getAffectedRegisters().add("instructionPointer",64);
18471  partInit.code() = std::string("//c.sdsp\n")+
18472  "etiss_uint32 exception = 0;\n"
18473  "etiss_uint32 temp = 0;\n"
18474  "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n"
18475  #if RISCV64_Pipeline1
18476  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18477  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18478  "etiss_uint32 num_stages = 4;\n"
18479  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18480  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18481  #endif
18482  #if RISCV64_Pipeline2
18483  "etiss_uint32 resource_time [100] = {1, 1, 1, 3, 1, 1, 1, 1, 4};\n"
18484  "etiss_uint32 resources [100][100] = {{0, 1}, {2}, {5}, {6, 7}};\n"
18485  "etiss_uint32 num_stages = 4;\n"
18486  "etiss_uint32 num_resources[100] = {2, 1, 1, 2};\n"
18487  "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n"
18488  #endif
18489 
18490  "etiss_uint64 offs = 0;\n"
18491 
18492 "offs = *((RISCV64*)cpu)->X[2] + " + toString(uimm) + ";\n"
18493 #if RISCV64_DEBUG_CALL
18494 "printf(\"offs = %#lx\\n\",offs); \n"
18495 #endif
18496  "etiss_uint64 MEM_offs;\n"
18497 "tmpbuf = (etiss_uint8 *)&MEM_offs;\n"
18498 "MEM_offs = *((RISCV64*)cpu)->X[" + toString(rs2) + "];\n"
18499 "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n"
18500 #if RISCV64_DEBUG_CALL
18501 "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n"
18502 #endif
18503 "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n"
18504 "{\n"
18505  "((RISCV64*)cpu)->RES = 0;\n"
18506  #if RISCV64_DEBUG_CALL
18507  "printf(\"((RISCV64*)cpu)->RES = %#lx\\n\",((RISCV64*)cpu)->RES); \n"
18508  #endif
18509 "}\n"
18510 
18511 
18512  "cpu->instructionPointer = " +toString((uint64_t)(ic.current_address_+ 2 ))+"ULL; \n"
18513 
18514  "return exception;\n"
18515 ;
18516 return true;
18517 },
18518 0,
18519 nullptr
18520 );
18521 //-------------------------------------------------------------------------------------------------------------------
18522 
18523 
fmsub_d_rd_frs1_frs2_frs3
static InstructionDefinition fmsub_d_rd_frs1_frs2_frs3(ISA32_RISCV64, "fmsub.d",(uint32_t) 0x2000047,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmsub.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs3)+"] & 0xffffffffffffffff), (etiss_uint32)1, choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amomin_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amomin_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amomin.d",(uint32_t) 0x8000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amomin.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "etiss_int64 cast_2 = res1; \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "if((etiss_int64)cast_2 > (etiss_int64)cast_1)\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res1;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
csrrw_rd_csr_rs1
static InstructionDefinition csrrw_rd_csr_rs1(ISA32_RISCV64, "csrrw",(uint32_t) 0x1073,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 csr=0;static BitArrayRange R_csr_0(31, 20);etiss_uint64 csr_0=R_csr_0.read(ba);csr+=csr_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//csrrw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 mAddr = 0;\n" "etiss_int64 writeMask = 0;\n" "etiss_int64 writeMaskU = 0;\n" "etiss_int64 sAddr = 0;\n" "etiss_int64 writeMaskS = 0;\n" "etiss_int64 uAddr = 0;\n" "etiss_uint64 rs_val = 0;\n" "etiss_uint64 csr_val = 0;\n" "etiss_int64 writeMaskM = 0;\n" "rs_val = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if("+toString(rd)+" != 0)\n" "{\n" "csr_val = ((RISCV64*)cpu)->CSR["+toString(csr)+"];\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | (rs_val & writeMask))&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = rs_val;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = csr_val;\n" "}\n" "else\n" "{\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | (rs_val & writeMask))&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = rs_val;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
lwu_rd_imm_rs1_
static InstructionDefinition lwu_rd_imm_rs1_(ISA32_RISCV64, "lwu",(uint32_t) 0x6003,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lwu\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)MEM_offs;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
subw_
static InstructionDefinition subw_(ISA32_RISCV64, "subw",(uint32_t) 0x4000003b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//subw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "res = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) - (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff);\n" "etiss_int32 cast_0 = res; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmv_d_x_rd_rs1
static InstructionDefinition fmv_d_x_rd_rs1(ISA32_RISCV64, "fmv.d.x",(uint32_t) 0xf2000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmv.d.x\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = (etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fdiv_d_rd_frs1_frs2
static InstructionDefinition fdiv_d_rd_frs1_frs2(ISA32_RISCV64, "fdiv.d",(uint32_t) 0x1a000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fdiv.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fdiv_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
flt_d_rd_frs1_frs2
static InstructionDefinition flt_d_rd_frs1_frs2(ISA32_RISCV64, "flt.d",(uint32_t) 0xa2001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//flt.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (etiss_uint32)2);\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
sb_rs2_imm_rs1_
static InstructionDefinition sb_rs2_imm_rs1_(ISA32_RISCV64, "sb",(uint32_t) 0x23,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(31, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(11, 7);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sb\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint8 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,1);\n" "if((offs + 1 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
lw_rd_imm_rs1_
static InstructionDefinition lw_rd_imm_rs1_(ISA32_RISCV64, "lw",(uint32_t) 0x2003,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lw\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_1 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
slt_rd_rs1_rs2
static InstructionDefinition slt_rd_rs1_rs2(ISA32_RISCV64, "slt",(uint32_t) 0x2033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//slt\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 choose1 = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "if((etiss_int64)cast_1 < (etiss_int64)cast_0)\n" "{\n" "choose1 = 1;\n" "}\n" "else\n" "{\n" "choose1 = 0;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = choose1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
ISA32_RISCV64
etiss::instr::InstructionGroup ISA32_RISCV64("ISA32_RISCV64", 32)
fcvt_l_s_rd_frs1
static InstructionDefinition fcvt_l_s_rd_frs1(ISA32_RISCV64, "fcvt.l.s",(uint32_t) 0xc0200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.l.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_uint32 flags = 0;\n" "res = fcvt_32_64(unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]), (etiss_uint32)0, ("+toString(rm)+" & 0xff));\n" "etiss_int64 cast_0 = res; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
divu_rd_rs1_rs2
static InstructionDefinition divu_rd_rs1_rs2(ISA32_RISCV64, "divu",(uint32_t) 0x2005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//divu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if(*((RISCV64*)cpu)->X["+toString(rs2)+"] != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] / *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "}\n" "else\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = - 1;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fsqrt_d_rd_frs1
static InstructionDefinition fsqrt_d_rd_frs1(ISA32_RISCV64, "fsqrt.d",(uint32_t) 0x5a000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsqrt.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fsqrt_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
sc_w_rd_rs1_rs2
static InstructionDefinition sc_w_rd_rs1_rs2(ISA32_RISCV64, "sc.w",(uint32_t) 0x1800202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sc.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if(offs == ((RISCV64*)cpu)->RES)\n" "{\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = 0;\n" "}\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "else\n" "{\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = 1;\n" "}\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
fadd_d_rd_frs1_frs2
static InstructionDefinition fadd_d_rd_frs1_frs2(ISA32_RISCV64, "fadd.d",(uint32_t) 0x2000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fadd.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fadd_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
sd_rs2_imm_rs1_
static InstructionDefinition sd_rs2_imm_rs1_(ISA32_RISCV64, "sd",(uint32_t) 0x3023,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(31, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(11, 7);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sd\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:436
sltu_rd_rs1_rs2
static InstructionDefinition sltu_rd_rs1_rs2(ISA32_RISCV64, "sltu",(uint32_t) 0x3033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sltu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 choose1 = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if((etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs1)+"] < (etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "choose1 = 1;\n" "}\n" "else\n" "{\n" "choose1 = 0;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = choose1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64MMU
Definition: RISCV64MMU.h:56
etiss::Plugin::getLastAssignedCoreName
const std::string & getLastAssignedCoreName()
Definition: Plugin.h:175
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
add_rd_rs1_rs2
static InstructionDefinition add_rd_rs1_rs2(ISA32_RISCV64, "add",(uint32_t) 0x33,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//add\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = *((RISCV64*)cpu)->X["+toString(rs1)+"] + *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
srai_rd_rs1_shamt
static InstructionDefinition srai_rd_rs1_shamt(ISA32_RISCV64, "srai",(uint32_t) 0x40005013,(uint32_t) 0xfc00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_0(25, 20);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//srai\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_0 >> "+toString(shamt)+");\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
endif
endif() endforeach() unset(LOCAL_SOURCE1) unset(LOCAL_SOURCE2) set(ETISS_HEADER $
Definition: CMakeLists.txt:42
slliw_rd_rs1_shamt
static InstructionDefinition slliw_rd_rs1_shamt(ISA32_RISCV64, "slliw",(uint32_t) 0x101b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_0(24, 20);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//slliw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 sh_val = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "sh_val = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) << "+toString(shamt)+");\n" "etiss_int32 cast_0 = sh_val; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::S7
etiss_uint64 S7
Definition: RISCV64.h:66
c_addi_rs1_imm
static InstructionDefinition c_addi_rs1_imm(ISA16_RISCV64, "c.addi",(uint16_t) 0x1,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(11, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(12, 12);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(6, 2);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.addi\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x20)>>5 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294967232;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rs1)+"] = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
div_rd_rs1_rs2
static InstructionDefinition div_rd_rs1_rs2(ISA32_RISCV64, "div",(uint32_t) 0x2004033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//div\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 XLM1 = 0;\n" "etiss_int64 MMIN = 0;\n" "etiss_int64 M1 = 0;\n" "etiss_int64 ONE = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if(*((RISCV64*)cpu)->X["+toString(rs2)+"] != 0)\n" "{\n" "M1 = - 1;\n" "XLM1 = 64 - 1;\n" "ONE = 1;\n" "MMIN = (ONE << XLM1);\n" "if((*((RISCV64*)cpu)->X["+toString(rs1)+"] == MMIN) && (*((RISCV64*)cpu)->X["+toString(rs2)+"] == M1))\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = MMIN;\n" "}\n" "else\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_1 / (etiss_int64)cast_0);\n" "}\n" "}\n" "else\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = - 1;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64_Pipeline2
#define RISCV64_Pipeline2
Definition: RISCV64Arch.cpp:40
etiss::mm::NOERROR
const MM_EXPORT int32_t NOERROR
RISCV64::T1
etiss_uint64 T1
Definition: RISCV64.h:49
c_addiw_rs1_imm
static InstructionDefinition c_addiw_rs1_imm(ISA16_RISCV64, "c.addiw",(uint16_t) 0x2001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(11, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(12, 12);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(6, 2);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.addiw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int32 res = 0;\n" "if(("+toString(imm)+" & 0x20)>>5 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294967232;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rs1)+" != 0)\n" "{\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int32)cast_0 + imm_extended;\n" "etiss_int32 cast_1 = res; \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rs1)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
ecall_
static InstructionDefinition ecall_(ISA32_RISCV64, "ecall",(uint32_t) 0x73,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//ecall\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "exception = ETISS_RETURNCODE_SYSCALL; \n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
c_addi16sp_imm
static InstructionDefinition c_addi16sp_imm(ISA16_RISCV64, "c.addi16sp",(uint16_t) 0x6101,(uint16_t) 0xef83, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_int64 imm=0;static BitArrayRange R_imm_9(12, 12);etiss_int64 imm_9=R_imm_9.read(ba);imm+=imm_9<< 9;static BitArrayRange R_imm_4(6, 6);etiss_int64 imm_4=R_imm_4.read(ba);imm+=imm_4<< 4;static BitArrayRange R_imm_6(5, 5);etiss_int64 imm_6=R_imm_6.read(ba);imm+=imm_6<< 6;static BitArrayRange R_imm_7(4, 3);etiss_int64 imm_7=R_imm_7.read(ba);imm+=imm_7<< 7;static BitArrayRange R_imm_5(2, 2);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add(reg_name[2], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.addi16sp\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x200)>>9 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294966272;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[2]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X[2] = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_d_s_rd_frs1
static InstructionDefinition fcvt_d_s_rd_frs1(ISA32_RISCV64, "fcvt.d.s",(uint32_t) 0x42000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.d.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "res = fconv_f2d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffff), ("+toString(rm)+" & 0xff));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::gdbcore_
RISCV64GDBCore gdbcore_
Definition: RISCV64Arch.h:147
mret_
static InstructionDefinition mret_(ISA32_RISCV64, "mret",(uint32_t) 0x30200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//mret\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->CSR[3088] = (((RISCV64*)cpu)->CSR[768] & 0x1800)>>11;\n" "((RISCV64*)cpu)->CSR[768] ^= (((RISCV64*)cpu)->CSR[768] & 0x1800);\n" "((RISCV64*)cpu)->CSR[768] ^= ((etiss_uint32)((((RISCV64*)cpu)->CSR[768] & 0x80)>>4)) ^ (((RISCV64*)cpu)->CSR[768] & 0x8);\n" "cpu->instructionPointer = ((RISCV64*)cpu)->CSR[833];\n" "((RISCV64*)cpu)->CSR[0]= ((RISCV64*)cpu)->CSR[768];\n" "((RISCV64*)cpu)->CSR[256]=((RISCV64*)cpu)->CSR[768];\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
c_ldsp_rd_uimm_sp_
static InstructionDefinition c_ldsp_rd_uimm_sp_(ISA16_RISCV64, "c.ldsp",(uint16_t) 0x6002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 uimm=0;static BitArrayRange R_uimm_5(12, 12);etiss_uint64 uimm_5=R_uimm_5.read(ba);uimm+=uimm_5<< 5;static BitArrayRange R_uimm_3(6, 5);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(4, 2);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.ldsp\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X[2] + "+toString(uimm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:84
slti_rd_rs1_imm
static InstructionDefinition slti_rd_rs1_imm(ISA32_RISCV64, "slti",(uint32_t) 0x2013,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//slti\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int8 choose1 = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = imm_extended; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "if((etiss_int64)cast_1 < (etiss_int64)cast_0)\n" "{\n" "choose1 = 1;\n" "}\n" "else\n" "{\n" "choose1 = 0;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = choose1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
xori_rd_rs1_imm
static InstructionDefinition xori_rd_rs1_imm(ISA32_RISCV64, "xori",(uint32_t) 0x4013,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//xori\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_0 ^ imm_extended);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
bne_rs1_rs2_imm
static InstructionDefinition bne_rs1_rs2_imm(ISA32_RISCV64, "bne",(uint32_t) 0x1063,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 31);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;static BitArrayRange R_imm_5(30, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_1(11, 8);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(7, 7);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//bne\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294959104;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if(*((RISCV64*)cpu)->X["+toString(rs1)+"] != *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "choose1 = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
RISCV64::A6
etiss_uint64 A6
Definition: RISCV64.h:59
RISCV64::A1
etiss_uint64 A1
Definition: RISCV64.h:54
fcvt_s_lu_rd_xrs1
static InstructionDefinition fcvt_s_lu_rd_xrs1(ISA32_RISCV64, "fcvt.s.lu",(uint32_t) 0xd0300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.s.lu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "res = fcvt_64_32(*((RISCV64*)cpu)->X["+toString(rs1)+"], (etiss_uint32)3);\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fnmsub_s_rd_frs1_frs2_frs3
static InstructionDefinition fnmsub_s_rd_frs1_frs2_frs3(ISA32_RISCV64, "fnmsub.s",(uint32_t) 0x4b,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fnmsub.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "etiss_uint32 frs3 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fmadd_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], ((RISCV64*)cpu)->F["+toString(rs3)+"], (etiss_uint32)3, choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "frs3 = unbox_s(((RISCV64*)cpu)->F["+toString(rs3)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)3, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_addw_8_rd_8_rd_8_rs2
static InstructionDefinition c_addw_8_rd_8_rd_8_rs2(ISA16_RISCV64, "c.addw",(uint16_t) 0x9c21,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(9, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rd+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.addw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "res = (*((RISCV64*)cpu)->X["+toString(rd)+" + 8] & 0xffffffff) + (*((RISCV64*)cpu)->X["+toString(rs2)+" + 8] & 0xffffffff);\n" "etiss_int32 cast_0 = res; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+" + 8] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:538
lr_w_rd_rs1
static InstructionDefinition lr_w_rd_rs1(ISA32_RISCV64, "lr.w",(uint32_t) 0x1000202f,(uint32_t) 0xf9f0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lr.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "((RISCV64*)cpu)->RES = offs;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
amoxor_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoxor_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoxor.d",(uint32_t) 0x2000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoxor.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "res2 = (res ^ *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
xor_rd_rs1_rs2
static InstructionDefinition xor_rd_rs1_rs2(ISA32_RISCV64, "xor",(uint32_t) 0x4033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//xor\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] ^ *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
csrrwi_rd_csr_zimm
static InstructionDefinition csrrwi_rd_csr_zimm(ISA32_RISCV64, "csrrwi",(uint32_t) 0x5073,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 csr=0;static BitArrayRange R_csr_0(31, 20);etiss_uint64 csr_0=R_csr_0.read(ba);csr+=csr_0;etiss_uint64 zimm=0;static BitArrayRange R_zimm_0(19, 15);etiss_uint64 zimm_0=R_zimm_0.read(ba);zimm+=zimm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//csrrwi\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 mAddr = 0;\n" "etiss_int64 writeMask = 0;\n" "etiss_int64 writeMaskU = 0;\n" "etiss_int64 sAddr = 0;\n" "etiss_int64 writeMaskS = 0;\n" "etiss_int64 uAddr = 0;\n" "etiss_int64 writeMaskM = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((RISCV64*)cpu)->CSR["+toString(csr)+"];\n" "}\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((etiss_uint64)"+toString(zimm)+" & writeMask))&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = (etiss_uint64)"+toString(zimm)+";\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_li_rd_imm
static InstructionDefinition c_li_rd_imm(ISA16_RISCV64, "c.li",(uint16_t) 0x4001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(12, 12);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(6, 2);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.li\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x20)>>5 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294967232;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
mulhu_rd_rs1_rs2
static InstructionDefinition mulhu_rd_rs1_rs2(ISA32_RISCV64, "mulhu",(uint32_t) 0x2003033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//mulhu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "res = ((etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs1)+"] * (etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)(res >> 64);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_wu_d_rd_frs1
static InstructionDefinition fcvt_wu_d_rd_frs1(ISA32_RISCV64, "fcvt.wu.d",(uint32_t) 0xc2100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.wu.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_int32 cast_0 = fcvt_64_32((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (etiss_uint32)1, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::deleteTimer
void deleteTimer(etiss::Plugin *timer)
delete timer instance
Definition: RISCV64Arch.cpp:241
c_beqz_8_rs1_imm
static InstructionDefinition c_beqz_8_rs1_imm(ISA16_RISCV64, "c.beqz",(uint16_t) 0xc001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_8(12, 12);etiss_int64 imm_8=R_imm_8.read(ba);imm+=imm_8<< 8;static BitArrayRange R_imm_3(11, 10);etiss_int64 imm_3=R_imm_3.read(ba);imm+=imm_3<< 3;static BitArrayRange R_imm_6(6, 5);etiss_int64 imm_6=R_imm_6.read(ba);imm+=imm_6<< 6;static BitArrayRange R_imm_1(4, 3);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_5(2, 2);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.beqz\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x100)>>8 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294966784;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if(*((RISCV64*)cpu)->X["+toString(rs1)+" + 8] == 0)\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "choose1 = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 2;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
c_sw_8_rs2_uimm_8_rs1_
static InstructionDefinition c_sw_8_rs2_uimm_8_rs1_(ISA16_RISCV64, "c.sw",(uint16_t) 0xc000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_2(6, 6);etiss_uint64 uimm_2=R_uimm_2.read(ba);uimm+=uimm_2<< 2;static BitArrayRange R_uimm_6(5, 5);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.sw\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+" + 8] + "+toString(uimm)+";\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+" + 8];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
jal_rd_imm
static InstructionDefinition jal_rd_imm(ISA32_RISCV64, "jal",(uint32_t) 0x6f,(uint32_t) 0x7f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_20(31, 31);etiss_int64 imm_20=R_imm_20.read(ba);imm+=imm_20<< 20;static BitArrayRange R_imm_1(30, 21);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(20, 20);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;static BitArrayRange R_imm_12(19, 12);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//jal\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x100000)>>20 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4292870144;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "else\n" "{\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "cpu->instructionPointer = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
and_rd_rs1_rs2
static InstructionDefinition and_rd_rs1_rs2(ISA32_RISCV64, "and",(uint32_t) 0x7033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//and\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::listenerSupportedRegisters_
std::set< std::string > listenerSupportedRegisters_
Definition: RISCV64Arch.h:145
fsgnj_s_rd_frs1_frs2
static InstructionDefinition fsgnj_s_rd_frs1_frs2(ISA32_RISCV64, "fsgnj.s",(uint32_t) 0x20000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsgnj.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((((RISCV64*)cpu)->F["+toString(rs1)+"] & 2147483647) | (((RISCV64*)cpu)->F["+toString(rs2)+"] & -2147483648));\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "res = ((frs1 & 2147483647) | (frs2 & -2147483648));\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_or_8_rd_8_rs2
static InstructionDefinition c_or_8_rd_8_rs2(ISA16_RISCV64, "c.or",(uint16_t) 0x8c41,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(9, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rd+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.or\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 rd_idx = 0;\n" "rd_idx = "+toString(rd)+" + 8;\n" "*((RISCV64*)cpu)->X[rd_idx] = (*((RISCV64*)cpu)->X[rd_idx] | *((RISCV64*)cpu)->X["+toString(rs2)+" + 8]);\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
c_ebreak_
static InstructionDefinition c_ebreak_(ISA16_RISCV64, "c.ebreak",(uint16_t) 0x9002,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.ebreak\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "return ETISS_RETURNCODE_CPUFINISHED; \n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
srliw_rd_rs1_shamt
static InstructionDefinition srliw_rd_rs1_shamt(ISA32_RISCV64, "srliw",(uint32_t) 0x501b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_0(24, 20);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//srliw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 sh_val = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "sh_val = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) >> "+toString(shamt)+");\n" "etiss_int32 cast_0 = sh_val; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::RISCV64Arch
RISCV64Arch()
Definition: RISCV64Arch.cpp:50
RISCV64::SP
etiss_uint64 SP
Definition: RISCV64.h:45
c_bnez_8_rs1_imm
static InstructionDefinition c_bnez_8_rs1_imm(ISA16_RISCV64, "c.bnez",(uint16_t) 0xe001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_8(12, 12);etiss_int64 imm_8=R_imm_8.read(ba);imm+=imm_8<< 8;static BitArrayRange R_imm_3(11, 10);etiss_int64 imm_3=R_imm_3.read(ba);imm+=imm_3<< 3;static BitArrayRange R_imm_6(6, 5);etiss_int64 imm_6=R_imm_6.read(ba);imm+=imm_6<< 6;static BitArrayRange R_imm_1(4, 3);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_5(2, 2);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.bnez\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x100)>>8 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294966784;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if(*((RISCV64*)cpu)->X["+toString(rs1)+" + 8] != 0)\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "choose1 = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 2;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
c_lwsp_rd_sp_uimm
static InstructionDefinition c_lwsp_rd_sp_uimm(ISA16_RISCV64, "c.lwsp",(uint16_t) 0x4002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 uimm=0;static BitArrayRange R_uimm_5(12, 12);etiss_uint64 uimm_5=R_uimm_5.read(ba);uimm+=uimm_5<< 5;static BitArrayRange R_uimm_2(6, 4);etiss_uint64 uimm_2=R_uimm_2.read(ba);uimm+=uimm_2<< 2;static BitArrayRange R_uimm_6(3, 2);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.lwsp\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X[2] + "+toString(uimm)+";\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
etiss::plugin::gdb::GDBCore
provides to architecture dependent registers as defined by gdb
Definition: GDBCore.h:76
fsgnjx_s_rd_frs1_frs2
static InstructionDefinition fsgnjx_s_rd_frs1_frs2(ISA32_RISCV64, "fsgnjx.s",(uint32_t) 0x20002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsgnjx.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = (((RISCV64*)cpu)->F["+toString(rs1)+"] ^ (((RISCV64*)cpu)->F["+toString(rs2)+"] & -2147483648));\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "res = (frs1 ^ (frs2 & -2147483648));\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::newCPU
virtual ETISS_CPU * newCPU()
allocate new cpu structure
Definition: RISCV64Arch.cpp:60
auipc_rd_imm
static InstructionDefinition auipc_rd_imm(ISA32_RISCV64, "auipc",(uint32_t) 0x17,(uint32_t) 0x7f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 12);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//auipc\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x80000000)>>31 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0 + imm_extended;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::TP
etiss_uint64 TP
Definition: RISCV64.h:47
fcvt_s_l_rd_xrs1
static InstructionDefinition fcvt_s_l_rd_xrs1(ISA32_RISCV64, "fcvt.s.l",(uint32_t) 0xd0200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.s.l\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "res = fcvt_64_32(*((RISCV64*)cpu)->X["+toString(rs1)+"], (etiss_uint32)2);\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_l_d_rd_frs1
static InstructionDefinition fcvt_l_d_rd_frs1(ISA32_RISCV64, "fcvt.l.d",(uint32_t) 0xc2200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.l.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_int64 cast_0 = fcvt_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (etiss_uint32)0, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_lw_8_rd_uimm_8_rs1_
static InstructionDefinition c_lw_8_rd_uimm_8_rs1_(ISA16_RISCV64, "c.lw",(uint16_t) 0x4000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_2(6, 6);etiss_uint64 uimm_2=R_uimm_2.read(ba);uimm+=uimm_2<< 2;static BitArrayRange R_uimm_6(5, 5);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;etiss_uint64 rd=0;static BitArrayRange R_rd_0(4, 2);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.lw\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+" + 8] + "+toString(uimm)+";\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+" + 8] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
remuw_rd_rs1_rs2
static InstructionDefinition remuw_rd_rs1_rs2(ISA32_RISCV64, "remuw",(uint32_t) 0x200703b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//remuw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if((*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff) != 0)\n" "{\n" "etiss_int64 cast_0 = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) % (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff)); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "else\n" "{\n" "etiss_int64 cast_1 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
sc_d_rd_rs1_rs2
static InstructionDefinition sc_d_rd_rs1_rs2(ISA32_RISCV64, "sc.d",(uint32_t) 0x1800302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sc.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if(offs == ((RISCV64*)cpu)->RES)\n" "{\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = 0;\n" "}\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "else\n" "{\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = 1;\n" "}\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
fmul_s_rd_frs1_frs2
static InstructionDefinition fmul_s_rd_frs1_frs2(ISA32_RISCV64, "fmul.s",(uint32_t) 0x10000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmul.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fmul_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmul_s(frs1, frs2, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_mv_rd_rs2
static InstructionDefinition c_mv_rd_rs2(ISA16_RISCV64, "c.mv",(uint16_t) 0x8002,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(6, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.mv\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
sllw_rd_rs1_rs2
static InstructionDefinition sllw_rd_rs1_rs2(ISA32_RISCV64, "sllw",(uint32_t) 0x103b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sllw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 sh_val = 0;\n" "etiss_uint32 count = 0;\n" "etiss_int32 mask = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "mask = 31;\n" "count = ((*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff) & mask);\n" "sh_val = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) << count);\n" "etiss_int32 cast_0 = sh_val; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::RES
etiss_uint64 RES
Definition: RISCV64.h:81
remu_rd_rs1_rs2
static InstructionDefinition remu_rd_rs1_rs2(ISA32_RISCV64, "remu",(uint32_t) 0x2007033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//remu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if(*((RISCV64*)cpu)->X["+toString(rs2)+"] != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] % *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "}\n" "else\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
ETISS_CPU
basic cpu state structure needed for execution of any cpu architecture.
Definition: CPU.h:88
amoadd_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoadd_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoadd.d",(uint32_t) 0x302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoadd.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "res2 = res + *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
fnmadd_s_rd_frs1_frs2_frs3
static InstructionDefinition fnmadd_s_rd_frs1_frs2_frs3(ISA32_RISCV64, "fnmadd.s",(uint32_t) 0x4f,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fnmadd.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "etiss_uint32 frs3 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fmadd_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], ((RISCV64*)cpu)->F["+toString(rs3)+"], (etiss_uint32)2, choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "frs3 = unbox_s(((RISCV64*)cpu)->F["+toString(rs3)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)2, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:568
fnmadd_d_rd_frs1_frs2_frs3
static InstructionDefinition fnmadd_d_rd_frs1_frs2_frs3(ISA32_RISCV64, "fnmadd.d",(uint32_t) 0x200004f,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fnmadd.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs3)+"] & 0xffffffffffffffff), (etiss_uint32)2, choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::GP
etiss_uint64 GP
Definition: RISCV64.h:46
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:385
rd
static BitArrayRange rd(25, 21)
RISCV64::ZERO
etiss_uint64 ZERO
Definition: RISCV64.h:43
RISCV64::A0
etiss_uint64 A0
Definition: RISCV64.h:53
jalr_rd_rs1_imm
static InstructionDefinition jalr_rd_rs1_imm(ISA32_RISCV64, "jalr",(uint32_t) 0x67,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//jalr\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 new_pc = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "new_pc = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "else\n" "{\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "cpu->instructionPointer = (new_pc & ~1)&0xffffffffffffffff;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
sraiw_rd_rs1_shamt
static InstructionDefinition sraiw_rd_rs1_shamt(ISA32_RISCV64, "sraiw",(uint32_t) 0x4000501b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_0(24, 20);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sraiw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int32 sh_val = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "sh_val = ((etiss_int32)cast_0 >> "+toString(shamt)+");\n" "etiss_int32 cast_1 = sh_val; \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_w_s_rd_frs1
static InstructionDefinition fcvt_w_s_rd_frs1(ISA32_RISCV64, "fcvt.w.s",(uint32_t) 0xc0000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.w.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "if(64 == 32)\n" "{\n" "etiss_int32 cast_0 = fcvt_s(((RISCV64*)cpu)->F["+toString(rs1)+"], (etiss_uint32)0, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "etiss_int32 cast_1 = fcvt_s(frs1, (etiss_uint32)0, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_wu_s_rd_frs1
static InstructionDefinition fcvt_wu_s_rd_frs1(ISA32_RISCV64, "fcvt.wu.s",(uint32_t) 0xc0100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.wu.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "if(64 == 32)\n" "{\n" "etiss_int32 cast_0 = fcvt_s(((RISCV64*)cpu)->F["+toString(rs1)+"], (etiss_uint32)1, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "etiss_int32 cast_1 = fcvt_s(frs1, (etiss_uint32)1, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
ETISS_CPU::resourceUsages
etiss_uint64 resourceUsages[ETISS_MAX_RESOURCES]
how many cycles each resource is used
Definition: CPU.h:97
fsqrt_s_rd_frs1
static InstructionDefinition fsqrt_s_rd_frs1(ISA32_RISCV64, "fsqrt.s",(uint32_t) 0x58000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsqrt.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fsqrt_s(((RISCV64*)cpu)->F["+toString(rs1)+"], choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fsqrt_s(frs1, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::deleteCPU
virtual void deleteCPU(ETISS_CPU *)
delete cpu structure
Definition: RISCV64Arch.cpp:195
fence_i_
static InstructionDefinition fence_i_(ISA32_RISCV64, "fence_i",(uint32_t) 0x100f,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_uint64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fence_i\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->FENCE[1] = "+toString(imm)+";\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::ins_X
etiss_uint64 ins_X[32]
Definition: RISCV64.h:76
RISCV64::S1
etiss_uint64 S1
Definition: RISCV64.h:52
fclass_d_rd_frs1
static InstructionDefinition fclass_d_rd_frs1(ISA32_RISCV64, "fclass.d",(uint32_t) 0xe2001053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fclass.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = fclass_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff));\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::FCSR
etiss_uint32 FCSR
Definition: RISCV64.h:78
ETISS_CPU::mode
etiss_uint32 mode
instruction set mode of the processor
Definition: CPU.h:107
lui_rd_imm
static InstructionDefinition lui_rd_imm(ISA32_RISCV64, "lui",(uint32_t) 0x37,(uint32_t) 0x7f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 12);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lui\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x80000000)>>31 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = imm_extended;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amomaxu_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amomaxu_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amomaxu.d",(uint32_t) 0xe000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amomaxu.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "if(res1 < *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res1;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64ArchSpecificImp.h
etiss::instr::BitArrayRange
Acts as a view/filter to a BitArray.
Definition: Instruction.h:337
RISCV64::A3
etiss_uint64 A3
Definition: RISCV64.h:56
srl_rd_rs1_rs2
static InstructionDefinition srl_rd_rs1_rs2(ISA32_RISCV64, "srl",(uint32_t) 0x5033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//srl\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] >> (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 64 - 1));\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amominu_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amominu_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amominu.w",(uint32_t) 0xc000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amominu.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "if(res1 > *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res1;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
c_srai_8_rs1_shamt
static InstructionDefinition c_srai_8_rs1_shamt(ISA16_RISCV64, "c.srai",(uint16_t) 0x8401,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_5(12, 12);etiss_uint64 shamt_5=R_shamt_5.read(ba);shamt+=shamt_5<< 5;static BitArrayRange R_shamt_0(6, 2);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.srai\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 rs1_idx = 0;\n" "rs1_idx = "+toString(rs1)+" + 8;\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[rs1_idx]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X[rs1_idx] = ((etiss_int64)cast_0 >> "+toString(shamt)+");\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::getGDBCore
virtual etiss::plugin::gdb::GDBCore & getGDBCore()
get the GDBcore for RISCV64 architecture
Definition: RISCV64Arch.cpp:228
c_fsdsp_rs2_uimm_x2_
static InstructionDefinition c_fsdsp_rs2_uimm_x2_(ISA16_RISCV64, "c.fsdsp",(uint16_t) 0xa002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(6, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(9, 7);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.fsdsp\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X[2] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
sfence_vma_
static InstructionDefinition sfence_vma_(ISA32_RISCV64, "sfence.vma",(uint32_t) 0x12000073,(uint32_t) 0xfe007fff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[2], 64);partInit.getAffectedRegisters().add(reg_name[3], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sfence.vma\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->FENCE[2] = "+toString(rs1)+";\n" "((RISCV64*)cpu)->FENCE[3] = "+toString(rs2)+";\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
divw_rd_rs1_rs2
static InstructionDefinition divw_rd_rs1_rs2(ISA32_RISCV64, "divw",(uint32_t) 0x200403b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//divw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int32 MMIN = 0;\n" "etiss_int32 M1 = 0;\n" "etiss_int32 ONE = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if(*((RISCV64*)cpu)->X["+toString(rs2)+"] != 0)\n" "{\n" "M1 = - 1;\n" "ONE = 1;\n" "MMIN = (ONE << 31);\n" "if(((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) == MMIN) && ((*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff) == M1))\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ( - 1 << 31);\n" "}\n" "else\n" "{\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "etiss_int64 cast_2 = ((etiss_int64)cast_1 / (etiss_int64)cast_0); \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_2;\n" "}\n" "}\n" "else\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = - 1;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmsub_s_rd_frs1_frs2_frs3
static InstructionDefinition fmsub_s_rd_frs1_frs2_frs3(ISA32_RISCV64, "fmsub.s",(uint32_t) 0x47,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmsub.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "etiss_uint32 frs3 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fmadd_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], ((RISCV64*)cpu)->F["+toString(rs3)+"], (etiss_uint32)1, choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "frs3 = unbox_s(((RISCV64*)cpu)->F["+toString(rs3)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)1, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_d_l_rd_rs1
static InstructionDefinition fcvt_d_l_rd_rs1(ISA32_RISCV64, "fcvt.d.l",(uint32_t) 0xd2200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.d.l\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = fcvt_d((etiss_int64)cast_0, (etiss_uint32)2, ("+toString(rm)+" & 0xff));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_swsp_rs2_uimm_sp_
static InstructionDefinition c_swsp_rs2_uimm_sp_(ISA16_RISCV64, "c.swsp",(uint16_t) 0xc002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(6, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_2(12, 9);etiss_uint64 uimm_2=R_uimm_2.read(ba);uimm+=uimm_2<< 2;static BitArrayRange R_uimm_6(8, 7);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.swsp\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X[2] + "+toString(uimm)+";\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
ETISS_CPU::instructionPointer
etiss_uint64 instructionPointer
pointer to next instruction.
Definition: CPU.h:92
addi_rd_rs1_imm
static InstructionDefinition addi_rd_rs1_imm(ISA32_RISCV64, "addi",(uint32_t) 0x13,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//addi\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0 + imm_extended;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::mm::MMU
Definition: MMU.h:75
sub_rd_rs1_rs2
static InstructionDefinition sub_rd_rs1_rs2(ISA32_RISCV64, "sub",(uint32_t) 0x40000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sub\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = *((RISCV64*)cpu)->X["+toString(rs1)+"] - *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
srlw_rd_rs1_rs2
static InstructionDefinition srlw_rd_rs1_rs2(ISA32_RISCV64, "srlw",(uint32_t) 0x503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//srlw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 sh_val = 0;\n" "etiss_uint32 count = 0;\n" "etiss_int32 mask = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "mask = 31;\n" "count = ((*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff) & mask);\n" "sh_val = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) >> count);\n" "etiss_int32 cast_0 = sh_val; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_d_lu_rd_rs1
static InstructionDefinition fcvt_d_lu_rd_rs1(ISA32_RISCV64, "fcvt.d.lu",(uint32_t) 0xd2300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.d.lu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "res = fcvt_d((etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs1)+"], (etiss_uint32)3, ("+toString(rm)+" & 0xff));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
tlb_overlap_handler
int32_t tlb_overlap_handler(int32_t fault, MMU *mmu, uint64_t vma, MM_ACCESS access)
Definition: RISCV64Arch.cpp:45
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:52
fmax_s_rd_frs1_frs2
static InstructionDefinition fmax_s_rd_frs1_frs2(ISA32_RISCV64, "fmax.s",(uint32_t) 0x28001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmax.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fsel_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], (etiss_uint32)1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "res = fsel_s(frs1, frs2, (etiss_uint32)1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::CPUArch
the interface to translate instructions of and processor architecture
Definition: CPUArch.h:157
RISCV64::T2
etiss_uint64 T2
Definition: RISCV64.h:50
reg_name
static const char *const reg_name[]
Definition: RISCV64Arch.cpp:252
fcvt_s_w_rd_rs1
static InstructionDefinition fcvt_s_w_rd_rs1(ISA32_RISCV64, "fcvt.s.w",(uint32_t) 0xd0000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.s.w\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fcvt_s((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff), (etiss_uint32)2, ("+toString(rm)+" & 0xff));\n" "}\n" "else\n" "{\n" "res = fcvt_s((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff), (etiss_uint32)2, ("+toString(rm)+" & 0xff));\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::F
etiss_uint64 F[32]
Definition: RISCV64.h:77
amomaxu_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amomaxu_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amomaxu.w",(uint32_t) 0xe000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amomaxu.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "if(res1 < *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res1;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
csrrci_rd_csr_zimm
static InstructionDefinition csrrci_rd_csr_zimm(ISA32_RISCV64, "csrrci",(uint32_t) 0x7073,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 csr=0;static BitArrayRange R_csr_0(31, 20);etiss_uint64 csr_0=R_csr_0.read(ba);csr+=csr_0;etiss_uint64 zimm=0;static BitArrayRange R_zimm_0(19, 15);etiss_uint64 zimm_0=R_zimm_0.read(ba);zimm+=zimm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//csrrci\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 mAddr = 0;\n" "etiss_int64 writeMask = 0;\n" "etiss_int64 writeMaskU = 0;\n" "etiss_int64 sAddr = 0;\n" "etiss_int64 writeMaskS = 0;\n" "etiss_int64 uAddr = 0;\n" "etiss_int64 writeMaskM = 0;\n" "res = ((RISCV64*)cpu)->CSR["+toString(csr)+"];\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "if("+toString(zimm)+" != 0)\n" "{\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((res & ~(etiss_uint64)"+toString(zimm)+") & writeMask))&0xffffffffffffffff&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = (res & ~(etiss_uint64)"+toString(zimm)+")&0xffffffffffffffff;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::instr::InstructionDefinition
maps to Instruction
Definition: Instruction.h:961
csrrsi_rd_csr_zimm
static InstructionDefinition csrrsi_rd_csr_zimm(ISA32_RISCV64, "csrrsi",(uint32_t) 0x6073,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 csr=0;static BitArrayRange R_csr_0(31, 20);etiss_uint64 csr_0=R_csr_0.read(ba);csr+=csr_0;etiss_uint64 zimm=0;static BitArrayRange R_zimm_0(19, 15);etiss_uint64 zimm_0=R_zimm_0.read(ba);zimm+=zimm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//csrrsi\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 mAddr = 0;\n" "etiss_int64 writeMask = 0;\n" "etiss_int64 writeMaskU = 0;\n" "etiss_int64 sAddr = 0;\n" "etiss_int64 writeMaskS = 0;\n" "etiss_int64 uAddr = 0;\n" "etiss_int64 writeMaskM = 0;\n" "res = ((RISCV64*)cpu)->CSR["+toString(csr)+"];\n" "if("+toString(zimm)+" != 0)\n" "{\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((res | (etiss_uint64)"+toString(zimm)+") & writeMask))&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = (res | (etiss_uint64)"+toString(zimm)+");\n" "}\n" "}\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_jalr_rs1
static InstructionDefinition c_jalr_rs1(ISA16_RISCV64, "c.jalr",(uint16_t) 0x9002,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(11, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.jalr\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "*((RISCV64*)cpu)->X[1] = "+toString((uint64_t) ic.current_address_)+"ULL + 2;\n" "cpu->instructionPointer = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
addiw_rd_rs1_imm
static InstructionDefinition addiw_rd_rs1_imm(ISA32_RISCV64, "addiw",(uint32_t) 0x1b,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//addiw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int32 res = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int32)cast_0 + imm_extended;\n" "etiss_int32 cast_1 = res; \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
sll_rd_rs1_rs2
static InstructionDefinition sll_rd_rs1_rs2(ISA32_RISCV64, "sll",(uint32_t) 0x1033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sll\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] << (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 64 - 1));\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amoor_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoor_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoor.w",(uint32_t) 0x4000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoor.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "res2 = (res1 | *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
sltiu_rd_rs1_imm
static InstructionDefinition sltiu_rd_rs1_imm(ISA32_RISCV64, "sltiu",(uint32_t) 0x3013,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sltiu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 full_imm = 0;\n" "etiss_int8 choose1 = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = imm_extended; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "full_imm = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if((etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs1)+"] < (etiss_uint64)full_imm)\n" "{\n" "choose1 = 1;\n" "}\n" "else\n" "{\n" "choose1 = 0;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = choose1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_sub_8_rd_8_rs2
static InstructionDefinition c_sub_8_rd_8_rs2(ISA16_RISCV64, "c.sub",(uint16_t) 0x8c01,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(9, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rd+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.sub\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 rd_idx = 0;\n" "rd_idx = "+toString(rd)+" + 8;\n" "*((RISCV64*)cpu)->X[rd_idx] = *((RISCV64*)cpu)->X[rd_idx] - *((RISCV64*)cpu)->X["+toString(rs2)+" + 8];\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
fmv_w_x_rd_rs1
static InstructionDefinition fmv_w_x_rd_rs1(ISA32_RISCV64, "fmv.w.x",(uint32_t) 0xf0000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmv.w.x\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 upper = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff);\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)(*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff));\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amominu_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amominu_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amominu.d",(uint32_t) 0xc000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amominu.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "if(res > *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64_Pipeline1
#define RISCV64_Pipeline1
Definition: RISCV64Arch.cpp:39
RISCV64Arch::getInstructionSizeInBytes
virtual unsigned getInstructionSizeInBytes()
Definition: RISCV64Arch.cpp:211
RISCV64Arch::getListenerSupportedRegisters
virtual const std::set< std::string > & getListenerSupportedRegisters()
Definition: RISCV64Arch.cpp:55
RISCV64::S9
etiss_uint64 S9
Definition: RISCV64.h:68
fadd_s_rd_frs1_frs2
static InstructionDefinition fadd_s_rd_frs1_frs2(ISA32_RISCV64, "fadd.s",(uint32_t) 0x53,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fadd.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fadd_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fadd_s(frs1, frs2, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
feq_d_rd_frs1_frs2
static InstructionDefinition feq_d_rd_frs1_frs2(ISA32_RISCV64, "feq.d",(uint32_t) 0xa2002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//feq.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (etiss_uint32)0);\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmin_s_rd_frs1_frs2
static InstructionDefinition fmin_s_rd_frs1_frs2(ISA32_RISCV64, "fmin.s",(uint32_t) 0x28000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmin.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fsel_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], (etiss_uint32)0);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "res = fsel_s(frs1, frs2, (etiss_uint32)0);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fdiv_s_rd_frs1_frs2
static InstructionDefinition fdiv_s_rd_frs1_frs2(ISA32_RISCV64, "fdiv.s",(uint32_t) 0x18000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fdiv.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fdiv_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fdiv_s(frs1, frs2, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
slli_rd_rs1_shamt
static InstructionDefinition slli_rd_rs1_shamt(ISA32_RISCV64, "slli",(uint32_t) 0x1013,(uint32_t) 0xfc00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_0(25, 20);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//slli\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] << "+toString(shamt)+");\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_d_w_rd_rs1
static InstructionDefinition fcvt_d_w_rd_rs1(ISA32_RISCV64, "fcvt.d.w",(uint32_t) 0xd2000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.d.w\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = fcvt_32_64((etiss_int64)cast_0, (etiss_uint32)2, ("+toString(rm)+" & 0xff));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_d_wu_rd_rs1
static InstructionDefinition fcvt_d_wu_rd_rs1(ISA32_RISCV64, "fcvt.d.wu",(uint32_t) 0xd2100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.d.wu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "res = fcvt_32_64((etiss_uint64)(*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff), (etiss_uint32)3, ("+toString(rm)+" & 0xff));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmadd_s_rd_frs1_frs2_frs3
static InstructionDefinition fmadd_s_rd_frs1_frs2_frs3(ISA32_RISCV64, "fmadd.s",(uint32_t) 0x43,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmadd.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "etiss_uint32 frs3 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fmadd_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], ((RISCV64*)cpu)->F["+toString(rs3)+"], (etiss_uint32)0, choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "frs3 = unbox_s(((RISCV64*)cpu)->F["+toString(rs3)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)0, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::cfg
Configuration & cfg(const std::string &cfgName)
Get reference of the global ETISS configuration object.
Definition: Misc.cpp:560
amoor_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoor_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoor.d",(uint32_t) 0x4000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoor.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "res2 = (res | *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
mul_rd_rs1_rs2
static InstructionDefinition mul_rd_rs1_rs2(ISA32_RISCV64, "mul",(uint32_t) 0x2000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//mul\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "res = ((etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs1)+"] * (etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)res;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
uret_
static InstructionDefinition uret_(ISA32_RISCV64, "uret",(uint32_t) 0x200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//uret\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->CSR[3088] = 0;\n" "((RISCV64*)cpu)->CSR[0] ^= ((etiss_uint32)((((RISCV64*)cpu)->CSR[0] & 0x10)>>4)) ^ (((RISCV64*)cpu)->CSR[0] & 0x1);\n" "cpu->instructionPointer = ((RISCV64*)cpu)->CSR[65];\n" "((RISCV64*)cpu)->CSR[768]= ((RISCV64*)cpu)->CSR[0];\n" "((RISCV64*)cpu)->CSR[256]=((RISCV64*)cpu)->CSR[0];\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
fence_
static InstructionDefinition fence_(ISA32_RISCV64, "fence",(uint32_t) 0xf,(uint32_t) 0xf000707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 succ=0;static BitArrayRange R_succ_0(23, 20);etiss_uint64 succ_0=R_succ_0.read(ba);succ+=succ_0;etiss_uint64 pred=0;static BitArrayRange R_pred_0(27, 24);etiss_uint64 pred_0=R_pred_0.read(ba);pred+=pred_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[0], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fence\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->FENCE[0] = (("+toString(pred)+" << 4) | "+toString(succ)+");\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_add_rd_rs2
static InstructionDefinition c_add_rd_rs2(ISA16_RISCV64, "c.add",(uint16_t) 0x9002,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(6, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rd], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.add\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = *((RISCV64*)cpu)->X["+toString(rd)+"] + *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
fsgnjn_d_rd_frs1_frs2
static InstructionDefinition fsgnjn_d_rd_frs1_frs2(ISA32_RISCV64, "fsgnjn.d",(uint32_t) 0x22001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsgnjn.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 ONE = 0;\n" "etiss_int64 upper = 0;\n" "etiss_int64 MSK1 = 0;\n" "etiss_int64 MSK2 = 0;\n" "ONE = 1;\n" "MSK1 = (ONE << 63);\n" "MSK2 = MSK1 - 1;\n" "res = (((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff) & MSK2) | (~(((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff) & MSK1))&0xffffffffffffffff;\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fnmsub_d_rd_frs1_frs2_frs3
static InstructionDefinition fnmsub_d_rd_frs1_frs2_frs3(ISA32_RISCV64, "fnmsub.d",(uint32_t) 0x200004b,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fnmsub.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs3)+"] & 0xffffffffffffffff), (etiss_uint32)3, choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
rem_rd_rs1_rs2
static InstructionDefinition rem_rd_rs1_rs2(ISA32_RISCV64, "rem",(uint32_t) 0x2006033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//rem\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int32 XLM1 = 0;\n" "etiss_int64 MMIN = 0;\n" "etiss_int64 M1 = 0;\n" "etiss_int64 ONE = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if(*((RISCV64*)cpu)->X["+toString(rs2)+"] != 0)\n" "{\n" "M1 = - 1;\n" "XLM1 = 64 - 1;\n" "ONE = 1;\n" "MMIN = (ONE << XLM1);\n" "if((*((RISCV64*)cpu)->X["+toString(rs1)+"] == MMIN) && (*((RISCV64*)cpu)->X["+toString(rs2)+"] == M1))\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = 0;\n" "}\n" "else\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_1 % (etiss_int64)cast_0);\n" "}\n" "}\n" "else\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::RA
etiss_uint64 RA
Definition: RISCV64.h:44
c_xor_8_rd_8_rs2
static InstructionDefinition c_xor_8_rd_8_rs2(ISA16_RISCV64, "c.xor",(uint16_t) 0x8c21,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(9, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rd+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.xor\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 rd_idx = 0;\n" "rd_idx = "+toString(rd)+" + 8;\n" "*((RISCV64*)cpu)->X[rd_idx] = (*((RISCV64*)cpu)->X[rd_idx] ^ *((RISCV64*)cpu)->X["+toString(rs2)+" + 8]);\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::CodePart::getRegisterDependencies
RegisterSet & getRegisterDependencies()
Definition: CodePart.h:413
addw_
static InstructionDefinition addw_(ISA32_RISCV64, "addw",(uint32_t) 0x3b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//addw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "res = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) + (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff);\n" "etiss_int32 cast_0 = res; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Timer
Definition: RISCV64Timer.h:66
RISCV64::T4
etiss_uint64 T4
Definition: RISCV64.h:72
fmv_x_w_rd_frs1
static InstructionDefinition fmv_x_w_rd_frs1(ISA32_RISCV64, "fmv.x.w",(uint32_t) 0xe0000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmv.x.w\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 cast_0 = (((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_sdsp_rs2_uimm_sp_
static InstructionDefinition c_sdsp_rs2_uimm_sp_(ISA16_RISCV64, "c.sdsp",(uint16_t) 0xe002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(6, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(9, 7);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.sdsp\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X[2] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
ori_rd_rs1_imm
static InstructionDefinition ori_rd_rs1_imm(ISA32_RISCV64, "ori",(uint32_t) 0x6013,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//ori\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_0 | imm_extended);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
uint32_t
unsigned int uint32_t
Definition: stddef.h:23
fle_s_rd_frs1_frs2
static InstructionDefinition fle_s_rd_frs1_frs2(ISA32_RISCV64, "fle.s",(uint32_t) 0xa0000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fle.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], (etiss_uint32)1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_s(frs1, frs2, (etiss_uint32)1);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
flw_rd_imm_xrs1_
static InstructionDefinition flw_rd_imm_xrs1_(ISA32_RISCV64, "flw",(uint32_t) 0x2007,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//flw\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "res = MEM_offs;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
amoand_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoand_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoand.w",(uint32_t) 0x6000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoand.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "res2 = (res1 & *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
remw_rd_rs1_rs2
static InstructionDefinition remw_rd_rs1_rs2(ISA32_RISCV64, "remw",(uint32_t) 0x200603b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//remw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int32 MMIN = 0;\n" "etiss_int32 M1 = 0;\n" "etiss_int32 ONE = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if(*((RISCV64*)cpu)->X["+toString(rs2)+"] != 0)\n" "{\n" "M1 = - 1;\n" "ONE = 1;\n" "MMIN = (ONE << 31);\n" "if(((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) == MMIN) && (*((RISCV64*)cpu)->X["+toString(rs2)+"] == M1))\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = 0;\n" "}\n" "else\n" "{\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "etiss_int64 cast_2 = ((etiss_int64)cast_1 % (etiss_int64)cast_0); \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_2;\n" "}\n" "}\n" "else\n" "{\n" "etiss_int64 cast_3 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_3 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_3 =0x0 + (etiss_uint64)cast_3 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_3;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::S2
etiss_uint64 S2
Definition: RISCV64.h:61
RISCV64::S4
etiss_uint64 S4
Definition: RISCV64.h:63
etiss::toString
std::string toString(const T &val)
conversion of type T to std::string.
Definition: Misc.h:174
c_j_imm
static InstructionDefinition c_j_imm(ISA16_RISCV64, "c.j",(uint16_t) 0xa001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_int64 imm=0;static BitArrayRange R_imm_11(12, 12);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;static BitArrayRange R_imm_4(11, 11);etiss_int64 imm_4=R_imm_4.read(ba);imm+=imm_4<< 4;static BitArrayRange R_imm_8(10, 9);etiss_int64 imm_8=R_imm_8.read(ba);imm+=imm_8<< 8;static BitArrayRange R_imm_10(8, 8);etiss_int64 imm_10=R_imm_10.read(ba);imm+=imm_10<< 10;static BitArrayRange R_imm_6(7, 7);etiss_int64 imm_6=R_imm_6.read(ba);imm+=imm_6<< 6;static BitArrayRange R_imm_7(6, 6);etiss_int64 imm_7=R_imm_7.read(ba);imm+=imm_7<< 7;static BitArrayRange R_imm_1(5, 3);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_5(2, 2);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.j\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "cpu->instructionPointer = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
etiss::CodeBlock::fileglobalCode
std::set< std::string > & fileglobalCode()
Definition: CodePart.h:603
amomax_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amomax_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amomax.d",(uint32_t) 0xa000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amomax.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "etiss_int64 cast_2 = res; \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "if((etiss_int64)cast_2 < (etiss_int64)cast_1)\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
amoadd_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoadd_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoadd.w",(uint32_t) 0x202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoadd.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "res2 = res1 + *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64::S8
etiss_uint64 S8
Definition: RISCV64.h:67
c_andi_8_rs1_imm
static InstructionDefinition c_andi_8_rs1_imm(ISA16_RISCV64, "c.andi",(uint16_t) 0x8801,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(12, 12);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(6, 2);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.andi\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int8 rs1_idx = 0;\n" "if(("+toString(imm)+" & 0x20)>>5 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294967232;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "rs1_idx = "+toString(rs1)+" + 8;\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X[rs1_idx]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X[rs1_idx] = ((etiss_int64)cast_0 & imm_extended);\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
RISCV64::A2
etiss_uint64 A2
Definition: RISCV64.h:55
fsub_s_rd_frs1_frs2
static InstructionDefinition fsub_s_rd_frs1_frs2(ISA32_RISCV64, "fsub.s",(uint32_t) 0x8000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsub.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fsub_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], choose1);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fsub_s(frs1, frs2, choose1);\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_s_d_rd_frs1
static InstructionDefinition fcvt_s_d_rd_frs1(ISA32_RISCV64, "fcvt.s.d",(uint32_t) 0x40100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.s.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "res = fconv_d2f(((RISCV64*)cpu)->F["+toString(rs1)+"], ("+toString(rm)+" & 0xff));\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
bgeu_rs1_rs2_imm
static InstructionDefinition bgeu_rs1_rs2_imm(ISA32_RISCV64, "bgeu",(uint32_t) 0x7063,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 31);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;static BitArrayRange R_imm_5(30, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_1(11, 8);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(7, 7);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//bgeu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294959104;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if(*((RISCV64*)cpu)->X["+toString(rs1)+"] >= *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "choose1 = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
ISA16_RISCV64
etiss::instr::InstructionGroup ISA16_RISCV64("ISA16_RISCV64", 16)
bge_rs1_rs2_imm
static InstructionDefinition bge_rs1_rs2_imm(ISA32_RISCV64, "bge",(uint32_t) 0x5063,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 31);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;static BitArrayRange R_imm_5(30, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_1(11, 8);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(7, 7);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//bge\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294959104;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "if((etiss_int64)cast_1 >= (etiss_int64)cast_0)\n" "{\n" "etiss_int64 cast_2 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "choose1 = (etiss_int64)cast_2 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
RISCV64::S3
etiss_uint64 S3
Definition: RISCV64.h:62
c_slli_rs1_shamt
static InstructionDefinition c_slli_rs1_shamt(ISA16_RISCV64, "c.slli",(uint16_t) 0x2,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(11, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_5(12, 12);etiss_uint64 shamt_5=R_shamt_5.read(ba);shamt+=shamt_5<< 5;static BitArrayRange R_shamt_0(6, 2);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.slli\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rs1)+" == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" "}\n" "*((RISCV64*)cpu)->X["+toString(rs1)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] << "+toString(shamt)+");\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
ETISS_CPU::cpuTime_ps
etiss_uint64 cpuTime_ps
simulation time of cpu
Definition: CPU.h:95
RISCV64
struct RISCV64 RISCV64
Definition: RISCV64.h:85
RISCV64Arch::newTimer
etiss::Plugin * newTimer(ETISS_CPU *cpu)
create a simple default timer implementaion instance for this architecture.
Definition: RISCV64Arch.cpp:235
RISCV64Arch::getMaximumInstructionSizeInBytes
virtual unsigned getMaximumInstructionSizeInBytes()
Definition: RISCV64Arch.cpp:204
RISCV64Arch::resetCPU
virtual void resetCPU(ETISS_CPU *cpu, etiss::uint64 *startpointer)
reset cpu (structure)
Definition: RISCV64Arch.cpp:67
or_rd_rs1_rs2
static InstructionDefinition or_rd_rs1_rs2(ISA32_RISCV64, "or",(uint32_t) 0x6033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//or\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] | *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
lbu_rd_imm_rs1_
static InstructionDefinition lbu_rd_imm_rs1_(ISA32_RISCV64, "lbu",(uint32_t) 0x4003,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lbu\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint8 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,1);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)MEM_offs;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
beq_rs1_rs2_imm
static InstructionDefinition beq_rs1_rs2_imm(ISA32_RISCV64, "beq",(uint32_t) 0x63,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 31);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;static BitArrayRange R_imm_5(30, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_1(11, 8);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(7, 7);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//beq\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294959104;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if(*((RISCV64*)cpu)->X["+toString(rs1)+"] == *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "choose1 = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
RISCV64::CSR
etiss_uint64 CSR[4096]
Definition: RISCV64.h:79
c_nop_
static InstructionDefinition c_nop_(ISA16_RISCV64, "c.nop",(uint16_t) 0x1,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.nop\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
c_lui_rd_imm
static InstructionDefinition c_lui_rd_imm(ISA16_RISCV64, "c.lui",(uint16_t) 0x6001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 imm=0;static BitArrayRange R_imm_17(12, 12);etiss_uint64 imm_17=R_imm_17.read(ba);imm+=imm_17<< 17;static BitArrayRange R_imm_12(6, 2);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.lui\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x20000)>>17 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294705152;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" "}\n" "if(imm_extended == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
lb_rd_imm_rs1_
static InstructionDefinition lb_rd_imm_rs1_(ISA32_RISCV64, "lb",(uint32_t) 0x3,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lb\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint8 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,1);\n" "etiss_int8 cast_1 = MEM_offs; \n" "if((etiss_int8)((etiss_uint8)cast_1 - 0x80) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint8)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
sh_rs2_imm_rs1_
static InstructionDefinition sh_rs2_imm_rs1_(ISA32_RISCV64, "sh",(uint32_t) 0x1023,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(31, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(11, 7);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sh\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint16 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,2);\n" "if((offs + 2 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
fmadd_d_rd_frs1_frs2_frs3
static InstructionDefinition fmadd_d_rd_frs1_frs2_frs3(ISA32_RISCV64, "fmadd.d",(uint32_t) 0x2000043,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rs3=0;static BitArrayRange R_rs3_0(31, 27);etiss_uint64 rs3_0=R_rs3_0.read(ba);rs3+=rs3_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmadd.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmadd_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs3)+"] & 0xffffffffffffffff), (etiss_uint64)0, choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::FENCE
etiss_uint64 FENCE[4]
Definition: RISCV64.h:80
fcvt_lu_s_rd_frs1
static InstructionDefinition fcvt_lu_s_rd_frs1(ISA32_RISCV64, "fcvt.lu.s",(uint32_t) 0xc0300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.lu.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_uint32 flags = 0;\n" "res = fcvt_32_64(unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]), (etiss_uint32)1, ("+toString(rm)+" & 0xff));\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)res;\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::headers_
std::set< std::string > headers_
Definition: RISCV64Arch.h:146
bltu_rs1_rs2_imm
static InstructionDefinition bltu_rs1_rs2_imm(ISA32_RISCV64, "bltu",(uint32_t) 0x6063,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 31);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;static BitArrayRange R_imm_5(30, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_1(11, 8);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(7, 7);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//bltu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294959104;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if(*((RISCV64*)cpu)->X["+toString(rs1)+"] < *((RISCV64*)cpu)->X["+toString(rs2)+"])\n" "{\n" "etiss_int64 cast_0 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "choose1 = (etiss_int64)cast_0 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
RISCV64::A5
etiss_uint64 A5
Definition: RISCV64.h:58
fcvt_lu_d_rd_frs1
static InstructionDefinition fcvt_lu_d_rd_frs1(ISA32_RISCV64, "fcvt.lu.d",(uint32_t) 0xc2300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.lu.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_int64 cast_0 = fcvt_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (etiss_uint32)1, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_srli_8_rs1_shamt
static InstructionDefinition c_srli_8_rs1_shamt(ISA16_RISCV64, "c.srli",(uint16_t) 0x8001,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_5(12, 12);etiss_uint64 shamt_5=R_shamt_5.read(ba);shamt+=shamt_5<< 5;static BitArrayRange R_shamt_0(6, 2);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.srli\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 rs1_idx = 0;\n" "rs1_idx = "+toString(rs1)+" + 8;\n" "*((RISCV64*)cpu)->X[rs1_idx] = (*((RISCV64*)cpu)->X[rs1_idx] >> "+toString(shamt)+");\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
c_jr_rs1
static InstructionDefinition c_jr_rs1(ISA16_RISCV64, "c.jr",(uint16_t) 0x8002,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(11, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.jr\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "cpu->instructionPointer = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
c_sd_8_rs2_uimm_8_rs1_
static InstructionDefinition c_sd_8_rs2_uimm_8_rs1_(ISA16_RISCV64, "c.sd",(uint16_t) 0xe000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(6, 5);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.sd\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+" + 8] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+" + 8];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
ld_rd_imm_rs1_
static InstructionDefinition ld_rd_imm_rs1_(ISA32_RISCV64, "ld",(uint32_t) 0x3003,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//ld\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_1 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
fmul_d_rd_frs1_frs2
static InstructionDefinition fmul_d_rd_frs1_frs2(ISA32_RISCV64, "fmul.d",(uint32_t) 0x12000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmul.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fmul_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
sw_rs2_imm_rs1_
static InstructionDefinition sw_rs2_imm_rs1_(ISA32_RISCV64, "sw",(uint32_t) 0x2023,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(31, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(11, 7);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sw\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
c_fsd_rs2_uimm_8_rs1_
static InstructionDefinition c_fsd_rs2_uimm_8_rs1_(ISA16_RISCV64, "c.fsd",(uint16_t) 0xa000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(6, 5);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.fsd\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+" + 8] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV64*)cpu)->F["+toString(rs2)+" + 8] & 0xffffffffffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
srli_rd_rs1_shamt
static InstructionDefinition srli_rd_rs1_shamt(ISA32_RISCV64, "srli",(uint32_t) 0x5013,(uint32_t) 0xfc00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 shamt=0;static BitArrayRange R_shamt_0(25, 20);etiss_uint64 shamt_0=R_shamt_0.read(ba);shamt+=shamt_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//srli\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (*((RISCV64*)cpu)->X["+toString(rs1)+"] >> "+toString(shamt)+");\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
mulhsu_rd_rs1_rs2
static InstructionDefinition mulhsu_rd_rs1_rs2(ISA32_RISCV64, "mulhsu",(uint32_t) 0x2002033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//mulhsu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = ((etiss_int64)cast_0 * (etiss_uint64)*((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)(res >> 64);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmax_d_rd_frs1_frs2
static InstructionDefinition fmax_d_rd_frs1_frs2(ISA32_RISCV64, "fmax.d",(uint32_t) 0x2a001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmax.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "res = fsel_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (etiss_uint32)1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmv_x_d_rd_frs1
static InstructionDefinition fmv_x_d_rd_frs1(ISA32_RISCV64, "fmv.x.d",(uint32_t) 0xe2000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmv.x.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 cast_0 = ((RISCV64*)cpu)->F["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
lh_rd_imm_rs1_
static InstructionDefinition lh_rd_imm_rs1_(ISA32_RISCV64, "lh",(uint32_t) 0x1003,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lh\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint16 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,2);\n" "etiss_int16 cast_1 = MEM_offs; \n" "if((etiss_int16)((etiss_uint16)cast_1 - 0x8000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint16)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
sra_rd_rs1_rs2
static InstructionDefinition sra_rd_rs1_rs2(ISA32_RISCV64, "sra",(uint32_t) 0x40005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sra\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_0 >> (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 64 - 1));\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fld_rd_imm_rs1_
static InstructionDefinition fld_rd_imm_rs1_(ISA32_RISCV64, "fld",(uint32_t) 0x3007,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fld\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "res = MEM_offs;\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
sraw_rd_rs1_rs2
static InstructionDefinition sraw_rd_rs1_rs2(ISA32_RISCV64, "sraw",(uint32_t) 0x4000503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sraw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 sh_val = 0;\n" "etiss_uint32 count = 0;\n" "etiss_int32 mask = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "mask = 31;\n" "count = ((*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff) & mask);\n" "etiss_int64 cast_0 = (*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "sh_val = ((etiss_int32)cast_0 >> count);\n" "etiss_int32 cast_1 = sh_val; \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint32)cast_1 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_1;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fsw_rs2_imm_xrs1_
static InstructionDefinition fsw_rs2_imm_xrs1_(ISA32_RISCV64, "fsw",(uint32_t) 0x2027,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(31, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(11, 7);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsw\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64
Definition: RISCV64.h:41
ebreak_
static InstructionDefinition ebreak_(ISA32_RISCV64, "ebreak",(uint32_t) 0x100073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//ebreak\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "return ETISS_RETURNCODE_CPUFINISHED; \n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64::A7
etiss_uint64 A7
Definition: RISCV64.h:60
amoswap_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoswap_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoswap.w",(uint32_t) 0x800202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoswap.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
int32_t
signed int int32_t
Definition: stddef.h:15
uint16_t
unsigned short int uint16_t
Definition: stddef.h:22
mulw_rd_rs1_rs2
static InstructionDefinition mulw_rd_rs1_rs2(ISA32_RISCV64, "mulw",(uint32_t) 0x200003b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//mulw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) * (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff)); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
memset
__DEVICE__ void * memset(void *__a, int __b, size_t __c)
Definition: __clang_cuda_device_functions.h:1480
c_and_8_rd_8_rs2
static InstructionDefinition c_and_8_rd_8_rs2(ISA16_RISCV64, "c.and",(uint16_t) 0x8c61,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(9, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rd+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.and\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int8 rd_idx = 0;\n" "rd_idx = "+toString(rd)+" + 8;\n" "*((RISCV64*)cpu)->X[rd_idx] = (*((RISCV64*)cpu)->X[rd_idx] & *((RISCV64*)cpu)->X["+toString(rs2)+" + 8]);\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch::initCodeBlock
virtual void initCodeBlock(etiss::CodeBlock &cb) const
called before instructions are translated for the code block
Definition: RISCV64Arch.cpp:223
divuw_rd_rs1_rs2
static InstructionDefinition divuw_rd_rs1_rs2(ISA32_RISCV64, "divuw",(uint32_t) 0x200503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//divuw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(rd)+" != 0)\n" "{\n" "if((*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff) != 0)\n" "{\n" "etiss_int64 cast_0 = ((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff) / (*((RISCV64*)cpu)->X["+toString(rs2)+"] & 0xffffffff)); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "else\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = - 1;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
uint64_t
unsigned long long int uint64_t
Definition: stddef.h:27
ETISS_CPU::resources
const char * resources[ETISS_MAX_RESOURCES]
names of resources
Definition: CPU.h:99
flt_s_rd_frs1_frs2
static InstructionDefinition flt_s_rd_frs1_frs2(ISA32_RISCV64, "flt.s",(uint32_t) 0xa0001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//flt.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], (etiss_uint32)2);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_s(frs1, frs2, (etiss_uint32)2);\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = fcmp_s((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffff), (etiss_uint32)2);\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
amomax_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amomax_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amomax.w",(uint32_t) 0xa000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amomax.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "etiss_int64 cast_2 = res1; \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "if((etiss_int64)cast_2 < (etiss_int64)cast_1)\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res1;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
dii_
static InstructionDefinition dii_(ISA16_RISCV64, "dii",(uint16_t) 0x0,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//dii\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64::T6
etiss_uint64 T6
Definition: RISCV64.h:74
RISCV64::S11
etiss_uint64 S11
Definition: RISCV64.h:70
RISCV64::S6
etiss_uint64 S6
Definition: RISCV64.h:65
mulh_rd_rs1_rs2
static InstructionDefinition mulh_rd_rs1_rs2(ISA32_RISCV64, "mulh",(uint32_t) 0x2001033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//mulh\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 res = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "res = ((etiss_int64)cast_1 * (etiss_int64)cast_0);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)(res >> 64);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fle_d_rd_frs1_frs2
static InstructionDefinition fle_d_rd_frs1_frs2(ISA32_RISCV64, "fle.d",(uint32_t) 0xa2000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fle.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (etiss_uint32)1);\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::T5
etiss_uint64 T5
Definition: RISCV64.h:73
fsub_d_rd_frs1_frs2
static InstructionDefinition fsub_d_rd_frs1_frs2(ISA32_RISCV64, "fsub.d",(uint32_t) 0xa000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsub.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" "if("+toString(rm)+" < 7)\n" "{\n" "choose1 = ("+toString(rm)+" & 0xff);\n" "}\n" "else\n" "{\n" "choose1 = (((RISCV64*)cpu)->FCSR & 0xff);\n" "}\n" "res = fsub_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), choose1);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
c_fld_rd_uimm_8_rs1_
static InstructionDefinition c_fld_rd_uimm_8_rs1_(ISA16_RISCV64, "c.fld",(uint16_t) 0x2000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(6, 5);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;etiss_uint64 rd=0;static BitArrayRange R_rd_0(4, 2);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.fld\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+" + 8] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "res = MEM_offs;\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+" + 8] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+" + 8] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64Arch::newMMU
etiss::mm::MMU * newMMU(ETISS_CPU *cpu)
It is an interface to instanciate a Memory Management Unit.
Definition: RISCV64Arch.cpp:247
c_fldsp_rd_uimm_x2_
static InstructionDefinition c_fldsp_rd_uimm_x2_(ISA16_RISCV64, "c.fldsp",(uint16_t) 0x2002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 uimm=0;static BitArrayRange R_uimm_5(12, 12);etiss_uint64 uimm_5=R_uimm_5.read(ba);uimm+=uimm_5<< 5;static BitArrayRange R_uimm_3(6, 5);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(4, 2);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.fldsp\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "offs = *((RISCV64*)cpu)->X[2] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "res = MEM_offs;\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
RISCV64::S5
etiss_uint64 S5
Definition: RISCV64.h:64
sret_
static InstructionDefinition sret_(ISA32_RISCV64, "sret",(uint32_t) 0x10200073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//sret\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "((RISCV64*)cpu)->CSR[3088] = (((RISCV64*)cpu)->CSR[256] & 0x100)>>8;\n" "((RISCV64*)cpu)->CSR[256] ^= (((RISCV64*)cpu)->CSR[256] & 0x100);\n" "((RISCV64*)cpu)->CSR[256] ^= ((etiss_uint32)((((RISCV64*)cpu)->CSR[256] & 0x20)>>4)) ^ (((RISCV64*)cpu)->CSR[256] & 0x2);\n" "cpu->instructionPointer = ((RISCV64*)cpu)->CSR[321];\n" "((RISCV64*)cpu)->CSR[768]= ((RISCV64*)cpu)->CSR[256];\n" "((RISCV64*)cpu)->CSR[0]=((RISCV64*)cpu)->CSR[256];\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
andi_rd_rs1_imm
static InstructionDefinition andi_rd_rs1_imm(ISA32_RISCV64, "andi",(uint32_t) 0x7013,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//andi\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = ((etiss_int64)cast_0 & imm_extended);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::A4
etiss_uint64 A4
Definition: RISCV64.h:57
lhu_rd_imm_rs1_
static InstructionDefinition lhu_rd_imm_rs1_(ISA32_RISCV64, "lhu",(uint32_t) 0x5003,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_int64 imm=0;static BitArrayRange R_imm_0(31, 20);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lhu\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint16 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,2);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)MEM_offs;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
amoswap_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoswap_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoswap.d",(uint32_t) 0x800302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoswap.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if("+toString(rd)+" != 0)\n" "{\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "}\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
ETISS_CPU::cpuCycleTime_ps
etiss_uint64 cpuCycleTime_ps
frequency of the cpu. use to allign e.g. memory delays
Definition: CPU.h:103
c_ld_8_rd_uimm_8_rs1_
static InstructionDefinition c_ld_8_rd_uimm_8_rs1_(ISA16_RISCV64, "c.ld",(uint16_t) 0x6000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(9, 7);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 uimm=0;static BitArrayRange R_uimm_3(12, 10);etiss_uint64 uimm_3=R_uimm_3.read(ba);uimm+=uimm_3<< 3;static BitArrayRange R_uimm_6(6, 5);etiss_uint64 uimm_6=R_uimm_6.read(ba);uimm+=uimm_6<< 6;etiss_uint64 rd=0;static BitArrayRange R_rd_0(4, 2);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.ld\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+" + 8] + "+toString(uimm)+";\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+" + 8] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
csrrc_rd_csr_rs1
static InstructionDefinition csrrc_rd_csr_rs1(ISA32_RISCV64, "csrrc",(uint32_t) 0x3073,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 csr=0;static BitArrayRange R_csr_0(31, 20);etiss_uint64 csr_0=R_csr_0.read(ba);csr+=csr_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//csrrc\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 xrs1 = 0;\n" "etiss_int64 mAddr = 0;\n" "etiss_int64 writeMask = 0;\n" "etiss_int64 writeMaskU = 0;\n" "etiss_int64 sAddr = 0;\n" "etiss_int64 writeMaskS = 0;\n" "etiss_int64 uAddr = 0;\n" "etiss_uint64 xrd = 0;\n" "etiss_int64 writeMaskM = 0;\n" "xrd = ((RISCV64*)cpu)->CSR["+toString(csr)+"];\n" "xrs1 = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = xrd;\n" "}\n" "if("+toString(rs1)+" != 0)\n" "{\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((xrd & ~xrs1) & writeMask))&0xffffffffffffffff&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = (xrd & ~xrs1)&0xffffffffffffffff;\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::Plugin
base plugin class that provides access to different plugin functions if present
Definition: Plugin.h:76
uint64
etiss_uint64 uint64
Definition: 386-GCC.h:82
etiss_uint64
uint64_t etiss_uint64
Definition: types.h:96
fsgnjx_d_rd_frs1_frs2
static InstructionDefinition fsgnjx_d_rd_frs1_frs2(ISA32_RISCV64, "fsgnjx.d",(uint32_t) 0x22002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsgnjx.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 ONE = 0;\n" "etiss_int64 upper = 0;\n" "etiss_int64 MSK1 = 0;\n" "ONE = 1;\n" "MSK1 = (ONE << 63);\n" "res = ((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff) ^ ((((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff) & MSK1));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fsgnjn_s_rd_frs1_frs2
static InstructionDefinition fsgnjn_s_rd_frs1_frs2(ISA32_RISCV64, "fsgnjn.s",(uint32_t) 0x20001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsgnjn.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((((RISCV64*)cpu)->F["+toString(rs1)+"] & 2147483647) | (~((RISCV64*)cpu)->F["+toString(rs2)+"] & -2147483648))&0xffffffffffffffff;\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "res = ((frs1 & 2147483647) | (~frs2 & -2147483648))&0xffffffff;\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fmin_d_rd_frs1_frs2
static InstructionDefinition fmin_d_rd_frs1_frs2(ISA32_RISCV64, "fmin.d",(uint32_t) 0x2a000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fmin.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "res = fsel_d((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff), (etiss_uint32)0);\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::Configuration::get
T get(const std::string &key, T default_, bool *default_used=0)
template function to read the value of a configuration key.
Definition: Misc.h:349
amomin_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amomin_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amomin.w",(uint32_t) 0x8000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amomin.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "etiss_uint64 choose1 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "etiss_int64 cast_2 = res1; \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "if((etiss_int64)cast_2 > (etiss_int64)cast_1)\n" "{\n" "choose1 = *((RISCV64*)cpu)->X["+toString(rs2)+"];\n" "}\n" "else\n" "{\n" "choose1 = res1;\n" "}\n" "res2 = choose1;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
lr_d_rd_rs1
static InstructionDefinition lr_d_rd_rs1(ISA32_RISCV64, "lr.d",(uint32_t) 0x1000302f,(uint32_t) 0xf9f0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//lr.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "((RISCV64*)cpu)->RES = offs;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
csrrs_rd_csr_rs1
static InstructionDefinition csrrs_rd_csr_rs1(ISA32_RISCV64, "csrrs",(uint32_t) 0x2073,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 csr=0;static BitArrayRange R_csr_0(31, 20);etiss_uint64 csr_0=R_csr_0.read(ba);csr+=csr_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//csrrs\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 xrs1 = 0;\n" "etiss_int64 mAddr = 0;\n" "etiss_int64 writeMask = 0;\n" "etiss_int64 writeMaskU = 0;\n" "etiss_int64 sAddr = 0;\n" "etiss_int64 writeMaskS = 0;\n" "etiss_int64 uAddr = 0;\n" "etiss_uint64 xrd = 0;\n" "etiss_int64 writeMaskM = 0;\n" "xrd = ((RISCV64*)cpu)->CSR["+toString(csr)+"];\n" "xrs1 = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = xrd;\n" "}\n" "if("+toString(rs1)+" != 0)\n" "{\n" "if((("+toString(csr)+" == 0) || ("+toString(csr)+" == 256)) || ("+toString(csr)+" == 768))\n" "{\n" "uAddr = 0;\n" "sAddr = 256;\n" "mAddr = 768;\n" "writeMaskM = -9223372036846388805;\n" "writeMaskS = -9223372036853866189;\n" "writeMaskU = -9223372036853866479;\n" "}\n" "if((("+toString(csr)+" == 68) || ("+toString(csr)+" == 324)) || ("+toString(csr)+" == 836))\n" "{\n" "uAddr = 68;\n" "sAddr = 324;\n" "mAddr = 836;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if((("+toString(csr)+" == 4) || ("+toString(csr)+" == 260)) || ("+toString(csr)+" == 772))\n" "{\n" "uAddr = 4;\n" "sAddr = 260;\n" "mAddr = 772;\n" "writeMaskM = 3003;\n" "writeMaskS = 819;\n" "writeMaskU = 273;\n" "}\n" "if(uAddr != sAddr)\n" "{\n" "if(((RISCV64*)cpu)->CSR[3088] == 3)\n" "{\n" "writeMask = writeMaskM;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" "}\n" "if(((RISCV64*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" "}\n" "((RISCV64*)cpu)->CSR[uAddr] = ((((RISCV64*)cpu)->CSR[uAddr] & ~writeMask) | ((xrd | xrs1) & writeMask))&0xffffffffffffffff;\n" "((RISCV64*)cpu)->CSR[sAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "((RISCV64*)cpu)->CSR[mAddr] = ((RISCV64*)cpu)->CSR[uAddr];\n" "}\n" "else\n" "{\n" "((RISCV64*)cpu)->CSR["+toString(csr)+"] = (xrd | xrs1);\n" "}\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fcvt_s_wu_rd_rs1
static InstructionDefinition fcvt_s_wu_rd_rs1(ISA32_RISCV64, "fcvt.s.wu",(uint32_t) 0xd0100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.s.wu\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" "if(64 == 32)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = fcvt_s((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff), (etiss_uint32)3, ("+toString(rm)+" & 0xff));\n" "}\n" "else\n" "{\n" "res = fcvt_s((*((RISCV64*)cpu)->X["+toString(rs1)+"] & 0xffffffff), (etiss_uint32)3, ("+toString(rm)+" & 0xff));\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 32) | (etiss_uint64)res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64Arch.h
etiss_int64
int64_t etiss_int64
Definition: types.h:95
fclass_s_rd_frs1
static InstructionDefinition fclass_s_rd_frs1(ISA32_RISCV64, "fclass.s",(uint32_t) 0xe0001053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fclass.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = fclass_s(unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]));\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
fsgnj_d_rd_frs1_frs2
static InstructionDefinition fsgnj_d_rd_frs1_frs2(ISA32_RISCV64, "fsgnj.d",(uint32_t) 0x22000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsgnj.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 res = 0;\n" "etiss_int64 ONE = 0;\n" "etiss_int64 upper = 0;\n" "etiss_int64 MSK1 = 0;\n" "etiss_int64 MSK2 = 0;\n" "ONE = 1;\n" "MSK1 = (ONE << 63);\n" "MSK2 = MSK1 - 1;\n" "res = (((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff) & MSK2) | ((((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff) & MSK1));\n" "if(64 == 64)\n" "{\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = res;\n" "}\n" "else\n" "{\n" "upper = - 1;\n" "((RISCV64*)cpu)->F["+toString(rd)+"] = ((upper << 64) | res);\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
etiss::mm::MM_ACCESS
MM_ACCESS
Definition: PageFaultVector.h:62
c_addi4spn_rd_imm
static InstructionDefinition c_addi4spn_rd_imm(ISA16_RISCV64, "c.addi4spn",(uint16_t) 0x0,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rd=0;static BitArrayRange R_rd_0(4, 2);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 imm=0;static BitArrayRange R_imm_4(12, 11);etiss_uint64 imm_4=R_imm_4.read(ba);imm+=imm_4<< 4;static BitArrayRange R_imm_6(10, 7);etiss_uint64 imm_6=R_imm_6.read(ba);imm+=imm_6<< 6;static BitArrayRange R_imm_2(6, 6);etiss_uint64 imm_2=R_imm_2.read(ba);imm+=imm_2<< 2;static BitArrayRange R_imm_3(5, 5);etiss_uint64 imm_3=R_imm_3.read(ba);imm+=imm_3<< 3;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[2], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.addi4spn\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "if("+toString(imm)+" == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+" + 8] = *((RISCV64*)cpu)->X[2] + "+toString(imm)+";\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
amoxor_w_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoxor_w_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoxor.w",(uint32_t) 0x2000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoxor.w\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res1 = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "etiss_int32 cast_0 = MEM_offs; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "res1 = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res1;\n" "}\n" "res2 = (res1 ^ *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" "if((offs + 4 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
fcvt_w_d_rd_frs1
static InstructionDefinition fcvt_w_d_rd_frs1(ISA32_RISCV64, "fcvt.w.d",(uint32_t) 0xc2000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rm=0;static BitArrayRange R_rm_0(14, 12);etiss_uint64 rm_0=R_rm_0.read(ba);rm+=rm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fcvt.w.d\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_int32 cast_0 = fcvt_64_32((((RISCV64*)cpu)->F["+toString(rs1)+"] & 0xffffffffffffffff), (etiss_uint32)0, ("+toString(rm)+" & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_int64)cast_0;\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
wfi_
static InstructionDefinition wfi_(ISA32_RISCV64, "wfi",(uint32_t) 0x10500073,(uint32_t) 0xffffffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//wfi\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "return ETISS_RETURNCODE_CPUFINISHED; \n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
etiss::CodeBlock
A list of CodeSets.
Definition: CodePart.h:569
blt_rs1_rs2_imm
static InstructionDefinition blt_rs1_rs2_imm(ISA32_RISCV64, "blt",(uint32_t) 0x4063,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_12(31, 31);etiss_int64 imm_12=R_imm_12.read(ba);imm+=imm_12<< 12;static BitArrayRange R_imm_5(30, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_1(11, 8);etiss_int64 imm_1=R_imm_1.read(ba);imm+=imm_1<< 1;static BitArrayRange R_imm_11(7, 7);etiss_int64 imm_11=R_imm_11.read(ba);imm+=imm_11<< 11;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//blt\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 imm_extended = 0;\n" "etiss_int64 choose1 = 0;\n" "if(("+toString(imm)+" & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294959104;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs2)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "etiss_int64 cast_1 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_1 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_1 =0x0 + (etiss_uint64)cast_1 ;\n" "}\n" "if((etiss_int64)cast_1 < (etiss_int64)cast_0)\n" "{\n" "etiss_int64 cast_2 = "+toString((uint64_t) ic.current_address_)+"ULL ; \n" "if((etiss_int64)((etiss_uint64)cast_2 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_2 =0x0 + (etiss_uint64)cast_2 ;\n" "}\n" "choose1 = (etiss_int64)cast_2 + imm_extended;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "}\n" "else\n" "{\n" "choose1 = "+toString((uint64_t) ic.current_address_)+"ULL + 4;\n" "}\n" "cpu->instructionPointer = choose1;\n" "cpu->instructionPointer = (uint64_t)cpu->instructionPointer; \n" "return 0;\n" ;return true;}, 0, nullptr)
RISCV64::S0
etiss_uint64 S0
Definition: RISCV64.h:51
etiss::instr
Definition: ClassDefs.h:61
RISCV64Arch::getHeaders
virtual const std::set< std::string > & getHeaders() const
required headers (RISCV64.h)
Definition: RISCV64Arch.cpp:218
amoand_d_rd_rs1_rs2_aqu_aq_rel_rl_
static InstructionDefinition amoand_d_rd_rs1_rs2_aqu_aq_rel_rl_(ISA32_RISCV64, "amoand.d",(uint32_t) 0x6000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 aq=0;static BitArrayRange R_aq_0(26, 26);etiss_uint64 aq_0=R_aq_0.read(ba);aq+=aq_0;etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;etiss_uint64 rl=0;static BitArrayRange R_rl_0(25, 25);etiss_uint64 rl_0=R_rl_0.read(ba);rl+=rl_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//amoand.d\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint64 offs = 0;\n" "etiss_int64 res = 0;\n" "etiss_uint64 res2 = 0;\n" "offs = *((RISCV64*)cpu)->X["+toString(rs1)+"];\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "etiss_int64 cast_0 = MEM_offs; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "res = (etiss_int64)cast_0;\n" "if("+toString(rd)+" != 0)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = res;\n" "}\n" "res2 = (res & *((RISCV64*)cpu)->X["+toString(rs2)+"]);\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
ETISS_CPU::cycles
etiss_uint64 cycles[ETISS_MAX_RESOURCES]
how many cycles in each resource (including waiting)
Definition: CPU.h:101
RISCV64::T3
etiss_uint64 T3
Definition: RISCV64.h:71
RISCV64::S10
etiss_uint64 S10
Definition: RISCV64.h:69
fsd_rs2_imm_rs1_
static InstructionDefinition fsd_rs2_imm_rs1_(ISA32_RISCV64, "fsd",(uint32_t) 0x3027,(uint32_t) 0x707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_int64 imm=0;static BitArrayRange R_imm_5(31, 25);etiss_int64 imm_5=R_imm_5.read(ba);imm+=imm_5<< 5;static BitArrayRange R_imm_0(11, 7);etiss_int64 imm_0=R_imm_0.read(ba);imm+=imm_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rs1], 64);partInit.getRegisterDependencies().add(reg_name[rs2], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//fsd\n")+"etiss_uint32 exception = 0;\n" "etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_int64 offs = 0;\n" "etiss_int64 imm_extended = 0;\n" "if(("+toString(imm)+" & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" "}\n" "else\n" "{\n" "imm_extended = 4294967295;\n" "imm_extended = (imm_extended << 32);\n" "imm_extended = imm_extended + 4294963200;\n" "}\n" "imm_extended = imm_extended + "+toString(imm)+";\n" "etiss_int64 cast_0 = *((RISCV64*)cpu)->X["+toString(rs1)+"]; \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint64)cast_0 ;\n" "}\n" "offs = (etiss_int64)cast_0 + imm_extended;\n" "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV64*)cpu)->F["+toString(rs2)+"] & 0xffffffffffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" "if((offs + 8 > ((RISCV64*)cpu)->RES) && (offs < 8 + ((RISCV64*)cpu)->RES))\n" "{\n" "((RISCV64*)cpu)->RES = 0;\n" "}\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" "return exception;\n" ;return true;}, 0, nullptr)
c_subw_8_rd_8_rd_8_rs2
static InstructionDefinition c_subw_8_rd_8_rd_8_rs2(ISA16_RISCV64, "c.subw",(uint16_t) 0x9c01,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(4, 2);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(9, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getRegisterDependencies().add(reg_name[rd+8], 64);partInit.getRegisterDependencies().add(reg_name[rs2+8], 64);partInit.getAffectedRegisters().add(reg_name[rd+8], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//c.subw\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 res = 0;\n" "res = (*((RISCV64*)cpu)->X["+toString(rd)+" + 8] & 0xffffffff) - (*((RISCV64*)cpu)->X["+toString(rs2)+" + 8] & 0xffffffff);\n" "etiss_int32 cast_0 = res; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" "cast_0 =0x0 + (etiss_uint32)cast_0 ;\n" "}\n" "*((RISCV64*)cpu)->X["+toString(rd)+" + 8] = (etiss_int64)cast_0;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+2))+"ULL; \n" ;return true;}, 0, nullptr)
feq_s_rd_frs1_frs2
static InstructionDefinition feq_s_rd_frs1_frs2(ISA32_RISCV64, "feq.s",(uint32_t) 0xa0002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint64 rs2=0;static BitArrayRange R_rs2_0(24, 20);etiss_uint64 rs2_0=R_rs2_0.read(ba);rs2+=rs2_0;etiss_uint64 rs1=0;static BitArrayRange R_rs1_0(19, 15);etiss_uint64 rs1_0=R_rs1_0.read(ba);rs1+=rs1_0;etiss_uint64 rd=0;static BitArrayRange R_rd_0(11, 7);etiss_uint64 rd_0=R_rd_0.read(ba);rd+=rd_0;CodePart &partInit=cs.append(CodePart::INITIALREQUIRED);partInit.getAffectedRegisters().add(reg_name[rd], 64);partInit.getAffectedRegisters().add("instructionPointer", 64);partInit.code()=std::string("//feq.s\n")+"etiss_uint32 temp = 0;\n" "etiss_uint8 * tmpbuf = (etiss_uint8 *)&temp;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "if(64 == 32)\n" "{\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_s(((RISCV64*)cpu)->F["+toString(rs1)+"], ((RISCV64*)cpu)->F["+toString(rs2)+"], (etiss_uint32)0);\n" "}\n" "else\n" "{\n" "frs1 = unbox_s(((RISCV64*)cpu)->F["+toString(rs1)+"]);\n" "frs2 = unbox_s(((RISCV64*)cpu)->F["+toString(rs2)+"]);\n" "*((RISCV64*)cpu)->X["+toString(rd)+"] = (etiss_uint64)fcmp_s(frs1, frs2, (etiss_uint32)0);\n" "}\n" "flags = fget_flags();\n" "((RISCV64*)cpu)->FCSR = (((RISCV64*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" "cpu->instructionPointer = "+toString((uint64_t)(ic.current_address_+4))+"ULL; \n" ;return true;}, 0, nullptr)
RISCV64::X
etiss_uint64 * X[32]
Definition: RISCV64.h:75
RISCV64::T0
etiss_uint64 T0
Definition: RISCV64.h:48
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